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改进M4分频算法，自动计算PLL_Q，以适应不同晶振

This commit is contained in:
大石头 2017-04-22 13:23:56 +08:00
parent 46d9b83071
commit 16e0ef2985
2 changed files with 12 additions and 12 deletions
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5
Platform/CortexM/Sys.cpp
View File

@ -111,7 +111,7 @@ INROOT void TSys::OnInit()
//if (IsGD && (DevID == 0x0430 || DevID == 0x0414)) Clock = 120000000; //if (IsGD && (DevID == 0x0430 || DevID == 0x0414)) Clock = 120000000;
if (IsGD) Clock = 120000000; if (IsGD) Clock = 120000000;
#elif defined(STM32F4) #elif defined(STM32F4)
//if (IsGD) Clock = 200000000; if (IsGD) Clock = 200000000;
#endif #endif
_Index = 0; _Index = 0;
@ -137,9 +137,6 @@ INROOT void TSys::OnInit()
} }
} }
RAMSize = RamSizes[_Index]; RAMSize = RamSizes[_Index];
#if defined(STM32F4)
//if (IsGD) RAMSize <<= 1;
#endif
} }
InitHeapStack(StackTop()); InitHeapStack(StackTop());

19
Platform/STM32F4/Boot_F4.cpp
View File

@ -88,20 +88,23 @@ extern "C"
SYSCLK = PLL_VCO / PLL_P SYSCLK = PLL_VCO / PLL_P
USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ
*/ */
PLL_N = clock / 1000000; int n = clock / 1000000;
PLL_M = cystalClock / 1000000; // 为了让它除到1 PLL_M = cystalClock / 1000000; // 为了让它除到1
PLL_P = 2; // 这是分母，可用2/4/6，在系统主频不变的情况下，可以加倍扩大PLL_VC0以获取48M PLL_P = 2; // 这是分母，可用2/4/6，在系统主频不变的情况下，可以加倍扩大PLL_VC0以获取48M
PLL_N *= PLL_P; PLL_N = n * PLL_P;
// 168M分不出48M，向上加倍吧，恰巧336M可以 /*// 168M分不出48M，向上加倍吧，恰巧336M可以
while(PLL_N % 48 != 0) while(PLL_N % 48 != 0)
{ {
PLL_P += 2; PLL_P += 2;
assert_param(PLL_P >=2 && PLL_P <= 6); assert_param(PLL_P >=2 && PLL_P <= 8);
PLL_N *= PLL_P; PLL_N = n * PLL_P;
} }
PLL_Q = PLL_N / 48; // USB等需要48M PLL_Q = PLL_N / 48; // USB等需要48M*/
RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | PLL_Q = 0;
(RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); for(int usb=0; usb<PLL_N; usb+=48) PLL_Q++;
/*RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
(RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);*/
RCC_PLLConfig(RCC_PLLCFGR_PLLSRC_HSE, PLL_M, PLL_N, PLL_P, PLL_Q);
/* Enable the main PLL */ /* Enable the main PLL */
RCC->CR |= RCC_CR_PLLON; RCC->CR |= RCC_CR_PLLON;