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v2.6.2014.0823 平台文件独立，接管系统初始化控制权

This commit is contained in:
Stone 2014-08-22 16:02:51 +00:00
parent 45d1f07e59
commit 7a13fdcd7d
13 changed files with 221 additions and 7 deletions
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4
ADC.h
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@ -1,10 +1,8 @@
#ifndef __ADC_H__
#define __ADC_H__
#include "Pin.h"
//#include "Port.h"
#include "DMA.h"
#include "Sys.h"
#include "DMA.h"
/*
Analog-to-digital converter

194
Platform/Boot_F0.cpp Normal file
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@ -0,0 +1,194 @@
#include "stm32.h"
static void SetSysClock(void);
uint32_t SystemCoreClock = 48000000;
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
void SystemInit (void)
{
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001;
/* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
RCC->CFGR &= (uint32_t)0xF8FFB80C;
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF;
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
/* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
RCC->CFGR &= (uint32_t)0xFFC0FFFF;
/* Reset PREDIV1[3:0] bits */
RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
/* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */
RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;
/* Reset HSI14 bit */
RCC->CR2 &= (uint32_t)0xFFFFFFFE;
/* Disable all interrupts */
RCC->CIR = 0x00000000;
/* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */
SetSysClock();
}
/**
* @brief Update SystemCoreClock according to Clock Register Values
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
*
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
*
* (*) HSI_VALUE is a constant defined in stm32f0xx.h file (default value
* 8 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (**) HSE_VALUE is a constant defined in stm32f0xx.h file (default value
* 8 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
* @param None
* @retval None
*/
void SystemCoreClockUpdate (void)
{
uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
switch (tmp)
{
case 0x00: /* HSI used as system clock */
SystemCoreClock = HSI_VALUE;
break;
case 0x04: /* HSE used as system clock */
SystemCoreClock = HSE_VALUE;
break;
case 0x08: /* PLL used as system clock */
/* Get PLL clock source and multiplication factor ----------------------*/
pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
pllmull = ( pllmull >> 18) + 2;
if (pllsource == 0x00)
{
/* HSI oscillator clock divided by 2 selected as PLL clock entry */
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
}
else
{
prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
/* HSE oscillator clock selected as PREDIV1 clock entry */
SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
}
break;
default: /* HSI used as system clock */
SystemCoreClock = HSI_VALUE;
break;
}
/* Compute HCLK clock frequency ----------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
/* HCLK clock frequency */
SystemCoreClock >>= tmp;
}
/**
* @brief Configures the System clock frequency, AHB/APBx prescalers and Flash
* settings.
* @note This function should be called only once the RCC clock configuration
* is reset to the default reset state (done in SystemInit() function).
* @param None
* @retval None
*/
static void SetSysClock(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
uint32_t mull, pll;
/* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/
/* Enable HSE */
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CR & RCC_CR_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
/* Enable Prefetch Buffer and set Flash Latency */
FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;
/* HCLK = SYSCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
/* PCLK = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;
/* PLL configuration = HSE * 6 = 48 MHz */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
//RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL6);
// Ö§³Ö¶àÖÖ±¶Æµ
mull = SystemCoreClock / 8000000;
pll = ((mull - 2) * 4) << 16;
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | pll);
SystemCoreClock = 8000000 * mull;
/* Enable PLL */
RCC->CR |= RCC_CR_PLLON;
/* Wait till PLL is ready */
while((RCC->CR & RCC_CR_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
{
}
}
else
{ /* If HSE fails to start-up, the application will have wrong clock
configuration. User can add here some code to deal with this error */
}
}

0
Pin.h → Platform/Pin.h
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0
Pin_STM32F0.h → Platform/Pin_STM32F0.h
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0
Pin_STM32F1.h → Platform/Pin_STM32F1.h
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0
Pin_STM32F4.h → Platform/Pin_STM32F4.h
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0
startup_stm32f0xx.s → Platform/startup_stm32f0xx.s
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0
startup_stm32f0xx_x4.s → Platform/startup_stm32f0xx_x4.s
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0
startup_stm32f10x_hd.s → Platform/startup_stm32f10x_hd.s
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0
startup_stm32f4xx.s → Platform/startup_stm32f4xx.s
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0
stm32.h → Platform/stm32.h
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25
Sys.cpp
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@ -429,7 +429,7 @@ void TSys::Init(void)
RCC_ClocksTypeDef clock;
RCC_GetClocksFreq(&clock);
#if defined(GD32) && defined(STM32F10X) || defined(STM32F4)
#if defined(GD32) && defined(STM32F1) || defined(STM32F4)
// 如果当前频率不等于配置，则重新配置时钟
if(Clock != clock.SYSCLK_Frequency || CystalClock != HSE_VALUE) Bootstrap();
#ifdef STM32F4
@ -437,6 +437,15 @@ void TSys::Init(void)
#endif
RCC_GetClocksFreq(&clock);
Clock = clock.SYSCLK_Frequency;
#elif defined(STM32F0)
// 如果当前频率不等于配置，则重新配置时钟
if(Clock != clock.SYSCLK_Frequency)
{
SystemCoreClock = Clock;
SystemInit();
}
RCC_GetClocksFreq(&clock);
Clock = clock.SYSCLK_Frequency;
#else
Clock = clock.SYSCLK_Frequency;
#endif
@ -474,7 +483,19 @@ void TSys::ShowInfo()
ST_CPUID* cpu = (ST_CPUID*)&CPUID;
if(DevID > 0)
{
if(DevID == 0x410 || DevID == 0x412 || DevID == 0x414 || DevID == 0x430)
if(DevID == 0x410)
{
if(IsGD && RevID == 0x1303)
{
if(Clock == 48000000)
debug_printf("F130");
else
debug_printf("F150");
}
else
debug_printf("F103");
}
else if(DevID == 0x412 || DevID == 0x414 || DevID == 0x430)
debug_printf("F103");
else if(DevID == 0x418)
debug_printf("F107");

5
Sys.h
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@ -4,7 +4,7 @@
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "stm32.h"
#include "Platform/stm32.h"
/* 类型定义 */
typedef char sbyte;
@ -32,7 +32,7 @@ typedef char* String;
/* 引脚定义 */
//typedef ushort Pin;
#include "Pin.h"
#include "Platform/Pin.h"
/* 串口定义 */
#define COM1 0
@ -145,6 +145,7 @@ __inline void debug_printf( const char *format, ... ) {}
#endif //_Sys_H_
/*
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