104 lines
2.9 KiB
C++
104 lines
2.9 KiB
C++
#include "stm32.h"
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extern "C"
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{
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uint32_t SystemCoreClock = 48000000;
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__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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void SystemInit(void)
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{
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SystemCoreClock = 48000000;
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/* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */
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SetSysClock(SystemCoreClock, 8000000);
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SYSCFG_MemoryRemapConfig(SYSCFG_MemoryRemap_Flash);
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}
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void SetSysClock(unsigned int clock, unsigned int cystalClock)
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{
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__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
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uint32_t mull, pll;
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/* Set HSION bit */
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RCC->CR |= (uint32_t)0x00000001;
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/* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
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RCC->CFGR &= (uint32_t)0xF8FFB80C;
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/* Reset HSEON, CSSON and PLLON bits */
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RCC->CR &= (uint32_t)0xFEF6FFFF;
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/* Reset HSEBYP bit */
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RCC->CR &= (uint32_t)0xFFFBFFFF;
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/* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
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RCC->CFGR &= (uint32_t)0xFFC0FFFF;
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/* Reset PREDIV1[3:0] bits */
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RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
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/* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */
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RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;
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/* Reset HSI14 bit */
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RCC->CR2 &= (uint32_t)0xFFFFFFFE;
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/* Disable all interrupts */
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RCC->CIR = 0x00000000;
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/* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/
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/* Enable HSE */
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RCC->CR |= ((uint32_t)RCC_CR_HSEON);
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/* Wait till HSE is ready and if Time out is reached exit */
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do
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{
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HSEStatus = RCC->CR & RCC_CR_HSERDY;
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StartUpCounter++;
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} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
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if ((RCC->CR & RCC_CR_HSERDY) != RESET)
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{
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HSEStatus = (uint32_t)0x01;
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}
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else
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{
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HSEStatus = (uint32_t)0x00;
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}
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if (HSEStatus != (uint32_t)0x01) return;
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/* Enable Prefetch Buffer and set Flash Latency */
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FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;
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/* HCLK = SYSCLK */
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RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
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/* PCLK = HCLK */
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RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;
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/* PLL configuration = HSE * 6 = 48 MHz */
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RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
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//RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL6);
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// 支持多种倍频
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mull = clock / cystalClock;
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pll = ((mull - 2) * 4) << 16;
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RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | pll);
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//SystemCoreClock = cystalClock * mull;
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/* Enable PLL */
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RCC->CR |= RCC_CR_PLLON;
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/* Wait till PLL is ready */
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while((RCC->CR & RCC_CR_PLLRDY) == 0) { }
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/* Select PLL as system clock source */
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RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
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RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
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/* Wait till PLL is used as system clock source */
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while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL) { }
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}
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}
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