211 lines
7.1 KiB
C++
211 lines
7.1 KiB
C++
#include "stm32.h"
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extern "C"
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{
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/*!< Uncomment the following line if you need to relocate your vector Table in
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Internal SRAM. */
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/* #define VECT_TAB_SRAM */
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#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
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This value must be a multiple of 0x200. */
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uint32_t HSE_VALUE = 8000000;
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uint32_t SystemCoreClock = 72000000;
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__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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void SystemInit (void)
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{
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HSE_VALUE = 8000000;
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SystemCoreClock = 72000000;
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/* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */
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SetSysClock(SystemCoreClock, HSE_VALUE);
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}
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void SetSysClock(unsigned int clock, unsigned int cystalClock)
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{
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__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
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uint32_t mull, mull2;
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/* Reset the RCC clock configuration to the default reset state(for debug purpose) */
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/* Set HSION bit */
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RCC->CR |= (uint32_t)0x00000001;
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/* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
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#ifndef STM32F10X_CL
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RCC->CFGR &= (uint32_t)0xF8FF0000;
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#else
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RCC->CFGR &= (uint32_t)0xF0FF0000;
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#endif /* STM32F10X_CL */
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/* Reset HSEON, CSSON and PLLON bits */
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RCC->CR &= (uint32_t)0xFEF6FFFF;
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/* Reset HSEBYP bit */
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RCC->CR &= (uint32_t)0xFFFBFFFF;
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/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
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RCC->CFGR &= (uint32_t)0xFF80FFFF;
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#ifdef STM32F10X_CL
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/* Reset PLL2ON and PLL3ON bits */
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RCC->CR &= (uint32_t)0xEBFFFFFF;
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/* Disable all interrupts and clear pending bits */
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RCC->CIR = 0x00FF0000;
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/* Reset CFGR2 register */
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RCC->CFGR2 = 0x00000000;
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#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
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/* Disable all interrupts and clear pending bits */
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RCC->CIR = 0x009F0000;
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/* Reset CFGR2 register */
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RCC->CFGR2 = 0x00000000;
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#else
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/* Disable all interrupts and clear pending bits */
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RCC->CIR = 0x009F0000;
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#endif /* STM32F10X_CL */
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#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
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#ifdef DATA_IN_ExtSRAM
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SystemInit_ExtMemCtl();
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#endif /* DATA_IN_ExtSRAM */
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#endif
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/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
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/* Enable HSE */
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RCC->CR |= ((uint32_t)RCC_CR_HSEON);
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/* Wait till HSE is ready and if Time out is reached exit */
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do
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{
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HSEStatus = RCC->CR & RCC_CR_HSERDY;
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StartUpCounter++;
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} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
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if ((RCC->CR & RCC_CR_HSERDY) != RESET)
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HSEStatus = (uint32_t)0x01;
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else
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HSEStatus = (uint32_t)0x00;
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if (HSEStatus == (uint32_t)0x01)
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{
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/* Enable Prefetch Buffer */
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FLASH->ACR |= FLASH_ACR_PRFTBE;
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/* Flash 2 wait state */
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FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
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FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
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/* HCLK = SYSCLK */
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RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
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/* PCLK2 = HCLK */
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RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
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/* PCLK1 = HCLK */
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RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
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#ifdef STM32F10X_CL
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/* Configure PLLs ------------------------------------------------------*/
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/* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
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/* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
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RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
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RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
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RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
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RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
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/* Enable PLL2 */
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RCC->CR |= RCC_CR_PLL2ON;
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/* Wait till PLL2 is ready */
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while((RCC->CR & RCC_CR_PLL2RDY) == 0) { }
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/* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
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RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
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RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
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RCC_CFGR_PLLMULL9);
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#else
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/* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
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RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
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RCC_CFGR_PLLMULL));
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//RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
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// 支持超频，主频必须是8M的倍频
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mull = clock / cystalClock;
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mull2 = (mull - 2) << 18;
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// 处理0.5倍频
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if( (mull * cystalClock + cystalClock / 2) == clock )
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{
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mull = 2 * clock / cystalClock;
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mull2 = (mull - 2 ) << 18 | RCC_CFGR_PLLXTPRE_HSE_Div2;
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}
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RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | mull2);
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#endif /* STM32F10X_CL */
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/* Enable PLL */
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RCC->CR |= RCC_CR_PLLON;
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/* Wait till PLL is ready */
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while((RCC->CR & RCC_CR_PLLRDY) == 0) { }
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/* Select PLL as system clock source */
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RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
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RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
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/* Wait till PLL is used as system clock source */
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while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) { }
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}
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/* Configure the Vector Table location add offset address ------------------*/
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#ifdef VECT_TAB_SRAM
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SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
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#else
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SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
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#endif
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}
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#if !VEC_TABLE_ON_RAM
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/*void NMI_Handler() { FaultHandler(); }
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void HardFault_Handler() { FaultHandler(); }
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void MemManage_Handler() { FaultHandler(); }
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void BusFault_Handler() { FaultHandler(); }
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void UsageFault_Handler() { FaultHandler(); }*/
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/*void SVC_Handler() { UserHandler(); }
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void DebugMon_Handler() { UserHandler(); }
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void PendSV_Handler() { UserHandler(); }
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void SysTick_Handler() { UserHandler(); }
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void WWDG_IRQHandler() { UserHandler(); }
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void PVD_IRQHandler() { UserHandler(); }
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void RTC_IRQHandler() { UserHandler(); }
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void FLASH_IRQHandler() { UserHandler(); }
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void RCC_IRQHandler() { UserHandler(); }
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void EXTI0_1_IRQHandler() { UserHandler(); }
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void EXTI2_3_IRQHandler() { UserHandler(); }
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void EXTI4_15_IRQHandler() { UserHandler(); }
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void TS_IRQHandler() { UserHandler(); }
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void DMA1_Channel1_IRQHandler() { UserHandler(); }
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void DMA1_Channel2_3_IRQHandler() { UserHandler(); }
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void DMA1_Channel4_5_IRQHandler() { UserHandler(); }
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void ADC1_COMP_IRQHandler() { UserHandler(); }
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void TIM1_BRK_UP_TRG_COM_IRQHandler() { UserHandler(); }
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void TIM1_CC_IRQHandler() { UserHandler(); }
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void TIM2_IRQHandler() { UserHandler(); }
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void TIM3_IRQHandler() { UserHandler(); }
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void TIM6_DAC_IRQHandler() { UserHandler(); }
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void TIM14_IRQHandler() { UserHandler(); }
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void TIM15_IRQHandler() { UserHandler(); }
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void TIM16_IRQHandler() { UserHandler(); }
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void TIM17_IRQHandler() { UserHandler(); }
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void I2C1_IRQHandler() { UserHandler(); }
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void I2C2_IRQHandler() { UserHandler(); }
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void SPI1_IRQHandler() { UserHandler(); }
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void SPI2_IRQHandler() { UserHandler(); }
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void USART1_IRQHandler() { UserHandler(); }
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void USART2_IRQHandler() { UserHandler(); }
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void CEC_IRQHandler() { UserHandler(); }*/
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#endif
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}
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