454 lines
13 KiB
C++
454 lines
13 KiB
C++
#include "Enc28j60.h"
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#define ENC_DEBUG 0
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Enc28j60::Enc28j60() { Init(); }
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Enc28j60::Enc28j60(Spi* spi, Pin ce/*, Pin irq*/)
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{
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//_spi = spi;
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//_ce = NULL;
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//if(ce != P0) _ce = new OutputPort(ce, false, false);
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Init();
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Init(spi, ce);
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}
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Enc28j60::~Enc28j60()
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{
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delete _spi;
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_spi = NULL;
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/*if(_ce) delete _ce;
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_ce = NULL;*/
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}
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void Enc28j60::Init()
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{
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_spi = NULL;
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}
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void Enc28j60::Init(Spi* spi, Pin ce)
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{
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_spi = spi;
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if(ce != P0)
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{
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_ce.OpenDrain = false;
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_ce.Set(ce);
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}
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}
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byte Enc28j60::ReadOp(byte op, byte addr)
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{
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SpiScope sc(_spi);
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_spi->Write(op | (addr & ADDR_MASK));
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byte dat = _spi->Write(0xFF);
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// do dummy read if needed (for mac and mii, see datasheet page 29)
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if(addr & 0x80)
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{
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dat = _spi->Write(0xFF);
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}
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return dat;
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}
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void Enc28j60::WriteOp(byte op, byte addr, byte data)
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{
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SpiScope sc(_spi);
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_spi->Write(op | (addr & ADDR_MASK));
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_spi->Write(data);
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}
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void Enc28j60::ReadBuffer(byte* buf, uint len)
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{
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SpiScope sc(_spi);
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_spi->Write(ENC28J60_READ_BUF_MEM);
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while(len--)
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{
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*buf++ = _spi->Write(0);
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}
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*buf='\0';
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}
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void Enc28j60::WriteBuffer(const byte* buf, uint len)
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{
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SpiScope sc(_spi);
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_spi->Write(ENC28J60_WRITE_BUF_MEM);
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while(len--)
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{
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_spi->Write(*buf++);
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}
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}
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void Enc28j60::SetBank(byte addr)
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{
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// set the bank (if needed)
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if((addr & BANK_MASK) != Bank)
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{
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// set the bank
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WriteOp(ENC28J60_BIT_FIELD_CLR, ECON1, (ECON1_BSEL1 | ECON1_BSEL0));
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WriteOp(ENC28J60_BIT_FIELD_SET, ECON1, (addr & BANK_MASK) >> 5);
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Bank = (addr & BANK_MASK);
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}
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}
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byte Enc28j60::ReadReg(byte addr)
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{
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SetBank(addr);
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return ReadOp(ENC28J60_READ_CTRL_REG, addr);
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}
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void Enc28j60::WriteReg(byte addr, byte data)
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{
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SetBank(addr);
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WriteOp(ENC28J60_WRITE_CTRL_REG, addr, data);
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}
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// 发送ARP请求包到目的地址
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uint Enc28j60::PhyRead(byte addr)
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{
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// 设置PHY寄存器地址
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WriteReg(MIREGADR, addr);
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WriteReg(MICMD, MICMD_MIIRD);
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// 循环等待PHY寄存器被MII读取，需要10.24us
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while((ReadReg(MISTAT) & MISTAT_BUSY));
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// 停止读取
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//WriteReg(MICMD, MICMD_MIIRD);
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WriteReg(MICMD, 0x00); // 赋值0x00
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// 获得结果并返回
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return (ReadReg(MIRDH) << 8) | ReadReg(MIRDL);
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}
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bool Enc28j60::PhyWrite(byte addr, uint data)
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{
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// set the PHY register addr
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WriteReg(MIREGADR, addr);
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// write the PHY data
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WriteReg(MIWRL, data);
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WriteReg(MIWRH, data >> 8);
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//ulong us = Time.Current() + 10 * 1000;
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TimeWheel tw(0, 10, 0);
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// 等待 PHY 写完成
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while(ReadReg(MISTAT) & MISTAT_BUSY)
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{
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//if(us < Time.Current()) return false;
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if(tw.Expired()) return false;
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}
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return true;
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}
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void Enc28j60::ClockOut(byte clock)
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{
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// setup clkout: 2 is 12.5MHz:
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WriteReg(ECOCON, clock & 0x7);
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}
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void Enc28j60::Init(byte mac[6])
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{
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assert_param(mac);
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memcpy(Mac, mac, 6);
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}
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bool Enc28j60::OnOpen()
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{
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assert_param(Mac);
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debug_printf("Enc28j60::Open(%02X-%02X-%02X-%02X-%02X-%02X)\r\n", Mac[0], Mac[1], Mac[2], Mac[3], Mac[4], Mac[5]);
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if(!_ce.Empty())
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{
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_ce = true;
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Sys.Sleep(100);
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_ce = false;
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Sys.Sleep(100);
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_ce = true;
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}
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// 检查并打开Spi
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_spi->Open();
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// 系统软重启
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WriteOp(ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
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Sys.Sleep(3);
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// check CLKRDY bit to see if reset is complete
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// The CLKRDY does not work. See Rev. B4 Silicon Errata point. Just wait.
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//while(!(ReadReg(ESTAT) & ESTAT_CLKRDY));
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// do bank 0 stuff
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// initialize receive buffer
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// 16-bit transfers, must write low byte first
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// 设置接收缓冲区开始地址
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NextPacketPtr = RXSTART_INIT;
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// Rx开始
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WriteReg(ERXSTL, RXSTART_INIT & 0xFF);
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WriteReg(ERXSTH, RXSTART_INIT >> 8);
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// 设置接收指针地址
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WriteReg(ERXRDPTL, RXSTART_INIT & 0xFF);
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WriteReg(ERXRDPTH, RXSTART_INIT >> 8);
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// 设置接收缓冲区的末尾地址 ERXND寄存器默认指向整个缓冲区的最后一个单元
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WriteReg(ERXNDL, RXSTOP_INIT & 0xFF);
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WriteReg(ERXNDH, RXSTOP_INIT >> 8);
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// 设置发送缓冲区起始地址 ETXST寄存器默认地址是整个缓冲区的第一个单元
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WriteReg(ETXSTL, TXSTART_INIT & 0xFF);
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WriteReg(ETXSTH, TXSTART_INIT >> 8);
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// TX 结束
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WriteReg(ETXNDL, TXSTOP_INIT & 0xFF);
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WriteReg(ETXNDH, TXSTOP_INIT >> 8);
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// Bank 1 填充，包过滤
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// 广播包只允许ARP通过，单播包只允许目的地址是我们mac(MAADR)的数据包
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//
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// The pattern to match on is therefore
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// Type ETH.DST
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// ARP BROADCAST
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// 06 08 -- ff ff ff ff ff ff -> ip checksum for theses bytes=f7f9
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// in binary these poitions are:11 0000 0011 1111
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// This is hex 303F->EPMM0=0x3f,EPMM1=0x30
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//WriteReg(ERXFCON, ERXFCON_UCEN|ERXFCON_CRCEN|ERXFCON_PMEN);
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WriteReg(ERXFCON, ERXFCON_UCEN | ERXFCON_CRCEN | ERXFCON_BCEN); // ERXFCON_BCEN 不过滤广播包，实现DHCP
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WriteReg(EPMM0, 0x3f);
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WriteReg(EPMM1, 0x30);
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WriteReg(EPMCSL, 0xf9);
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WriteReg(EPMCSH, 0xf7);
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// Bank 2，打开MAC接收
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WriteReg(MACON1, MACON1_MARXEN | MACON1_TXPAUS | MACON1_RXPAUS);
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// MACON2清零，让MAC退出复位状态
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WriteReg(MACON2, 0x00);
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// 启用自动填充到60字节并进行Crc校验
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WriteOp(ENC28J60_BIT_FIELD_SET, MACON3, MACON3_PADCFG0 | MACON3_TXCRCEN | MACON3_FRMLNEN | MACON3_FULDPX);
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// 配置非背对背包之间的间隔
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WriteReg(MAIPGL, 0x12);
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WriteReg(MAIPGH, 0x0C);
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// 配置背对背包之间的间隔
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WriteReg(MABBIPG, 0x15); // 有的例程这里是0x12
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// 设置控制器将接收的最大包大小，不要发送大于该大小的包
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WriteReg(MAMXFLL, MAX_FRAMELEN & 0xFF);
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WriteReg(MAMXFLH, MAX_FRAMELEN >> 8);
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// Bank 3 填充
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// write MAC addr
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// NOTE: MAC addr in ENC28J60 is byte-backward
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WriteReg(MAADR5, Mac[0]);
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WriteReg(MAADR4, Mac[1]);
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WriteReg(MAADR3, Mac[2]);
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WriteReg(MAADR2, Mac[3]);
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WriteReg(MAADR1, Mac[4]);
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WriteReg(MAADR0, Mac[5]);
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bool flag = true;
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// 配置PHY为全双工 LEDB为拉电流
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if(flag && !PhyWrite(PHCON1, PHCON1_PDPXMD)) flag = false;
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// 阻止发送回路的自动环回
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if(flag && !PhyWrite(PHCON2, PHCON2_HDLDIS)) flag = false;
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// PHY LED 配置,LED用来指示通信的状态
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if(flag && !PhyWrite(PHLCON, 0x476)) flag = false;
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if(!flag)
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{
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debug_printf("Enc28j60::Init Failed! Can't write Physical, please check Spi!\r\n");
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return false;
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}
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// 切换到bank0
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SetBank(ECON1);
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// 打开中断
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WriteOp(ENC28J60_BIT_FIELD_SET, EIE, EIE_INTIE | EIE_PKTIE);
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// 新增加，有些例程里面没有
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WriteOp(ENC28J60_BIT_FIELD_SET, EIE, EIE_RXERIE | EIE_TXERIE | EIE_INTIE);
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// 打开包接收
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WriteOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN);
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byte rev = GetRevision();
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if(rev == 0)
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{
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debug_printf("Enc28j60::Init Failed! Revision=%d\r\n", rev);
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return false;
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}
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// 将enc28j60第三引脚的时钟输出改为：from 6.25MHz to 12.5MHz(本例程该引脚NC,没用到)
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ClockOut(2);
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debug_printf("Enc28j60::Inited! Revision=%d\r\n", rev);
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return true;
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}
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byte Enc28j60::GetRevision()
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{
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// 在EREVID 内也存储了版本信息。 EREVID 是一个只读控制寄存器，包含一个5 位标识符，用来标识器件特定硅片的版本号
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return ReadReg(EREVID);
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}
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bool Enc28j60::OnWrite(const byte* packet, uint len)
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{
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// 设置写指针为传输数据区域的开头
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WriteReg(EWRPTL, TXSTART_INIT & 0xFF);
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WriteReg(EWRPTH, TXSTART_INIT >> 8);
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// 设置TXND指针为纠正后的给定数据包大小
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WriteReg(ETXNDL, (TXSTART_INIT + len) & 0xFF);
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WriteReg(ETXNDH, (TXSTART_INIT + len) >> 8);
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// 写每个包的控制字节（0x00意味着使用macon3设置）
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WriteOp(ENC28J60_WRITE_BUF_MEM, 0, 0x00);
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// 复制数据包到传输缓冲区
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WriteBuffer(packet, len);
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// 把传输缓冲区的内容发送到网络
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WriteOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_TXRTS);
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#if ENC_DEBUG
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if(GetRevision() == 0x05u || GetRevision() == 0x06u)
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{
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ushort count = 0;
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while((ReadReg(EIR) & (EIR_TXERIF | EIR_TXIF)) && (++count < 1000));
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if((ReadReg(EIR) & EIR_TXERIF) || (count >= 1000))
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{
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WORD_VAL ReadPtrSave;
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WORD_VAL TXEnd;
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TXSTATUS TXStatus;
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byte i;
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// Cancel the previous transmission if it has become stuck set
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//BFCReg(ECON1, ECON1_TXRTS);
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WriteOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_TXRTS);
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// Save the current read pointer (controlled by application)
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ReadPtrSave.v[0] = ReadReg(ERDPTL);
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ReadPtrSave.v[1] = ReadReg(ERDPTH);
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// Get the location of the transmit status vector
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TXEnd.v[0] = ReadReg(ETXNDL);
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TXEnd.v[1] = ReadReg(ETXNDH);
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TXEnd.Val++;
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// ReadReg the transmit status vector
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WriteReg(ERDPTL, TXEnd.v[0]);
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WriteReg(ERDPTH, TXEnd.v[1]);
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ReadBuffer((byte*)&TXStatus, sizeof(TXStatus));
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// Implement retransmission if a late collision occured (this can
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// happen on B5 when certain link pulses arrive at the same time
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// as the transmission)
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for(i = 0; i < 16u; i++)
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{
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if((ReadReg(EIR) & EIR_TXERIF) && TXStatus.bits.LateCollision)
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{
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// Reset the TX logic
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WriteOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_TXRTS);
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WriteOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_TXRTS);
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WriteOp(ENC28J60_BIT_FIELD_CLR, EIR, EIR_TXERIF | EIR_TXIF);
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// Transmit the packet again
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WriteOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_TXRTS);
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while(!(ReadReg(EIR) & (EIR_TXERIF | EIR_TXIF)));
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// Cancel the previous transmission if it has become stuck set
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WriteOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_TXRTS);
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// ReadReg transmit status vector
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WriteReg(ERDPTL, TXEnd.v[0]);
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WriteReg(ERDPTH, TXEnd.v[1]);
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ReadBuffer((byte*)&TXStatus, sizeof(TXStatus));
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}
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else
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{
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break;
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}
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}
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// Restore the current read pointer
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WriteReg(ERDPTL, ReadPtrSave.v[0]);
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WriteReg(ERDPTH, ReadPtrSave.v[1]);
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}
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}
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#endif
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// Reset the transmit logic problem. See Rev. B4 Silicon Errata point 12.
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if( (ReadReg(EIR) & EIR_TXERIF) )
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{
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WriteOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_TXRTS);
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}
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return true;
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}
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// 从网络接收缓冲区获取一个数据包，该包开头是以太网头
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// packet，该包应该存储到的缓冲区；maxlen，可接受的最大数据长度
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uint Enc28j60::OnRead(byte* packet, uint maxlen)
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{
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uint rxstat;
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uint len;
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// 检测缓冲区是否收到一个数据包
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/*if( !(ReadReg(EIR) & EIR_PKTIF) )
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{
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// The above does not work. See Rev. B4 Silicon Errata point 6.
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// 通过查看EPKTCNT寄存器再次检查是否收到包
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// EPKTCNT为0表示没有包接收/或包已被处理
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if(ReadReg(EPKTCNT) == 0) return 0;
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}*/
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// 收到的以太网数据包长度
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if( ReadReg(EPKTCNT) == 0 ) return 0;
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// 配置接收缓冲器读指针指向地址
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WriteReg(ERDPTL, (NextPacketPtr));
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WriteReg(ERDPTH, (NextPacketPtr) >> 8);
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// 下一个数据包的读指针
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NextPacketPtr = ReadOp(ENC28J60_READ_BUF_MEM, 0);
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NextPacketPtr |= ReadOp(ENC28J60_READ_BUF_MEM, 0) << 8;
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// 读数据包字节长度 (see datasheet page 43)
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len = ReadOp(ENC28J60_READ_BUF_MEM, 0);
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len |= ReadOp(ENC28J60_READ_BUF_MEM, 0) << 8;
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len -= 4; // 删除 CRC 计数
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// 读接收数据包的状态 (see datasheet page 43)
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rxstat = ReadOp(ENC28J60_READ_BUF_MEM, 0);
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rxstat |= ReadOp(ENC28J60_READ_BUF_MEM, 0) << 8;
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// 限制获取的长度。有些例程这里不用减一
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if (len > maxlen - 1)
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{
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len = maxlen - 1;
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}
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// check CRC and symbol errors (see datasheet page 44, table 7-3):
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// The ERXFCON.CRCEN is set by default. Normally we should not
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// need to check this.
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if ((rxstat & 0x80)==0)
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{
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// invalid
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len = 0;
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}
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else
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{
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// 从缓冲区中将数据包复制到packet中
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ReadBuffer(packet, len);
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}
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// Move the RX read pointer to the start of the next received packet
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// This frees the memory we just read out
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WriteReg(ERXRDPTL, (NextPacketPtr));
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WriteReg(ERXRDPTH, (NextPacketPtr) >> 8);
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// 数据包个数递减位EPKTCNT减1
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WriteOp(ENC28J60_BIT_FIELD_SET, ECON2, ECON2_PKTDEC);
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return len;
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}
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// 返回MAC连接状态
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bool Enc28j60::Linked()
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{
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return PhyRead(PHSTAT1) & PHSTAT1_LLSTAT;
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}
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