140 lines
3.9 KiB
C++
140 lines
3.9 KiB
C++
#include "Kernel\Sys.h"
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#include "Kernel\Interrupt.h"
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//#include "SerialPort.h"
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#include "..\stm32.h"
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#define IS_IRQ(irq) (irq >= -16 && irq <= VectorySize - 16)
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//#include "..\CMSIS\Interrupt.cpp"
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void TInterrupt::OnInit() const
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{
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// 禁用所有中断
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NVIC->ICER[0] = 0xFFFFFFFF;
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#if defined(STM32F1) || defined(STM32F4)
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NVIC->ICER[1] = 0xFFFFFFFF;
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NVIC->ICER[2] = 0xFFFFFFFF;
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#endif // defined(STM32F1) || defined(STM32F4)
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// 清除所有中断位
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NVIC->ICPR[0] = 0xFFFFFFFF;
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#if defined(STM32F1) || defined(STM32F4)
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NVIC->ICPR[1] = 0xFFFFFFFF;
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NVIC->ICPR[2] = 0xFFFFFFFF;
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#endif // defined(STM32F1) || defined(STM32F4)
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#if defined(BOOT) || defined(APP)
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StrBoot.pUserHandler = RealHandler;;
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#endif
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#if defined(APP)
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GlobalEnable();
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#endif
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#ifdef STM32F4
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/*SCB->AIRCR = (0x5FA << SCB_AIRCR_VECTKEY_Pos) // 解锁
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| (7 << SCB_AIRCR_PRIGROUP_Pos); // 没有优先组位*/
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// 中断优先级分配方案4，四位都是抢占优先级。其实上面的寄存器操作就是设置优先级方案为0
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NVIC_PriorityGroupConfig(NVIC_PriorityGroup_4);
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// 打开系统异常，否则这些异常都会跑到硬件中断里面
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SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk
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| SCB_SHCSR_BUSFAULTENA_Msk
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| SCB_SHCSR_MEMFAULTENA_Msk;
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#endif // STM32F4
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#ifdef STM32F1
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/*SCB->AIRCR = (0x5FA << SCB_AIRCR_VECTKEY_Pos) // 解锁
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| (7 << SCB_AIRCR_PRIGROUP_Pos); // 没有优先组位*/
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// 中断优先级分配方案4，四位都是抢占优先级。其实上面的寄存器操作就是设置优先级方案为0
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NVIC_PriorityGroupConfig(NVIC_PriorityGroup_4);
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// 打开系统异常，否则这些异常都会跑到硬件中断里面
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SCB->SHCSR |= SCB_SHCSR_USGFAULTENA
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| SCB_SHCSR_BUSFAULTENA
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| SCB_SHCSR_MEMFAULTENA;
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#endif // STM32F1
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// 初始化EXTI中断线为默认值
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EXTI_DeInit();
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}
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#ifdef STM32F1
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uint TInterrupt::EncodePriority (uint priorityGroup, uint preemptPriority, uint subPriority) const
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{
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return NVIC_EncodePriority(priorityGroup, preemptPriority, subPriority);
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}
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void TInterrupt::DecodePriority (uint priority, uint priorityGroup, uint* pPreemptPriority, uint* pSubPriority) const
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{
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NVIC_DecodePriority(priority, priorityGroup, (uint32_t*)pPreemptPriority, (uint32_t*)pSubPriority);
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}
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#endif
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#if !defined(TINY)
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#if defined(STM32F0)
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#pragma arm section code = "SectionForSys"
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#endif
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extern "C"
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{
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void FAULT_SubHandler(uint* registers, uint exception)
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{
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debug_printf("LR=0x%08x PC=0x%08x PSR=0x%08x\r\n", registers[5], registers[6], registers[7]);
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for(int i=0; i<=7; i++)
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{
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debug_printf("R%d=0x%08x\r\n", i, registers[i]);
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}
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debug_printf("R12=0x%08x\r\n", registers[4]);
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TInterrupt::Halt();
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}
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#if defined ( __CC_ARM )
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__asm void FaultHandler()
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{
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IMPORT FAULT_SubHandler
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//on entry, we have an exception frame on the stack:
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//SP+00: R0
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//SP+04: R1
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//SP+08: R2
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//SP+12: R3
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//SP+16: R12
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//SP+20: LR
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//SP+24: PC
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//SP+28: PSR
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//R0-R12 are not overwritten yet
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#if defined(STM32F0) || defined(GD32F150)
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//add sp,sp,#16 // remove R0-R3
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push {r4-r7} // store R0-R11
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#else
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add sp,sp,#16 // remove R0-R3
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push {r0-r11} // store R0-R11
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#endif
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mov r0,sp
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//R0+00: R0-R12
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//R0+52: LR
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//R0+56: PC
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//R0+60: PSR
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mrs r1,IPSR // exception number
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b FAULT_SubHandler
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//never expect to return
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}
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#elif (defined (__GNUC__))
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void FaultHandler()
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{
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__asm volatile (
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#if defined(STM32F0) || defined(GD32F150)
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"push {r4-r7} \n\t"
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#else
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"add sp,sp,#16 \n\t"
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"push {r0-r11} \n\t"
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#endif
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"mov r0,sp \n\t"
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"mrs r1,IPSR \n\t"
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"b FAULT_SubHandler \n\t");
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}
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#endif
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}
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#endif
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