forked from OSchip/llvm-project
GlobalISel: make translate* functions take the most specialized class possible.
NFC. llvm-svn: 277188
This commit is contained in:
parent
02d8d054ab
commit
0d56e05a12
|
|
@ -113,17 +113,17 @@ private:
|
||||||
|
|
||||||
/// Translate \p Inst into a binary operation \p Opcode.
|
/// Translate \p Inst into a binary operation \p Opcode.
|
||||||
/// \pre \p Inst is a binary operation.
|
/// \pre \p Inst is a binary operation.
|
||||||
bool translateBinaryOp(unsigned Opcode, const Instruction &Inst);
|
bool translateBinaryOp(unsigned Opcode, const BinaryOperator &Inst);
|
||||||
|
|
||||||
/// Translate branch (br) instruction.
|
/// Translate branch (br) instruction.
|
||||||
/// \pre \p Inst is a branch instruction.
|
/// \pre \p Inst is a branch instruction.
|
||||||
bool translateBr(const Instruction &Inst);
|
bool translateBr(const BranchInst &Inst);
|
||||||
|
|
||||||
/// Translate return (ret) instruction.
|
/// Translate return (ret) instruction.
|
||||||
/// The target needs to implement CallLowering::lowerReturn for
|
/// The target needs to implement CallLowering::lowerReturn for
|
||||||
/// this to succeed.
|
/// this to succeed.
|
||||||
/// \pre \p Inst is a return instruction.
|
/// \pre \p Inst is a return instruction.
|
||||||
bool translateReturn(const Instruction &Inst);
|
bool translateReturn(const ReturnInst &Inst);
|
||||||
/// @}
|
/// @}
|
||||||
|
|
||||||
// Builder for machine instruction a la IRBuilder.
|
// Builder for machine instruction a la IRBuilder.
|
||||||
|
|
|
||||||
|
|
@ -77,7 +77,10 @@ MachineBasicBlock &IRTranslator::getOrCreateBB(const BasicBlock &BB) {
|
||||||
return *MBB;
|
return *MBB;
|
||||||
}
|
}
|
||||||
|
|
||||||
bool IRTranslator::translateBinaryOp(unsigned Opcode, const Instruction &Inst) {
|
bool IRTranslator::translateBinaryOp(unsigned Opcode,
|
||||||
|
const BinaryOperator &Inst) {
|
||||||
|
// FIXME: handle signed/unsigned wrapping flags.
|
||||||
|
|
||||||
// Get or create a virtual register for each value.
|
// Get or create a virtual register for each value.
|
||||||
// Unless the value is a Constant => loadimm cst?
|
// Unless the value is a Constant => loadimm cst?
|
||||||
// or inline constant each time?
|
// or inline constant each time?
|
||||||
|
|
@ -92,19 +95,15 @@ bool IRTranslator::translateBinaryOp(unsigned Opcode, const Instruction &Inst) {
|
||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
bool IRTranslator::translateReturn(const Instruction &Inst) {
|
bool IRTranslator::translateReturn(const ReturnInst &RI) {
|
||||||
assert(isa<ReturnInst>(Inst) && "Return expected");
|
const Value *Ret = RI.getReturnValue();
|
||||||
const Value *Ret = cast<ReturnInst>(Inst).getReturnValue();
|
|
||||||
// The target may mess up with the insertion point, but
|
// The target may mess up with the insertion point, but
|
||||||
// this is not important as a return is the last instruction
|
// this is not important as a return is the last instruction
|
||||||
// of the block anyway.
|
// of the block anyway.
|
||||||
return CLI->lowerReturn(MIRBuilder, Ret, !Ret ? 0 : getOrCreateVReg(*Ret));
|
return CLI->lowerReturn(MIRBuilder, Ret, !Ret ? 0 : getOrCreateVReg(*Ret));
|
||||||
}
|
}
|
||||||
|
|
||||||
bool IRTranslator::translateBr(const Instruction &Inst) {
|
bool IRTranslator::translateBr(const BranchInst &BrInst) {
|
||||||
assert(isa<BranchInst>(Inst) && "Branch expected");
|
|
||||||
const BranchInst &BrInst = *cast<BranchInst>(&Inst);
|
|
||||||
|
|
||||||
unsigned Succ = 0;
|
unsigned Succ = 0;
|
||||||
if (!BrInst.isUnconditional()) {
|
if (!BrInst.isUnconditional()) {
|
||||||
// We want a G_BRCOND to the true BB followed by an unconditional branch.
|
// We want a G_BRCOND to the true BB followed by an unconditional branch.
|
||||||
|
|
@ -201,23 +200,23 @@ bool IRTranslator::translate(const Instruction &Inst) {
|
||||||
switch(Inst.getOpcode()) {
|
switch(Inst.getOpcode()) {
|
||||||
// Arithmetic operations.
|
// Arithmetic operations.
|
||||||
case Instruction::Add:
|
case Instruction::Add:
|
||||||
return translateBinaryOp(TargetOpcode::G_ADD, Inst);
|
return translateBinaryOp(TargetOpcode::G_ADD, cast<BinaryOperator>(Inst));
|
||||||
case Instruction::Sub:
|
case Instruction::Sub:
|
||||||
return translateBinaryOp(TargetOpcode::G_SUB, Inst);
|
return translateBinaryOp(TargetOpcode::G_SUB, cast<BinaryOperator>(Inst));
|
||||||
|
|
||||||
// Bitwise operations.
|
// Bitwise operations.
|
||||||
case Instruction::And:
|
case Instruction::And:
|
||||||
return translateBinaryOp(TargetOpcode::G_AND, Inst);
|
return translateBinaryOp(TargetOpcode::G_AND, cast<BinaryOperator>(Inst));
|
||||||
case Instruction::Or:
|
case Instruction::Or:
|
||||||
return translateBinaryOp(TargetOpcode::G_OR, Inst);
|
return translateBinaryOp(TargetOpcode::G_OR, cast<BinaryOperator>(Inst));
|
||||||
case Instruction::Xor:
|
case Instruction::Xor:
|
||||||
return translateBinaryOp(TargetOpcode::G_XOR, Inst);
|
return translateBinaryOp(TargetOpcode::G_XOR, cast<BinaryOperator>(Inst));
|
||||||
|
|
||||||
// Branch operations.
|
// Branch operations.
|
||||||
case Instruction::Br:
|
case Instruction::Br:
|
||||||
return translateBr(Inst);
|
return translateBr(cast<BranchInst>(Inst));
|
||||||
case Instruction::Ret:
|
case Instruction::Ret:
|
||||||
return translateReturn(Inst);
|
return translateReturn(cast<ReturnInst>(Inst));
|
||||||
|
|
||||||
// Casts
|
// Casts
|
||||||
case Instruction::BitCast:
|
case Instruction::BitCast:
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue