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X86: Open up some opportunities for constant folding by postponing shift lowering. 

Fixes PR15141.

llvm-svn: 174327
This commit is contained in:
Benjamin Kramer 2013-02-04 15:19:33 +00:00
parent 0611298446
commit 2c9da989c2
2 changed files with 12 additions and 4 deletions
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6
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -11583,8 +11583,7 @@ SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
// Lower SHL with variable shift amount.
if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
Op = DAG.getNode(X86ISD::VSHLI, dl, VT, Op.getOperand(1),
DAG.getConstant(23, MVT::i32));
Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
@ -11595,8 +11594,7 @@ SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
// a = a << 5;
Op = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, Op.getOperand(1),
DAG.getConstant(5, MVT::i32));
Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
// Turn 'a' into a mask suitable for VSELECT

10
llvm/test/CodeGen/X86/avx-shift.ll
View File

@ -112,6 +112,16 @@ define <8 x i32> @vshift08(<8 x i32> %a) nounwind {
ret <8 x i32> %bitop
}
; PR15141
; CHECK: _vshift13:
; CHECK-NOT: vpsll
; CHECK: vcvttps2dq
; CHECK-NEXT: vpmulld
define <4 x i32> @vshift13(<4 x i32> %in) {
%T = shl <4 x i32> %in, <i32 0, i32 1, i32 2, i32 4>
ret <4 x i32> %T
}
;;; Uses shifts for sign extension
; CHECK: _sext_v16i16
; CHECK: vpsllw