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[mips][ias] Correct ELF eflags when Octeon is the target. 

Reviewers: sdardis

Subscribers: petarj, mpf, dsanders, spetrovic, llvm-commits, sdardis

Differential Revision: http://reviews.llvm.org/D18899

llvm-svn: 269283
This commit is contained in:
Daniel Sanders 2016-05-12 11:31:19 +00:00
parent a166979e45
commit 415c159e09
5 changed files with 59 additions and 27 deletions
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22
llvm/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.cpp
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@ -53,17 +53,17 @@ uint8_t MipsABIFlagsSection::getCPR1SizeValue() {
namespace llvm { namespace llvm {
MCStreamer &operator<<(MCStreamer &OS, MipsABIFlagsSection &ABIFlagsSection) { MCStreamer &operator<<(MCStreamer &OS, MipsABIFlagsSection &ABIFlagsSection) {
// Write out a Elf_Internal_ABIFlags_v0 struct // Write out a Elf_Internal_ABIFlags_v0 struct
OS.EmitIntValue(ABIFlagsSection.getVersionValue(), 2); // version OS.EmitIntValue(ABIFlagsSection.getVersionValue(), 2); // version
OS.EmitIntValue(ABIFlagsSection.getISALevelValue(), 1); // isa_level OS.EmitIntValue(ABIFlagsSection.getISALevelValue(), 1); // isa_level
OS.EmitIntValue(ABIFlagsSection.getISARevisionValue(), 1); // isa_rev OS.EmitIntValue(ABIFlagsSection.getISARevisionValue(), 1); // isa_rev
OS.EmitIntValue(ABIFlagsSection.getGPRSizeValue(), 1); // gpr_size OS.EmitIntValue(ABIFlagsSection.getGPRSizeValue(), 1); // gpr_size
OS.EmitIntValue(ABIFlagsSection.getCPR1SizeValue(), 1); // cpr1_size OS.EmitIntValue(ABIFlagsSection.getCPR1SizeValue(), 1); // cpr1_size
OS.EmitIntValue(ABIFlagsSection.getCPR2SizeValue(), 1); // cpr2_size OS.EmitIntValue(ABIFlagsSection.getCPR2SizeValue(), 1); // cpr2_size
OS.EmitIntValue(ABIFlagsSection.getFpABIValue(), 1); // fp_abi OS.EmitIntValue(ABIFlagsSection.getFpABIValue(), 1); // fp_abi
OS.EmitIntValue(ABIFlagsSection.getISAExtensionSetValue(), 4); // isa_ext OS.EmitIntValue(ABIFlagsSection.getISAExtensionValue(), 4); // isa_ext
OS.EmitIntValue(ABIFlagsSection.getASESetValue(), 4); // ases OS.EmitIntValue(ABIFlagsSection.getASESetValue(), 4); // ases
OS.EmitIntValue(ABIFlagsSection.getFlags1Value(), 4); // flags1 OS.EmitIntValue(ABIFlagsSection.getFlags1Value(), 4); // flags1
OS.EmitIntValue(ABIFlagsSection.getFlags2Value(), 4); // flags2 OS.EmitIntValue(ABIFlagsSection.getFlags2Value(), 4); // flags2
return OS; return OS;
} }
} }

17
llvm/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.h
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@ -35,7 +35,7 @@ struct MipsABIFlagsSection {
// The size of co-processor 2 registers. // The size of co-processor 2 registers.
Mips::AFL_REG CPR2Size; Mips::AFL_REG CPR2Size;
// Processor-specific extension. // Processor-specific extension.
uint32_t ISAExtensionSet; Mips::AFL_EXT ISAExtension;
// Mask of ASEs used. // Mask of ASEs used.
uint32_t ASESet; uint32_t ASESet;
@ -51,8 +51,8 @@ public:
MipsABIFlagsSection() MipsABIFlagsSection()
: Version(0), ISALevel(0), ISARevision(0), GPRSize(Mips::AFL_REG_NONE), : Version(0), ISALevel(0), ISARevision(0), GPRSize(Mips::AFL_REG_NONE),
CPR1Size(Mips::AFL_REG_NONE), CPR2Size(Mips::AFL_REG_NONE), CPR1Size(Mips::AFL_REG_NONE), CPR2Size(Mips::AFL_REG_NONE),
ISAExtensionSet(0), ASESet(0), OddSPReg(false), Is32BitABI(false), ISAExtension(Mips::AFL_EXT_NONE), ASESet(0), OddSPReg(false),
FpABI(FpABIKind::ANY) {} Is32BitABI(false), FpABI(FpABIKind::ANY) {}
uint16_t getVersionValue() { return (uint16_t)Version; } uint16_t getVersionValue() { return (uint16_t)Version; }
uint8_t getISALevelValue() { return (uint8_t)ISALevel; } uint8_t getISALevelValue() { return (uint8_t)ISALevel; }
@ -61,7 +61,7 @@ public:
uint8_t getCPR1SizeValue(); uint8_t getCPR1SizeValue();
uint8_t getCPR2SizeValue() { return (uint8_t)CPR2Size; } uint8_t getCPR2SizeValue() { return (uint8_t)CPR2Size; }
uint8_t getFpABIValue(); uint8_t getFpABIValue();
uint32_t getISAExtensionSetValue() { return (uint32_t)ISAExtensionSet; } uint32_t getISAExtensionValue() { return (uint32_t)ISAExtension; }
uint32_t getASESetValue() { return (uint32_t)ASESet; } uint32_t getASESetValue() { return (uint32_t)ASESet; }
uint32_t getFlags1Value() { uint32_t getFlags1Value() {
@ -140,6 +140,14 @@ public:
CPR1Size = P.isFP64bit() ? Mips::AFL_REG_64 : Mips::AFL_REG_32; CPR1Size = P.isFP64bit() ? Mips::AFL_REG_64 : Mips::AFL_REG_32;
} }
template <class PredicateLibrary>
void setISAExtensionFromPredicates(const PredicateLibrary &P) {
if (P.hasCnMips())
ISAExtension = Mips::AFL_EXT_OCTEON;
else
ISAExtension = Mips::AFL_EXT_NONE;
}
template <class PredicateLibrary> template <class PredicateLibrary>
void setASESetFromPredicates(const PredicateLibrary &P) { void setASESetFromPredicates(const PredicateLibrary &P) {
ASESet = 0; ASESet = 0;
@ -179,6 +187,7 @@ public:
setISALevelAndRevisionFromPredicates(P); setISALevelAndRevisionFromPredicates(P);
setGPRSizeFromPredicates(P); setGPRSizeFromPredicates(P);
setCPR1SizeFromPredicates(P); setCPR1SizeFromPredicates(P);
setISAExtensionFromPredicates(P);
setASESetFromPredicates(P); setASESetFromPredicates(P);
setFpAbiFromPredicates(P); setFpAbiFromPredicates(P);
OddSPReg = P.useOddSPReg(); OddSPReg = P.useOddSPReg();

4
llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
View File

@ -707,6 +707,10 @@ MipsTargetELFStreamer::MipsTargetELFStreamer(MCStreamer &S,
else else
EFlags |= ELF::EF_MIPS_ARCH_1; EFlags |= ELF::EF_MIPS_ARCH_1;
// Machine
if (Features[Mips::FeatureCnMips])
EFlags |= ELF::EF_MIPS_MACH_OCTEON;
// Other options. // Other options.
if (Features[Mips::FeatureNaN2008]) if (Features[Mips::FeatureNaN2008])
EFlags |= ELF::EF_MIPS_NAN2008; EFlags |= ELF::EF_MIPS_NAN2008;

3
llvm/test/MC/Mips/elf_eflags.s
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@ -125,3 +125,6 @@
# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-NAN2008 %s # RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-NAN2008 %s
# MIPS64EL-MIPS64-NAN2008: Flags [ (0x60000406) # MIPS64EL-MIPS64-NAN2008: Flags [ (0x60000406)
# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=octeon %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-OCTEON %s
# MIPSEL-OCTEON: Flags [ (0x808B0006)

36
llvm/test/MC/Mips/mips_abi_flags_xx.s
View File

@ -3,22 +3,30 @@
# #
# RUN: llvm-mc %s -arch=mips -mcpu=mips32 -filetype=obj -o - | \ # RUN: llvm-mc %s -arch=mips -mcpu=mips32 -filetype=obj -o - | \
# RUN: llvm-readobj -sections -section-data -section-relocations -mips-abi-flags - | \ # RUN: llvm-readobj -sections -section-data -section-relocations -mips-abi-flags - | \
# RUN: FileCheck %s -check-prefix=CHECK-OBJ -check-prefix=CHECK-OBJ-R1 # RUN: FileCheck %s -check-prefix=CHECK-OBJ -check-prefix=CHECK-OBJ-32R1 \
# RUN: -check-prefix=CHECK-OBJ-MIPS
# RUN: llvm-mc /dev/null -arch=mips -mcpu=mips32 -mattr=fpxx -filetype=obj -o - | \ # RUN: llvm-mc /dev/null -arch=mips -mcpu=mips32 -mattr=fpxx -filetype=obj -o - | \
# RUN: llvm-readobj -sections -section-data -section-relocations -mips-abi-flags - | \ # RUN: llvm-readobj -sections -section-data -section-relocations -mips-abi-flags - | \
# RUN: FileCheck %s -check-prefix=CHECK-OBJ -check-prefix=CHECK-OBJ-R1 # RUN: FileCheck %s -check-prefix=CHECK-OBJ -check-prefix=CHECK-OBJ-32R1 \
# RUN: -check-prefix=CHECK-OBJ-MIPS
# RUN: llvm-mc /dev/null -arch=mips -mcpu=mips32r6 -mattr=fpxx -filetype=obj -o - | \ # RUN: llvm-mc /dev/null -arch=mips -mcpu=mips32r6 -mattr=fpxx -filetype=obj -o - | \
# RUN: llvm-readobj -sections -section-data -section-relocations -mips-abi-flags - | \ # RUN: llvm-readobj -sections -section-data -section-relocations -mips-abi-flags - | \
# RUN: FileCheck %s -check-prefix=CHECK-OBJ -check-prefix=CHECK-OBJ-R6 # RUN: FileCheck %s -check-prefix=CHECK-OBJ -check-prefix=CHECK-OBJ-32R6 \
# RUN: -check-prefix=CHECK-OBJ-MIPS
# RUN: llvm-mc /dev/null -arch=mips -mcpu=octeon -filetype=obj -o - | \
# RUN: llvm-readobj -sections -section-data -section-relocations -mips-abi-flags - | \
# RUN: FileCheck %s -check-prefix=CHECK-OBJ -check-prefix=CHECK-OBJ-64R2 \
# RUN: -check-prefix=CHECK-OBJ-OCTEON
# CHECK-ASM: .module fp=xx # CHECK-ASM: .module fp=xx
# Checking if the Mips.abiflags were correctly emitted. # Checking if the Mips.abiflags were correctly emitted.
# CHECK-OBJ: Section { # CHECK-OBJ: Section {
# CHECK-OBJ: Index: 5 # CHECK-OBJ: Index: 5
# CHECK-OBJ-LABEL: Name: .MIPS.abiflags (12) # CHECK-OBJ-LABEL: Name: .MIPS.abiflags
# CHECK-OBJ: Type: SHT_MIPS_ABIFLAGS (0x7000002A) # CHECK-OBJ: Type: SHT_MIPS_ABIFLAGS (0x7000002A)
# CHECK-OBJ: Flags [ (0x2) # CHECK-OBJ: Flags [ (0x2)
# CHECK-OBJ: SHF_ALLOC (0x2) # CHECK-OBJ: SHF_ALLOC (0x2)
@ -34,14 +42,22 @@
# CHECK-OBJ-LABEL: } # CHECK-OBJ-LABEL: }
# CHECK-OBJ: MIPS ABI Flags { # CHECK-OBJ: MIPS ABI Flags {
# CHECK-OBJ-NEXT: Version: 0 # CHECK-OBJ-NEXT: Version: 0
# CHECK-OBJ-R1-NEXT: ISA: {{MIPS32$}} # CHECK-OBJ-32R1-NEXT: ISA: {{MIPS32$}}
# CHECK-OBJ-R6-NEXT: ISA: MIPS32r6 # CHECK-OBJ-32R6-NEXT: ISA: MIPS32r6
# CHECK-OBJ-NEXT: ISA Extension: None (0x0) # CHECK-OBJ-64R2-NEXT: ISA: MIPS64r2
# CHECK-OBJ-MIPS-NEXT: ISA Extension: None (0x0)
# CHECK-OBJ-OCTEON-NEXT: ISA Extension: Cavium Networks Octeon (0x5)
# CHECK-OBJ-NEXT: ASEs [ (0x0) # CHECK-OBJ-NEXT: ASEs [ (0x0)
# CHECK-OBJ-NEXT: ] # CHECK-OBJ-NEXT: ]
# CHECK-OBJ-NEXT: FP ABI: Hard float (32-bit CPU, Any FPU) (0x5) # CHECK-OBJ-32R1-NEXT: FP ABI: Hard float (32-bit CPU, Any FPU) (0x5)
# CHECK-OBJ-NEXT: GPR size: 32 # CHECK-OBJ-32R6-NEXT: FP ABI: Hard float (32-bit CPU, Any FPU) (0x5)
# CHECK-OBJ-NEXT: CPR1 size: 32 # CHECK-OBJ-64R2-NEXT: FP ABI: Hard float (double precision) (0x1)
# CHECK-OBJ-32R1-NEXT: GPR size: 32
# CHECK-OBJ-32R6-NEXT: GPR size: 32
# CHECK-OBJ-64R2-NEXT: GPR size: 64
# CHECK-OBJ-32R1-NEXT: CPR1 size: 32
# CHECK-OBJ-32R6-NEXT: CPR1 size: 32
# CHECK-OBJ-64R2-NEXT: CPR1 size: 64
# CHECK-OBJ-NEXT: CPR2 size: 0 # CHECK-OBJ-NEXT: CPR2 size: 0
# CHECK-OBJ-NEXT: Flags 1 [ (0x1) # CHECK-OBJ-NEXT: Flags 1 [ (0x1)
# CHECK-OBJ-NEXT: ODDSPREG (0x1) # CHECK-OBJ-NEXT: ODDSPREG (0x1)