forked from OSchip/llvm-project
[Hexagon] Create helpers extractVector and insertVector in lowering
llvm-svn: 319351
This commit is contained in:
Krzysztof Parzyszek
parent
cf5b4af820
commit
6a8e5f4b0f
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@ -2579,6 +2579,101 @@ HexagonTargetLowering::buildVector64(ArrayRef<SDValue> Elem, const SDLoc &dl,
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return SDValue(N, 0);
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}
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SDValue
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HexagonTargetLowering::extractVector(SDValue VecV, SDValue IdxV,
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const SDLoc &dl, MVT ValTy, MVT ResTy,
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SelectionDAG &DAG) const {
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MVT VecTy = ty(VecV);
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assert(!ValTy.isVector() ||
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VecTy.getVectorElementType() == ValTy.getVectorElementType());
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unsigned VecWidth = VecTy.getSizeInBits();
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unsigned ValWidth = ValTy.getSizeInBits();
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unsigned ElemWidth = VecTy.getVectorElementType().getSizeInBits();
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assert(VecWidth == 32 || VecWidth == 64);
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assert((VecWidth % ElemWidth) == 0);
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// Cast everything to scalar integer types.
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MVT ScalarTy = tyScalar(VecTy);
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VecV = DAG.getBitcast(ScalarTy, VecV);
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SDValue WidthV = DAG.getConstant(ValWidth, dl, MVT::i32);
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SDValue ExtV;
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(IdxV)) {
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unsigned Off = C->getZExtValue() * ElemWidth;
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if (VecWidth == 64 && ValWidth == 32) {
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assert(Off == 0 || Off == 32);
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unsigned SubIdx = Off == 0 ? Hexagon::isub_lo : Hexagon::isub_hi;
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ExtV = DAG.getTargetExtractSubreg(SubIdx, dl, MVT::i32, VecV);
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} else if (Off == 0 && (ValWidth % 8) == 0) {
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ExtV = DAG.getZeroExtendInReg(VecV, dl, tyScalar(ValTy));
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} else {
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SDValue OffV = DAG.getConstant(Off, dl, MVT::i32);
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// The return type of EXTRACTU must be the same as the type of the
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// input vector.
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ExtV = DAG.getNode(HexagonISD::EXTRACTU, dl, ScalarTy,
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{VecV, WidthV, OffV});
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}
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} else {
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if (ty(IdxV) != MVT::i32)
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IdxV = DAG.getZExtOrTrunc(IdxV, dl, MVT::i32);
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SDValue OffV = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV,
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DAG.getConstant(ElemWidth, dl, MVT::i32));
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// EXTRACTURP takes width/offset in a 64-bit pair.
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SDValue CombV = DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64,
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{WidthV, OffV});
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ExtV = DAG.getNode(HexagonISD::EXTRACTURP, dl, ScalarTy,
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{VecV, CombV});
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}
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// Cast ExtV to the requested result type.
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ExtV = DAG.getZExtOrTrunc(ExtV, dl, tyScalar(ResTy));
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ExtV = DAG.getBitcast(ResTy, ExtV);
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return ExtV;
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}
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SDValue
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HexagonTargetLowering::insertVector(SDValue VecV, SDValue ValV, SDValue IdxV,
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const SDLoc &dl, MVT ValTy,
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SelectionDAG &DAG) const {
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MVT VecTy = ty(VecV);
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unsigned VecWidth = VecTy.getSizeInBits();
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unsigned ValWidth = ValTy.getSizeInBits();
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assert(VecWidth == 32 || VecWidth == 64);
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assert((VecWidth % ValWidth) == 0);
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// Cast everything to scalar integer types.
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MVT ScalarTy = MVT::getIntegerVT(VecWidth);
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// The actual type of ValV may be different than ValTy (which is related
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// to the vector type).
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unsigned VW = ty(ValV).getSizeInBits();
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ValV = DAG.getBitcast(MVT::getIntegerVT(VW), ValV);
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VecV = DAG.getBitcast(ScalarTy, VecV);
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if (VW != VecWidth)
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ValV = DAG.getAnyExtOrTrunc(ValV, dl, ScalarTy);
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SDValue WidthV = DAG.getConstant(ValWidth, dl, MVT::i32);
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SDValue InsV;
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(IdxV)) {
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unsigned W = C->getZExtValue() * ValWidth;
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SDValue OffV = DAG.getConstant(W, dl, MVT::i32);
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InsV = DAG.getNode(HexagonISD::INSERT, dl, ScalarTy,
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{VecV, ValV, WidthV, OffV});
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} else {
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if (ty(IdxV) != MVT::i32)
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IdxV = DAG.getZExtOrTrunc(IdxV, dl, MVT::i32);
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SDValue OffV = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, WidthV);
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// INSERTRP takes width/offset in a 64-bit pair.
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SDValue CombV = DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64,
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{WidthV, OffV});
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InsV = DAG.getNode(HexagonISD::INSERTRP, dl, ScalarTy,
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{VecV, ValV, CombV});
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}
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return DAG.getNode(ISD::BITCAST, dl, VecTy, InsV);
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}
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SDValue
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HexagonTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
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MVT VT = Op.getValueType().getSimpleVT();
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@ -2701,145 +2796,38 @@ HexagonTargetLowering::LowerEXTRACT_SUBVECTOR_HVX(SDValue Op,
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}
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SDValue
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HexagonTargetLowering::LowerEXTRACT_VECTOR(SDValue Op,
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SelectionDAG &DAG) const {
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// If we are dealing with EXTRACT_SUBVECTOR on a HVX type, we may
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// be able to simplify it to an EXTRACT_SUBREG.
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if (Op.getOpcode() == ISD::EXTRACT_SUBVECTOR && Subtarget.useHVXOps() &&
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Subtarget.isHVXVectorType(Op.getValueType().getSimpleVT()))
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return LowerEXTRACT_SUBVECTOR_HVX(Op, DAG);
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EVT VT = Op.getValueType();
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int VTN = VT.isVector() ? VT.getVectorNumElements() : 1;
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SDLoc dl(Op);
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SDValue Idx = Op.getOperand(1);
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HexagonTargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
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SelectionDAG &DAG) const {
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SDValue Vec = Op.getOperand(0);
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EVT VecVT = Vec.getValueType();
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EVT EltVT = VecVT.getVectorElementType();
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int EltSize = EltVT.getSizeInBits();
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SDValue Width = DAG.getConstant(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT ?
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EltSize : VTN * EltSize, dl, MVT::i64);
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// Constant element number.
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if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Idx)) {
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uint64_t X = CI->getZExtValue();
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SDValue Offset = DAG.getConstant(X * EltSize, dl, MVT::i32);
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const SDValue Ops[] = {Vec, Width, Offset};
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ConstantSDNode *CW = dyn_cast<ConstantSDNode>(Width);
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assert(CW && "Non constant width in LowerEXTRACT_VECTOR");
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SDValue N;
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MVT SVT = VecVT.getSimpleVT();
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uint64_t W = CW->getZExtValue();
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if (W == 1) {
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MVT LocVT = MVT::getIntegerVT(SVT.getSizeInBits());
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SDValue VecCast = DAG.getNode(ISD::BITCAST, dl, LocVT, Vec);
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SDValue Shifted = DAG.getNode(ISD::SRA, dl, LocVT, VecCast, Offset);
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return DAG.getNode(ISD::AND, dl, LocVT, Shifted,
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DAG.getConstant(1, dl, LocVT));
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} else if (W == 32) {
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// Translate this node into EXTRACT_SUBREG.
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unsigned Subreg = (X == 0) ? Hexagon::isub_lo : 0;
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if (X == 0)
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Subreg = Hexagon::isub_lo;
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else if (SVT == MVT::v2i32 && X == 1)
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Subreg = Hexagon::isub_hi;
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else if (SVT == MVT::v4i16 && X == 2)
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Subreg = Hexagon::isub_hi;
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else if (SVT == MVT::v8i8 && X == 4)
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Subreg = Hexagon::isub_hi;
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else
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llvm_unreachable("Bad offset");
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N = DAG.getTargetExtractSubreg(Subreg, dl, MVT::i32, Vec);
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} else if (SVT.getSizeInBits() == 32) {
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N = DAG.getNode(HexagonISD::EXTRACTU, dl, MVT::i32, Ops);
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} else if (SVT.getSizeInBits() == 64) {
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N = DAG.getNode(HexagonISD::EXTRACTU, dl, MVT::i64, Ops);
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if (VT.getSizeInBits() == 32)
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N = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, N);
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} else
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return SDValue();
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return DAG.getNode(ISD::BITCAST, dl, VT, N);
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}
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// Variable element number.
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SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i32, Idx,
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DAG.getConstant(EltSize, dl, MVT::i32));
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SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
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DAG.getConstant(32, dl, MVT::i64));
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SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
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const SDValue Ops[] = {Vec, Combined};
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SDValue N;
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if (VecVT.getSizeInBits() == 32) {
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N = DAG.getNode(HexagonISD::EXTRACTURP, dl, MVT::i32, Ops);
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} else {
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N = DAG.getNode(HexagonISD::EXTRACTURP, dl, MVT::i64, Ops);
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if (VT.getSizeInBits() == 32)
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N = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, N);
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}
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return DAG.getNode(ISD::BITCAST, dl, VT, N);
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MVT ElemTy = ty(Vec).getVectorElementType();
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return extractVector(Vec, Op.getOperand(1), SDLoc(Op), ElemTy, ty(Op), DAG);
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}
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SDValue
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HexagonTargetLowering::LowerINSERT_VECTOR(SDValue Op,
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SelectionDAG &DAG) const {
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EVT VT = Op.getValueType();
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int VTN = VT.isVector() ? VT.getVectorNumElements() : 1;
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SDLoc dl(Op);
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HexagonTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
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SelectionDAG &DAG) const {
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SDValue Vec = Op.getOperand(0);
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SDValue Val = Op.getOperand(1);
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SDValue Idx = Op.getOperand(2);
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EVT VecVT = Vec.getValueType();
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EVT EltVT = VecVT.getVectorElementType();
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int EltSize = EltVT.getSizeInBits();
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SDValue Width = DAG.getConstant(Op.getOpcode() == ISD::INSERT_VECTOR_ELT ?
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EltSize : VTN * EltSize, dl, MVT::i64);
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MVT VecTy = ty(Vec);
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if (Subtarget.useHVXOps() && Subtarget.isHVXVectorType(VecTy))
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return LowerEXTRACT_SUBVECTOR_HVX(Op, DAG);
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if (ConstantSDNode *C = cast<ConstantSDNode>(Idx)) {
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SDValue Offset = DAG.getConstant(C->getSExtValue() * EltSize, dl, MVT::i32);
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const SDValue Ops[] = {Vec, Val, Width, Offset};
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return extractVector(Vec, Op.getOperand(1), SDLoc(Op), ty(Op), ty(Op), DAG);
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}
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SDValue N;
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if (VT.getSizeInBits() == 32)
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N = DAG.getNode(HexagonISD::INSERT, dl, MVT::i32, Ops);
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else if (VT.getSizeInBits() == 64)
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N = DAG.getNode(HexagonISD::INSERT, dl, MVT::i64, Ops);
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else
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return SDValue();
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SDValue
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HexagonTargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
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SelectionDAG &DAG) const {
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MVT VecTy = ty(Op);
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return insertVector(Op.getOperand(0), Op.getOperand(1), Op.getOperand(2),
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SDLoc(Op), VecTy.getVectorElementType(), DAG);
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}
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return DAG.getNode(ISD::BITCAST, dl, VT, N);
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}
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// Variable element number.
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SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i32, Idx,
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DAG.getConstant(EltSize, dl, MVT::i32));
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SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
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DAG.getConstant(32, dl, MVT::i64));
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SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
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if (VT.getSizeInBits() == 64 && Val.getValueSizeInBits() == 32) {
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SDValue C = DAG.getConstant(0, dl, MVT::i32);
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Val = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, Val);
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}
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const SDValue Ops[] = {Vec, Val, Combined};
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SDValue N;
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if (VT.getSizeInBits() == 32)
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N = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i32, Ops);
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else if (VT.getSizeInBits() == 64)
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N = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i64, Ops);
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else
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return SDValue();
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return DAG.getNode(ISD::BITCAST, dl, VT, N);
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SDValue
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HexagonTargetLowering::LowerINSERT_SUBVECTOR(SDValue Op,
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SelectionDAG &DAG) const {
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SDValue ValV = Op.getOperand(1);
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return insertVector(Op.getOperand(0), ValV, Op.getOperand(2),
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SDLoc(Op), ty(ValV), DAG);
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}
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bool
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@ -2894,10 +2882,10 @@ HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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#endif
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llvm_unreachable("Should not custom lower this!");
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case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
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case ISD::INSERT_SUBVECTOR: return LowerINSERT_VECTOR(Op, DAG);
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case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR(Op, DAG);
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case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_VECTOR(Op, DAG);
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case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR(Op, DAG);
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case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
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case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
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case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
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case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
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case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
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case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
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case ISD::SRA:
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@ -117,13 +117,17 @@ namespace HexagonISD {
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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const char *getTargetNodeName(unsigned Opcode) const override;
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SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerEXTRACT_VECTOR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerEXTRACT_SUBVECTOR_HVX(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINSERT_VECTOR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
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@ -269,11 +273,24 @@ namespace HexagonISD {
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return AtomicExpansionKind::LLSC;
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}
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protected:
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private:
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MVT ty(SDValue Op) const {
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return Op.getValueType().getSimpleVT();
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}
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MVT tyScalar(MVT Ty) const {
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if (!Ty.isVector())
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return Ty;
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return MVT::getIntegerVT(Ty.getSizeInBits());
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}
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SDValue buildVector32(ArrayRef<SDValue> Elem, const SDLoc &dl, MVT VecTy,
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SelectionDAG &DAG) const;
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SDValue buildVector64(ArrayRef<SDValue> Elem, const SDLoc &dl, MVT VecTy,
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SelectionDAG &DAG) const;
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SDValue extractVector(SDValue VecV, SDValue IdxV, const SDLoc &dl,
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MVT ValTy, MVT ResTy, SelectionDAG &DAG) const;
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SDValue insertVector(SDValue VecV, SDValue ValV, SDValue IdxV,
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const SDLoc &dl, MVT ValTy, SelectionDAG &DAG) const;
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std::pair<const TargetRegisterClass*, uint8_t>
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findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT)
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