Nigel
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

[X86] Cleanup FCOPYSIGN lowering. NFC intended. 

llvm-svn: 223542
This commit is contained in:
Ahmed Bougacha 2014-12-05 23:11:36 +00:00
parent 22ac8711a5
commit 89bc485085
1 changed files with 15 additions and 29 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

44
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -14461,19 +14461,17 @@ static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
// At this point the operands and the result should have the same
// type, and that won't be f80 since that is not custom lowered.
// First get the sign bit of second operand.
SmallVector<Constant*,4> CV;
if (SrcVT == MVT::f64) {
const fltSemantics &Sem = APFloat::IEEEdouble;
CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
} else {
const fltSemantics &Sem = APFloat::IEEEsingle;
CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
}
const fltSemantics &Sem =
VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
const unsigned SizeInBits = VT.getSizeInBits();
SmallVector<Constant *, 4> CV(
VT == MVT::f64 ? 2 : 4,
ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
// First, clear all bits but the sign bit from the second operand (sign).
CV[0] = ConstantFP::get(*Context,
APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
Constant *C = ConstantVector::get(CV);
SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
@ -14481,21 +14479,9 @@ static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
false, false, false, 16);
SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
// Clear first operand sign bit.
CV.clear();
if (VT == MVT::f64) {
const fltSemantics &Sem = APFloat::IEEEdouble;
CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
APInt(64, ~(1ULL << 63)))));
CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
} else {
const fltSemantics &Sem = APFloat::IEEEsingle;
CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
APInt(32, ~(1U << 31)))));
CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
}
// Next, clear the sign bit from the first operand (magnitude).
CV[0] = ConstantFP::get(
*Context, APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
C = ConstantVector::get(CV);
CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
@ -14503,7 +14489,7 @@ static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
false, false, false, 16);
SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
// Or the value with the sign bit.
// OR the magnitude value with the sign bit.
return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
}