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R600/SI: Simplify verification of AMDGPU::OPERAND_REG_INLINE_C 

llvm-svn: 229751
This commit is contained in:
Marek Olsak 2015-02-18 22:12:41 +00:00
parent b8c818337d
commit 8eeebcccb5
1 changed files with 6 additions and 8 deletions
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10
llvm/lib/Target/R600/SIInstrInfo.cpp
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@ -1151,6 +1151,8 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
return false;
}
int RegClass = Desc.OpInfo[i].RegClass;
switch (Desc.OpInfo[i].OperandType) {
case MCOI::OPERAND_REGISTER:
if (MI->getOperand(i).isImm()) {
@ -1161,14 +1163,11 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
case AMDGPU::OPERAND_REG_IMM32:
break;
case AMDGPU::OPERAND_REG_INLINE_C:
if (MI->getOperand(i).isImm()) {
int RegClass = Desc.OpInfo[i].RegClass;
const TargetRegisterClass *RC = RI.getRegClass(RegClass);
if (!isInlineConstant(MI->getOperand(i), RC->getSize())) {
if (isLiteralConstant(MI->getOperand(i),
RI.getRegClass(RegClass)->getSize())) {
ErrInfo = "Illegal immediate value for operand.";
return false;
}
}
break;
case MCOI::OPERAND_IMMEDIATE:
// Check if this operand is an immediate.
@ -1186,7 +1185,6 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
if (!MI->getOperand(i).isReg())
continue;
int RegClass = Desc.OpInfo[i].RegClass;
if (RegClass != -1) {
unsigned Reg = MI->getOperand(i).getReg();
if (TargetRegisterInfo::isVirtualRegister(Reg))