forked from OSchip/llvm-project
Recognize sign/zero-extended constant BUILD_VECTORs for VMULL operations.
We need to check if the individual vector elements are sign/zero-extended values. For now this only handles constants values. Radar 8687140. llvm-svn: 120034
This commit is contained in:
Bob Wilson
parent
b91ae1ac52
commit
d7d2cf7842
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@ -3860,15 +3860,114 @@ static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
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return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val);
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}
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/// SkipExtension - For a node that is either a SIGN_EXTEND, ZERO_EXTEND, or
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/// an extending load, return the unextended value.
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/// isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each
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/// element has been zero/sign-extended, depending on the isSigned parameter,
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/// from an integer type half its size.
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static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
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bool isSigned) {
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// A v2i64 BUILD_VECTOR will have been legalized to a BITCAST from v4i32.
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EVT VT = N->getValueType(0);
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if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) {
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SDNode *BVN = N->getOperand(0).getNode();
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if (BVN->getValueType(0) != MVT::v4i32 ||
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BVN->getOpcode() != ISD::BUILD_VECTOR)
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return false;
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unsigned LoElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
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unsigned HiElt = 1 - LoElt;
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ConstantSDNode *Lo0 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt));
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ConstantSDNode *Hi0 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt));
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ConstantSDNode *Lo1 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt+2));
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ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2));
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if (!Lo0 || !Hi0 || !Lo1 || !Hi1)
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return false;
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if (isSigned) {
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if (Hi0->getSExtValue() == Lo0->getSExtValue() >> 32 &&
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Hi1->getSExtValue() == Lo1->getSExtValue() >> 32)
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return true;
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} else {
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if (Hi0->isNullValue() && Hi1->isNullValue())
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return true;
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}
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return false;
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}
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if (N->getOpcode() != ISD::BUILD_VECTOR)
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return false;
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for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
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SDNode *Elt = N->getOperand(i).getNode();
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
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unsigned EltSize = VT.getVectorElementType().getSizeInBits();
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unsigned HalfSize = EltSize / 2;
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if (isSigned) {
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int64_t SExtVal = C->getSExtValue();
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if ((SExtVal >> HalfSize) != (SExtVal >> EltSize))
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return false;
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} else {
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if ((C->getZExtValue() >> HalfSize) != 0)
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return false;
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}
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continue;
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}
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return false;
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}
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return true;
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}
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/// isSignExtended - Check if a node is a vector value that is sign-extended
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/// or a constant BUILD_VECTOR with sign-extended elements.
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static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
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if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N))
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return true;
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if (isExtendedBUILD_VECTOR(N, DAG, true))
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return true;
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return false;
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}
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/// isZeroExtended - Check if a node is a vector value that is zero-extended
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/// or a constant BUILD_VECTOR with zero-extended elements.
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static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
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if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N))
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return true;
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if (isExtendedBUILD_VECTOR(N, DAG, false))
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return true;
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return false;
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}
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/// SkipExtension - For a node that is a SIGN_EXTEND, ZERO_EXTEND, extending
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/// load, or BUILD_VECTOR with extended elements, return the unextended value.
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static SDValue SkipExtension(SDNode *N, SelectionDAG &DAG) {
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if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
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return N->getOperand(0);
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LoadSDNode *LD = cast<LoadSDNode>(N);
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if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
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return DAG.getLoad(LD->getMemoryVT(), N->getDebugLoc(), LD->getChain(),
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LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(),
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LD->isNonTemporal(), LD->getAlignment());
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// Otherwise, the value must be a BUILD_VECTOR. For v2i64, it will
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// have been legalized as a BITCAST from v4i32.
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if (N->getOpcode() == ISD::BITCAST) {
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SDNode *BVN = N->getOperand(0).getNode();
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assert(BVN->getOpcode() == ISD::BUILD_VECTOR &&
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BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR");
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unsigned LowElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
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return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), MVT::v2i32,
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BVN->getOperand(LowElt), BVN->getOperand(LowElt+2));
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}
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// Construct a new BUILD_VECTOR with elements truncated to half the size.
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assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
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EVT VT = N->getValueType(0);
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unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
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unsigned NumElts = VT.getVectorNumElements();
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MVT TruncVT = MVT::getIntegerVT(EltSize);
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SmallVector<SDValue, 8> Ops;
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for (unsigned i = 0; i != NumElts; ++i) {
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ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
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const APInt &CInt = C->getAPIntValue();
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Ops.push_back(DAG.getConstant(APInt(CInt).trunc(EltSize), TruncVT));
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}
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return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
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MVT::getVectorVT(TruncVT, NumElts), Ops.data(), NumElts);
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}
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static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
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@ -3879,19 +3978,16 @@ static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
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SDNode *N0 = Op.getOperand(0).getNode();
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SDNode *N1 = Op.getOperand(1).getNode();
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unsigned NewOpc = 0;
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if ((N0->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N0)) &&
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(N1->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N1))) {
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if (isSignExtended(N0, DAG) && isSignExtended(N1, DAG))
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NewOpc = ARMISD::VMULLs;
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} else if ((N0->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N0)) &&
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(N1->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N1))) {
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else if (isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG))
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NewOpc = ARMISD::VMULLu;
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} else if (VT == MVT::v2i64) {
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else if (VT == MVT::v2i64)
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// Fall through to expand this. It is not legal.
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return SDValue();
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} else {
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else
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// Other vector multiplications are legal.
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return Op;
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}
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// Legalize to a VMULL instruction.
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DebugLoc DL = Op.getDebugLoc();
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@ -267,3 +267,75 @@ entry:
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}
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declare <8 x i16> @llvm.arm.neon.vmullp.v8i16(<8 x i8>, <8 x i8>) nounwind readnone
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; Radar 8687140
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; VMULL needs to recognize BUILD_VECTORs with sign/zero-extended elements.
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define <8 x i16> @vmull_extvec_s8(<8 x i8> %arg) nounwind {
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; CHECK: vmull_extvec_s8
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; CHECK: vmull.s8
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%tmp3 = sext <8 x i8> %arg to <8 x i16>
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%tmp4 = mul <8 x i16> %tmp3, <i16 -12, i16 -12, i16 -12, i16 -12, i16 -12, i16 -12, i16 -12, i16 -12>
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ret <8 x i16> %tmp4
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}
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define <8 x i16> @vmull_extvec_u8(<8 x i8> %arg) nounwind {
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; CHECK: vmull_extvec_u8
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; CHECK: vmull.u8
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%tmp3 = zext <8 x i8> %arg to <8 x i16>
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%tmp4 = mul <8 x i16> %tmp3, <i16 12, i16 12, i16 12, i16 12, i16 12, i16 12, i16 12, i16 12>
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ret <8 x i16> %tmp4
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}
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define <8 x i16> @vmull_noextvec_s8(<8 x i8> %arg) nounwind {
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; Do not use VMULL if the BUILD_VECTOR element values are too big.
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; CHECK: vmull_noextvec_s8
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; CHECK: vmovl.s8
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; CHECK: vmul.i16
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%tmp3 = sext <8 x i8> %arg to <8 x i16>
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%tmp4 = mul <8 x i16> %tmp3, <i16 -999, i16 -999, i16 -999, i16 -999, i16 -999, i16 -999, i16 -999, i16 -999>
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ret <8 x i16> %tmp4
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}
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define <8 x i16> @vmull_noextvec_u8(<8 x i8> %arg) nounwind {
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; Do not use VMULL if the BUILD_VECTOR element values are too big.
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; CHECK: vmull_noextvec_u8
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; CHECK: vmovl.u8
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; CHECK: vmul.i16
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%tmp3 = zext <8 x i8> %arg to <8 x i16>
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%tmp4 = mul <8 x i16> %tmp3, <i16 999, i16 999, i16 999, i16 999, i16 999, i16 999, i16 999, i16 999>
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ret <8 x i16> %tmp4
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}
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define <4 x i32> @vmull_extvec_s16(<4 x i16> %arg) nounwind {
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; CHECK: vmull_extvec_s16
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; CHECK: vmull.s16
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%tmp3 = sext <4 x i16> %arg to <4 x i32>
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%tmp4 = mul <4 x i32> %tmp3, <i32 -12, i32 -12, i32 -12, i32 -12>
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ret <4 x i32> %tmp4
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}
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define <4 x i32> @vmull_extvec_u16(<4 x i16> %arg) nounwind {
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; CHECK: vmull_extvec_u16
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; CHECK: vmull.u16
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%tmp3 = zext <4 x i16> %arg to <4 x i32>
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%tmp4 = mul <4 x i32> %tmp3, <i32 1234, i32 1234, i32 1234, i32 1234>
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ret <4 x i32> %tmp4
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}
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define <2 x i64> @vmull_extvec_s32(<2 x i32> %arg) nounwind {
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; CHECK: vmull_extvec_s32
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; CHECK: vmull.s32
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%tmp3 = sext <2 x i32> %arg to <2 x i64>
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%tmp4 = mul <2 x i64> %tmp3, <i64 -1234, i64 -1234>
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ret <2 x i64> %tmp4
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}
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define <2 x i64> @vmull_extvec_u32(<2 x i32> %arg) nounwind {
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; CHECK: vmull_extvec_u32
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; CHECK: vmull.u32
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%tmp3 = zext <2 x i32> %arg to <2 x i64>
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%tmp4 = mul <2 x i64> %tmp3, <i64 1234, i64 1234>
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ret <2 x i64> %tmp4
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}
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