1. Add VMV_V_X in emitEpilogue.
2. Change all the positive numbers added by TP to negative numbers(in LowerCall).
3. Fix the LowerCall function to generate correct store instruction transferring the function parameters.
4. Fix hasReservedCallFrame function to return false.
5. Align the convention between caller and callee in the case of passing parameters by stack.
6. Change the stack offset calculation method of TP.
7. Unify the calculation of TP stack and SP stack offset.
8. Node that needing to manually modify the calculation of sp offset in the workitem.S. Since the growth direction of the stack is different from that of the traditional RISCV, it is now stipulated that for both the SP stack and the TP stack, the data is stored where the stack pointer is not offset.
9. There is a SPAdj check in eliminateFrameIndex function. but we don't need this value at all so that adding a getSPAdjust function to return zero.
10. V33 is a wrong value when parameters pushed to TP stack so there must be a MV instruction to refresh V33 after ADJCALLSTACKDOWN.
Summary: LegaLegalized vector parameters, but not been added FileCheck now.
Test Plan: Legalized vector parameters
Differential Revision: http://www.tpt.com/D740
Summary: LegaLegalized vector parameters, but not been added FileCheck now.
Test Plan: Legalized vector parameters
Differential Revision: http://www.tpt.com/D740
Summary:
fix addi instruction, there will be a hardware error when immediate is
negative number.
Test Plan: fix add instruction
Reviewers: zhoujing
Subscribers: zhoujing
Differential Revision: http://www.tpt.com/D722
Signed-off-by: qinfan <qinfan.wang@terapines.com>
In standard riscv vararg support, the varstart frame index will be stored in stack,
but because if the design of ventus, some code generation will be like this
vlw.v v0, -44(v8)
vadd.vi v1, v0, 4
vsw.v v1, -44(v8)
\vlw12.v v0, 0(v0)
the last vlw12 instruction is actually illeagl, it should be vlw
In our previous calling convention design, all non-kernel arguments are passed
by VGPRS or TP stack, but when the arguments point to private memory address
space, the wrong memory access instructions will be generated, because private
memory based address is scalar register
Cause there are two stacks in Ventus, we need to seperate TP stack and SP stack,
this commit just add very initial support for TP stack size calculation
We adjust the stack growing direction early months for OpenCL, in order to be
compatible with current architecture, we need to do some modification to
support vararg
Jules-Kong
zhoujing
Aries