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1121 Commits

Author SHA1 Message Date
Rafael Espindola 063f177300 Make ARM an X86 memcpy expansion more similar to each other. 
Now both subtarget define getMaxInlineSizeThreshold and the expansion uses it.

This should not change generated code.

llvm-svn: 43552
 2007-10-31 11:52:06 +00:00
Evan Cheng 1f2dd35898 Fix memcpy lowering when addresses are 4-byte aligned but size is not multiple of 4. 
llvm-svn: 43234
 2007-10-22 22:11:27 +00:00
Rafael Espindola 18a831d783 split LowerMEMCPY into LowerMEMCPYCall and LowerMEMCPYInline in the ARM backend. 
llvm-svn: 43176
 2007-10-19 14:35:17 +00:00
Chris Lattner 84f3461c49 legalizing the ret operation on f64 shouldn't introduce a new 
i64 bit convert needlessly.

llvm-svn: 43116
 2007-10-18 06:17:07 +00:00
Dan Gohman 482732af9d Set ISD::FPOW to Expand. 
llvm-svn: 42881
 2007-10-11 23:21:31 +00:00
Dan Gohman a160361c85 Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} to 
use ISD::{S,U}DIVREM and ISD::{S,U}MUL_HIO. Move the lowering code
associated with these operators into target-independent in LegalizeDAG.cpp
and TargetLowering.cpp.

llvm-svn: 42762
 2007-10-08 18:33:35 +00:00
Duncan Sands 86e0119822 Fold the adjust_trampoline intrinsic into 
init_trampoline.  There is now only one
trampoline intrinsic.

llvm-svn: 41841
 2007-09-11 14:10:23 +00:00
Dale Johannesen 3cf889f75e Enhance APFloat to retain bits of NaNs (fixes oggenc). 
Use APFloat interfaces for more references, mostly
of ConstantFPSDNode.

llvm-svn: 41632
 2007-08-31 04:03:46 +00:00
Duncan Sands 644f917358 Support for trampolines, except for X86 codegen which is 
still under discussion.

llvm-svn: 40549
 2007-07-27 12:58:54 +00:00
Gabor Greif e16561cd5d Here is the bulk of the sanitizing. 
Almost all occurrences of "bytecode" in the sources have been eliminated.

llvm-svn: 37913
 2007-07-05 17:07:56 +00:00
Evan Cheng 94f04c6fc9 Reflects the chanegs made to PredicateOperand. 
llvm-svn: 37898
 2007-07-05 07:18:20 +00:00
Evan Cheng 335c65e9a4 Silence a warning. 
llvm-svn: 37737
 2007-06-26 18:31:22 +00:00
Dan Gohman 309d3d51b3 Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from 
TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.

llvm-svn: 37704
 2007-06-22 14:59:07 +00:00
Evan Cheng 77d61e6f6d Be more conservative of duplicating blocks. 
llvm-svn: 37669
 2007-06-19 23:55:02 +00:00
Evan Cheng c3c949b473 Allow predicated immediate ARM to ARM calls. 
llvm-svn: 37659
 2007-06-19 21:05:09 +00:00
Evan Cheng 256144de4a Set ARM ifcvt duplication limit to 3 for now. 
llvm-svn: 37385
 2007-06-01 08:28:59 +00:00
Evan Cheng ea623560f8 Silence some compilation warnings. 
llvm-svn: 37197
 2007-05-18 01:19:57 +00:00
Evan Cheng 6addd65914 Set ARM if-conversion block size threshold to 10 instructions for now. 
llvm-svn: 37194
 2007-05-18 00:19:34 +00:00
Dale Johannesen 58698d2534 More effective breakdown of memcpy into repeated load/store. These are now 
in the order lod;lod;lod;sto;sto;sto which means the load-store optimizer
has a better chance of producing ldm/stm.  Ideally you would get cooperation
from the RA as well but this is not there yet.

llvm-svn: 37179
 2007-05-17 21:31:21 +00:00
Lauro Ramos Venancio 1b8d46ab21 Fix previous patch. GOTOFF can be used only when the symbol has internal 
linkage or hidden visibility.

llvm-svn: 37055
 2007-05-14 23:20:21 +00:00
Lauro Ramos Venancio d705f5d51d Optimize PIC implementation. GOTOFF can be used when the symbol is defined 
and used in the same module.

llvm-svn: 37044
 2007-05-14 18:46:23 +00:00
Evan Cheng 33c9886001 On Mac OS X, GV requires an extra load only when relocation-model is non-static. 
llvm-svn: 36718
 2007-05-04 00:26:58 +00:00
Lauro Ramos Venancio 83930198dd Debug support for arm-linux. 
Patch by Raul Herbster.

llvm-svn: 36690
 2007-05-03 20:28:35 +00:00
Evan Cheng bef131de68 Typo. It's checking if V is multiple of 4, not multiple of 3. :-) 
llvm-svn: 36663
 2007-05-03 02:00:18 +00:00
Lauro Ramos Venancio c39c12a3fa ARM TLS: implement "general dynamic", "initial exec" and "local exec" models. 
llvm-svn: 36506
 2007-04-27 13:54:47 +00:00
Evan Cheng c9f22fd1a4 Darwin runtime library does not have these. 
llvm-svn: 36505
 2007-04-27 08:15:43 +00:00
Lauro Ramos Venancio ee2d164f0f Implement PIC for arm-linux. 
llvm-svn: 36324
 2007-04-22 00:04:12 +00:00
Chris Lattner 502c3f48d9 arm has r+r*s and r+i addr modes, but no r+i+r*s addr modes. 
llvm-svn: 35962
 2007-04-13 06:50:55 +00:00
Chris Lattner fe926e2960 Fix incorrect fall-throughs in addr mode code. This fixes CodeGen/ARM/arm-negative-stride.ll 
llvm-svn: 35909
 2007-04-11 16:17:12 +00:00
Chris Lattner 9b6d69e0c2 restore support for negative strides 
llvm-svn: 35859
 2007-04-10 03:48:29 +00:00
Chris Lattner d44e24c896 remove dead target hooks 
llvm-svn: 35846
 2007-04-09 23:33:39 +00:00
Chris Lattner 39f65335d5 remove some dead target hooks, subsumed by isLegalAddressingMode 
llvm-svn: 35840
 2007-04-09 22:27:04 +00:00
Evan Cheng bd31f41daa Typo. 
llvm-svn: 35639
 2007-04-04 00:06:07 +00:00
Chris Lattner f742e2fe70 Arm supports negative strides as well, add them. This lets us compile: 
CodeGen/ARM/arm-negative-stride.ll to:

LBB1_2: @bb
        str r1, [r3, -r0, lsl #2]
        add r0, r0, #1
        cmp r0, r2
        bne LBB1_2      @bb

llvm-svn: 35609
 2007-04-03 00:13:57 +00:00
Chris Lattner 8e168a4f36 fix the CodeGen/ARM/2007-03-13-InstrSched.ll regression: allow IV's with scales 
to be folded into non-store instructions.

llvm-svn: 35601
 2007-04-02 18:51:18 +00:00
Chris Lattner 6223e83f6d add support for the 'w' inline asm register class. 
llvm-svn: 35598
 2007-04-02 17:24:08 +00:00
Lauro Ramos Venancio 6be85337b0 - Divides the comparisons in two types: comparisons that only use N and Z 
flags (ARMISD::CMPNZ) and comparisons that use all flags (ARMISD::CMP).
- Defines the instructions: TST, TEQ (ARM) and TST (Thumb).

llvm-svn: 35573
 2007-04-02 01:30:03 +00:00
Evan Cheng 17d48a8bc2 Add i16 address mode. 
llvm-svn: 35551
 2007-04-01 08:06:46 +00:00
Chris Lattner 1eb94d973a implement the new addressing mode description hook. 
llvm-svn: 35521
 2007-03-30 23:15:24 +00:00
Evan Cheng c2cba18f2b Remove isLegalAddressImmediate. 
llvm-svn: 35406
 2007-03-28 01:53:55 +00:00
Lauro Ramos Venancio 143b0dff31 bugfix: sometimes the spiller puts a load between the "mov lr, pc" and "bx" of a CALL_NOLINK. 
llvm-svn: 35381
 2007-03-27 16:19:21 +00:00
Chris Lattner d685514e2e switch TargetLowering::getConstraintType to take the entire constraint, 
not just the first letter.  No functionality change.

llvm-svn: 35322
 2007-03-25 02:14:49 +00:00
Dale Johannesen 0c6bb5eab7 repair x86 performance, dejagnu problems from previous change 
llvm-svn: 35245
 2007-03-21 21:51:52 +00:00
Dale Johannesen bacf4acf65 do not share old induction variables when this would result in invalid 
instructions (that would have to be split later)

llvm-svn: 35227
 2007-03-20 21:54:54 +00:00
Lauro Ramos Venancio a88c4a74f3 bugfix: When the source register of CALL_NOLINK was LR, the following code was emitted: 
mov lr, pc
    bx lr
So, the function was not called.

llvm-svn: 35218
 2007-03-20 17:57:23 +00:00
Chris Lattner f806e1cdbc fix indentation 
llvm-svn: 35202
 2007-03-20 02:25:53 +00:00
Evan Cheng 9bb01c9f4f Fix naming inconsistencies. 
llvm-svn: 35163
 2007-03-19 07:48:02 +00:00
Lauro Ramos Venancio 25d4052af6 Only ARMv6 has BSWAP. 
Fix MultiSource/Applications/aha test.

llvm-svn: 35128
 2007-03-16 22:54:16 +00:00
Evan Cheng 0e34d6af6b Added isLegalAddressExpression(). Only allows X +/- C for now. 
llvm-svn: 35122
 2007-03-16 08:43:56 +00:00
Evan Cheng 507eefa757 Zero is always a legal AM immediate. 
llvm-svn: 35087
 2007-03-13 20:37:59 +00:00
Evan Cheng 2150b9286f Updated TargetLowering LSR addressing mode hooks for ARM and Thumb. 
llvm-svn: 35075
 2007-03-12 23:30:29 +00:00
Evan Cheng 63170b6959 Fix a typo. 
llvm-svn: 35030
 2007-03-08 21:59:30 +00:00
Anton Korobeynikov ed4b303c10 Refactoring of formal parameter flags. Enable properly use of 
zext/sext/aext stuff.

llvm-svn: 35008
 2007-03-07 16:25:09 +00:00
Anton Korobeynikov e7ec3bc7bc Use new SDIselParamAttr enumeration. This removes "magick" constants 
from formal attributes' flags processing.

llvm-svn: 34963
 2007-03-06 08:12:33 +00:00
Lauro Ramos Venancio 3e906c48d3 Fix stack alignment in functions with varargs. 
llvm-svn: 34532
 2007-02-23 20:32:57 +00:00
Jim Laskey e0008e23cf Simplify lowering and selection of exception ops. 
llvm-svn: 34488
 2007-02-22 14:56:36 +00:00
Jim Laskey 3796abea0f Support to provide exception and selector registers. 
llvm-svn: 34482
 2007-02-21 22:54:50 +00:00
Lauro Ramos Venancio 603f201cba According to ARM EABI, 8-bytes function arguments must be 8-bytes aligned. 
llvm-svn: 34241
 2007-02-13 14:07:13 +00:00
Evan Cheng 4b6c8f7f5e Fix comments. 
llvm-svn: 33831
 2007-02-03 08:53:01 +00:00
Evan Cheng 48b094d9dd Fix a bug in getARMCMP (which translate CondCode to ARM specific CC) when the RHS is a constant. 
llvm-svn: 33775
 2007-02-02 01:53:26 +00:00
Evan Cheng 9b9e4ae796 Thumb does not have clz. 
llvm-svn: 33773
 2007-02-01 23:34:03 +00:00
Evan Cheng 143576ddd2 Specify the right CC for comparison libcalls. 
llvm-svn: 33702
 2007-01-31 09:30:58 +00:00
Evan Cheng 491fcdb49b Observe -soft-float. 
llvm-svn: 33699
 2007-01-31 08:40:13 +00:00
Evan Cheng 83f35170fa - Fix codegen for pc relative constant (e.g. JT) in thumb mode: 
.set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
        add r1, pc, #PCRELV0
This is not legal since add r1, pc, #c requires the constant be a multiple of 4.
Do the following instead:
        .set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
        mov r1, #PCRELV0
        add r1, pc

- In thumb mode, it's not possible to use .set generate a pc relative stub
  address. The stub is ARM code which is in a different section from the thumb
  code. Load the value from a constpool instead.
- Some asm printing clean up.

llvm-svn: 33664
 2007-01-30 20:37:08 +00:00
Reid Spencer 5301e7c605 For PR1136: Rename GlobalVariable::isExternal as isDeclaration to avoid 
confusion with external linkage types.

llvm-svn: 33663
 2007-01-30 20:08:39 +00:00
Nate Begeman eda5997cc8 Finish off bug 680, allowing targets to custom lower frame and return 
address nodes.

llvm-svn: 33636
 2007-01-29 22:58:52 +00:00
Anton Korobeynikov 037c867b54 Propagate changes from my local tree. This patch includes: 
1. New parameter attribute called 'inreg'. It has meaning "place this
parameter in registers, if possible". This is some generalization of
gcc's regparm(n) attribute. It's currently used only in X86-32 backend.
2. Completely rewritten CC handling/lowering code inside X86 backend.
Merged stdcall + c CCs and fastcall + fast CC.
3. Dropped CSRET CC. We cannot add struct return variant for each
target-specific CC (e.g. stdcall + csretcc and so on).
4. Instead of CSRET CC introduced 'sret' parameter attribute. Setting in
on first attribute has meaning 'This is hidden pointer to structure
return. Handle it gently'.
5. Fixed small bug in llvm-extract + add new feature to
FunctionExtraction pass, which relinks all internal-linkaged callees
from deleted function to external linkage. This will allow further
linking everything together.

NOTEs: 1. Documentation will be updated soon.
       2. llvm-upgrade should be improved to translate csret => sret.
          Before this, there will be some unexpected test fails.
llvm-svn: 33597
 2007-01-28 13:31:35 +00:00
Jim Laskey f9e5445ed4 Make LABEL a builtin opcode. 
llvm-svn: 33537
 2007-01-26 14:34:52 +00:00
Evan Cheng 52189b5805 Use bl to call Thumb fuctions directly. 
llvm-svn: 33433
 2007-01-22 19:40:10 +00:00
Evan Cheng bf216c364f isDarwin -> isTargetDarwin 
llvm-svn: 33366
 2007-01-19 19:28:01 +00:00
Evan Cheng 10043e215b ARM backend contribution from Apple. 
llvm-svn: 33353
 2007-01-19 07:51:42 +00:00