12c6982b3b
[mips][microMIPS] Implement LWSP and SWSP instructions
...
Differential Revision: http://reviews.llvm.org/D6416
llvm-svn: 224771
2014-12-23 16:16:33 +00:00
4b1eac4dda
[Hexagon] Adding memb instruction. Fixing whitespace in test from 224730.
...
llvm-svn: 224735
2014-12-22 21:40:43 +00:00
af1e5de141
[Hexagon] Adding classes and load unsigned byte instruction, updating usages.
...
llvm-svn: 224730
2014-12-22 21:20:03 +00:00
0f850bde0e
[Hexagon] Removing old variants of instructions and updating references.
...
llvm-svn: 224612
2014-12-19 20:29:29 +00:00
38ce8cd2e2
[Hexagon] Adding bit extraction and table indexing instructions.
...
llvm-svn: 224610
2014-12-19 20:01:08 +00:00
3c7f664d5a
[Hexagon] Adding bit insertion instructions.
...
llvm-svn: 224609
2014-12-19 19:54:38 +00:00
d63ef93b4b
[Hexagon] Adding more xtype shift instructions.
...
llvm-svn: 224608
2014-12-19 19:51:35 +00:00
cc09d1ccc5
[Hexagon] Adding xtype shift instructions.
...
llvm-svn: 224604
2014-12-19 19:34:50 +00:00
f3db884efb
[Hexagon] Adding transfers to and from control registers.
...
llvm-svn: 224599
2014-12-19 19:06:32 +00:00
5ccbb1298b
[Hexagon] Adding loop0/1 sp0/1/2loop0 instructions.
...
llvm-svn: 224556
2014-12-19 00:06:53 +00:00
174476ed96
Reverting 224550, was not ready for commit.
...
llvm-svn: 224552
2014-12-18 23:36:15 +00:00
9000481cda
[Hexagon] Adding loop0/1 sp0/1/2loop0 instructions.
...
llvm-svn: 224550
2014-12-18 23:27:51 +00:00
aa1bade7b4
[Hexagon] Updating doubleword shift usages to new versions.
...
llvm-svn: 224391
2014-12-16 23:36:15 +00:00
f5acc8c625
[Hexagon] Adding tstbit/bitclr/bitset instructions.
...
llvm-svn: 224374
2014-12-16 21:28:58 +00:00
615757f2f1
[Hexagon] Adding bit count and twiddling instructions.
...
llvm-svn: 224367
2014-12-16 20:57:56 +00:00
6fce46baf6
[Hexagon] Adding asr/lsr/asl reg/imm, asl with saturation, asr with rounding. Doubleword abs/neg/not. Interleave and deinterleave instructions.
...
llvm-svn: 224365
2014-12-16 20:40:23 +00:00
1944a8cd04
[Hexagon] Adding absolute value, and negate with saturation
...
llvm-svn: 224346
2014-12-16 17:44:49 +00:00
455f24aa77
[Hexagon] Adding saturate and swizzle instructions.
...
llvm-svn: 224343
2014-12-16 16:27:17 +00:00
2deca34803
[mips][microMIPS] Implement SWP and LWP instructions
...
Differential Revision: http://reviews.llvm.org/D5667
llvm-svn: 224338
2014-12-16 14:59:10 +00:00
a489a631ae
Add disassembler tests for mips4 platform. There are no functional changes.
...
llvm-svn: 224335
2014-12-16 13:02:25 +00:00
d9a00a9c38
[Hexagon] Adding doubleword multiplies with and without accumulation.
...
llvm-svn: 224293
2014-12-16 00:07:24 +00:00
18c927620a
[Hexagon] Adding halfword to doubleword multiplies.
...
llvm-svn: 224289
2014-12-15 23:29:37 +00:00
64ffd52943
[Hexagon] Adding logical-logical accumulation instructions and tests.
...
llvm-svn: 224288
2014-12-15 23:19:07 +00:00
71e11a1d0d
[Hexagon] Adding a number of additional multiply forms with tests.
...
llvm-svn: 224282
2014-12-15 22:10:37 +00:00
4a46429305
[Hexagon] Adding misc multiply encodings and tests.
...
llvm-svn: 224273
2014-12-15 21:17:03 +00:00
26f884aedf
[Hexagon] Adding doubleworld accumulating multiplies of halfwords.
...
llvm-svn: 224267
2014-12-15 20:17:46 +00:00
572c53e258
[Hexagon] Adding accumulating half word multiplies.
...
llvm-svn: 224266
2014-12-15 20:10:28 +00:00
d1704cdc07
[Hexagon] Adding multiply with rnd/sat/rndsat
...
llvm-svn: 224265
2014-12-15 20:01:59 +00:00
fe4012a969
[Hexagon] Adding encoding bits for halfword multiplies.
...
llvm-svn: 224261
2014-12-15 19:22:07 +00:00
b736bf3899
Move mips1 tests to test/MC/Disassembler/Mips/mips1
...
This matches the pattern of the mips2 and 3 tests, as well as our normal
conventions.
llvm-svn: 224254
2014-12-15 17:56:02 +00:00
d7ecf49e97
Add disassembler tests for mips3 platform. There are no functional changes.
...
llvm-svn: 224253
2014-12-15 16:19:34 +00:00
19703a0bd6
Add disassembler tests for mips2 platform. There are no functional changes.
...
llvm-svn: 224252
2014-12-15 15:58:20 +00:00
a67937331d
This is the first in a series of patches that add missing disassembler tests for mips platform. The patches are divided per version of mips CPU to keep the patches smaller and ease the review. There are no functional changes, code is changed only if new tests reveal a bug.This patch adds disassembler tests for mips1 CPU.
...
llvm-svn: 224251
2014-12-15 15:22:33 +00:00
90482a77b1
[Hexagon] Adding double word add/min/minu/max/maxu instructions and tests.
...
llvm-svn: 224153
2014-12-12 21:29:25 +00:00
984ef17d66
[Hexagon] Adding J class call instructions.
...
llvm-svn: 224150
2014-12-12 21:12:27 +00:00
eb52f69f59
[Hexagon] Adding encoding information for sign extend word instruction.
...
llvm-svn: 224026
2014-12-11 16:43:06 +00:00
220adb6370
[Hexagon] Adding combine ri/ir instructions.
...
llvm-svn: 223971
2014-12-10 22:23:07 +00:00
db0b13cef0
[Hexagon] Adding encodings for JR class instructions. Updating complier usages.
...
llvm-svn: 223967
2014-12-10 21:24:10 +00:00
8872d20788
[Hexagon] Adding JR class predicated call reg instructions.
...
llvm-svn: 223933
2014-12-10 18:24:16 +00:00
b030c254c0
[Hexagon] Fixing broken tests.
...
llvm-svn: 223823
2014-12-09 20:36:53 +00:00
4af437fee5
[Hexagon] Updating rr/ri 32/64 transfer encodings and adding tests.
...
llvm-svn: 223821
2014-12-09 20:23:30 +00:00
b580d7d8c8
[Hexagon] Adding word combine dot-new form and replacing old combine opcode.
...
llvm-svn: 223815
2014-12-09 19:23:45 +00:00
30dcb232b0
[Hexagon] Updating predicate register transfers and adding tstbit to allow select selection. Updating ll tests with predicate transfers that previously had nop encodings.
...
llvm-svn: 223800
2014-12-09 18:16:49 +00:00
f5b4d655d2
[Hexagon] Adding any8, all8, and/or/xor/andn/orn/not predicate register forms, mask, and vitpack instructions and patterns.
...
llvm-svn: 223710
2014-12-08 23:07:59 +00:00
df96b071f1
[Hexagon] Fixing broken test.
...
llvm-svn: 223704
2014-12-08 22:29:06 +00:00
b6c4dd96f9
[Hexagon] Adding xtype doubleword add, sub, and, or, xor and patterns.
...
llvm-svn: 223702
2014-12-08 22:19:14 +00:00
9bfe5473da
[Hexagon] Adding xtype doubleword comparisons. Removing unused multiclass.
...
llvm-svn: 223701
2014-12-08 21:56:47 +00:00
025f860638
[Hexagon] Adding xtype parity, min, minu, max, maxu instructions.
...
llvm-svn: 223693
2014-12-08 21:19:18 +00:00
8d1376c60e
[Hexagon] Adding xtype halfword add/sub ll/hl/lh/hh/sat/<<16 instructions.
...
llvm-svn: 223692
2014-12-08 20:33:01 +00:00
cc46cd8eec
[Hexagon] Adding add/sub with saturation. Removing unused def. Cleaning up shift patterns.
...
llvm-svn: 223680
2014-12-08 18:33:49 +00:00
b56e6cd9b9
[Hexagon] Adding combine reg, reg with predicated forms.
...
llvm-svn: 223667
2014-12-08 17:33:06 +00:00
a55070dbdd
[Hexagon] Adding packhl instruction.
...
llvm-svn: 223664
2014-12-08 17:01:18 +00:00
2c77a35e6e
[Hexagon] Adding sub/and/or reg, imm forms
...
llvm-svn: 223522
2014-12-05 21:38:29 +00:00
9665f98c10
[Hexagon] Updating mux_ir/ri/ii/rr with encoding bits
...
llvm-svn: 223515
2014-12-05 21:09:27 +00:00
19985e9a8d
[Hexagon] Adding tfrih/l instructions.
...
llvm-svn: 223506
2014-12-05 20:07:19 +00:00
a4ab58101a
[Hexagon] Adding add reg, imm form with encoding bits and test.
...
llvm-svn: 223504
2014-12-05 19:51:23 +00:00
383c36e3a8
[Hexagon] Adding DoubleRegs decoder. Moving C2_mux and A2_nop. Adding combine imm-imm form.
...
llvm-svn: 223494
2014-12-05 18:24:06 +00:00
7f0a430c7d
[Hexagon] Adding combine reg-reg forms.
...
llvm-svn: 223485
2014-12-05 17:38:36 +00:00
01785bb063
[Hexagon] Marking several instructions as isCodeGenOnly=0 and adding direct disassembly tests for many instructions.
...
llvm-svn: 223482
2014-12-05 17:27:39 +00:00
2c08dc33db
[Hexagon] Adding lit exception if Hexagon isn't built.
...
llvm-svn: 223335
2014-12-04 04:28:38 +00:00
5d6f03bd5a
[Hexagon] Marking some instructions as CodeGenOnly=0 and adding disassembly tests.
...
llvm-svn: 223334
2014-12-04 03:41:21 +00:00
a0199b9a59
Add support for ARM modified-immediate assembly syntax.
...
Certain ARM instructions accept 32-bit immediate operands encoded as a 8-bit
integer value (0-255) and a 4-bit rotation (0-30, even). Current ARM assembly
syntax support in LLVM allows the decoded (32-bit) immediate to be specified
as a single immediate operand for such instructions:
mov r0, #4278190080
The ARMARM defines an extended assembly syntax allowing the encoding to be made
more explicit, as in:
mov r0, #255 , #8 ; (same 32-bit value as above)
The behaviour of the two instructions can be different w.r.t flags, which is
documented under "Modified immediate constants" in ARMARM. This patch enables
support for this extended syntax at the MC layer.
llvm-svn: 223113
2014-12-02 10:53:20 +00:00
b682ddf33a
The andi16, addiusp and jraddiusp micromips instructions were missing dedicated decoder methods in MipsDisassembler.cpp to properly decode immediate operands. These methods are added together with corresponding tests.
...
llvm-svn: 223006
2014-12-01 11:12:04 +00:00
30895f9ab8
Add post-decode checking of HVC instruction.
...
Add checkDecodedInstruction for post-decode checking of instructions, to catch
the corner cases like HVC that don't fit into the general pattern. Needed to
check for an invalid condition field in instruction encoding despite HVC not
taking a predicate.
Patch by Matthew Wahab.
Change-Id: I48e28de981d7a9e43569594da3c45fb478b4f795
llvm-svn: 222992
2014-12-01 08:50:27 +00:00
7de905cd17
Add Thumb HVC and ERET virtualisation extension instructions.
...
Patch by Matthew Wahab.
Change-Id: I131f71c1150d5fa797066a18e09d526c19bf9016
llvm-svn: 222990
2014-12-01 08:39:19 +00:00
4d88ae2002
Add ARM ERET and HVC virtualisation extension instructions.
...
Patch by Matthew Wahab.
Change-Id: Iad75f078fbaa4ecc7d7a4820ad9b3930679cbbbb
llvm-svn: 222989
2014-12-01 08:33:28 +00:00
378107daa4
[PowerPC] Add asm support for cache-inhibited ld/st instructions
...
Add assembler support for the fixed-point cache-inhibited load/store
instructions. These are hypervisor-level only, so don't get too excited ;)
Fixes PR21650.
llvm-svn: 222976
2014-11-30 10:15:56 +00:00
c7e220f6e0
[mips][microMIPS] Implement NOP aliases
...
This patch implements microMIPS 16-bit (MOVE16 $0, $0) and
32-bit (SLL $0, $0, 0) NOP aliases.
http://reviews.llvm.org/D6440
llvm-svn: 222953
2014-11-29 13:29:24 +00:00
db6c5e7afa
Fix wrong encoding of MRSBanked.
...
Patch by Matthew Wahab.
Change-Id: Ia2a001ca2760028ea360fe77b56f203a219eefbc
llvm-svn: 222920
2014-11-28 15:01:06 +00:00
b4484d62ad
[mips] Add synci instruction.
...
Patch by Amaury Pouly
Reviewers: dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D6421
llvm-svn: 222899
2014-11-27 17:28:10 +00:00
aa2b9278fe
[mips][microMIPS] Implement disassembler support for 16-bit instructions LI16, ADDIUR1SP, ADDIUR2 and ADDIUS5
...
Differential Revision: http://reviews.llvm.org/D6419
llvm-svn: 222887
2014-11-27 14:41:44 +00:00
315e7eca1b
[mips][microMIPS] Implement disassembler support for 16-bit instructions LBU16, LHU16, LW16, SB16, SH16 and SW16
...
Differential Revision: http://reviews.llvm.org/D6405
llvm-svn: 222847
2014-11-26 18:56:38 +00:00
5901676581
[PowerPC] Add the 'attn' instruction
...
The attn instruction is not part of the Power ISA, but is documented in the A2
user manual, and is accepted by the GNU assembler for the A2 and the POWER4+.
Reported as part of PR21650.
llvm-svn: 222712
2014-11-25 00:30:11 +00:00
ea22c4cfbb
[mips][microMIPS] Implement disassembler support for 16-bit instructions
...
With the help of new method readInstruction16() two bytes are read and
decodeInstruction() is called with DecoderTableMicroMips16, if this fails
four bytes are read and decodeInstruction() is called with
DecoderTableMicroMips32.
Differential Revision: http://reviews.llvm.org/D6149
llvm-svn: 222648
2014-11-24 13:29:59 +00:00
a4c4b5fc01
[mips][micromips] Implement SWM32 and LWM32 instructions
...
Differential Revision: http://reviews.llvm.org/D5519
llvm-svn: 222367
2014-11-19 16:44:02 +00:00
55bb542856
[mips][microMIPS] Add disassembler tests for new microMIPS 32-bit
...
instructions: LWXS, BGEZALS, BLTZALS, BEQZC, BNEZC, JALS and JALRS.
http://reviews.llvm.org/D5413
llvm-svn: 222349
2014-11-19 11:49:57 +00:00
c8d452eed8
Fix bashism in tests added by r221341
...
llvm-svn: 221342
2014-11-05 12:40:21 +00:00
9e89d8cc5c
[ARM] Honor FeatureD16 in the assembler and disassembler
...
Some ARM FPUs only have 16 double-precision registers, rather than the
normal 32. LLVM represents this with the D16 target feature. This is
currently used by CodeGen to avoid using high registers when they are
not available, but the assembler and disassembler do not.
I fix this in the assmebler and disassembler rather than the
InstrInfo.td files, as the latter would require a large number of
changes everywhere one of the floating-point instructions is referenced
in the backend. This solution is similar to the one used for
co-processor numbers and MSR masks.
llvm-svn: 221341
2014-11-05 12:06:39 +00:00
5241881bbc
[Hexagon] Reverting 220584 to address ASAN errors.
...
llvm-svn: 221210
2014-11-04 00:14:36 +00:00
1d8cc909cc
Remove the cortex-a9-mp CPU.
...
This CPU definition is redundant. The Cortex-A9 is defined as
supporting multiprocessing extensions. Remove its definition and
update appropriate tests.
LLVM defines both a cortex-a9 CPU and a cortex-a9-mp CPU. The only
difference between the two CPU definitions in ARM.td is that
cortex-a9-mp contains the feature FeatureMP for multiprocessing
extensions.
This is redundant since the Cortex-A9 is defined as having
multiprocessing extensions in the TRMs. armcc also defines the
Cortex-A9 as having multiprocessing extensions by default.
Change-Id: Ifcadaa6c322be0a33d9d2a39cfdd7da1d75981a7
llvm-svn: 221166
2014-11-03 17:38:00 +00:00
4b01b7306c
AVX-512: Fixed encoding of VPBROADCASTM and added SKX forms of this instruction
...
llvm-svn: 220638
2014-10-26 09:52:24 +00:00
838307b31f
[Hexagon] Resubmission of 220427
...
Modified library structure to deal with circular dependency between HexagonInstPrinter and HexagonMCInst.
Adding encoding bits for add opcode.
Adding llvm-mc tests.
Removing unit tests.
http://reviews.llvm.org/D5624
llvm-svn: 220584
2014-10-24 19:00:32 +00:00
504bbf91cd
Revert r220427, "[Hexagon] Adding encoding bits for add opcode."
...
It brought cyclic dependecy between HexagonAsmPrinter and HexagonDesc.
llvm-svn: 220478
2014-10-23 11:31:22 +00:00
39a85abddf
[Thumb2] Improve disassembly of memory hints
...
Currently, the ARM disassembler will disassemble the Thumb2 memory hint
instructions (PLD, PLDW and PLI), even for targets which do not have
these instructions. This patch adds the required checks to the
disassmebler.
llvm-svn: 220472
2014-10-23 08:52:58 +00:00
73a51a1a68
[Hexagon] Adding encoding bits for add opcode.
...
Adding llvm-mc tests.
Removing unit tests.
http://reviews.llvm.org/D5624
llvm-svn: 220427
2014-10-22 20:58:35 +00:00
0676b902ad
[X86] Fix a bug where the disassembler was ignoring the VEX.W bit in 32-bit mode for certain instructions it shouldn't.
...
Unfortunately, this isn't easy to fix since there's no simple way to figure out from the disassembler tables whether the W-bit is being used to select a 64-bit GPR or if its a required part of the opcode. The fix implemented here just looks for "64" in the instruction name and ignores the W-bit in 32-bit mode if its present.
Fixes PR21169.
llvm-svn: 219194
2014-10-07 07:29:50 +00:00
92db6b78f7
[mips] Fix disassembly of [ls][wd]c[23], cache, and pref
...
Fixes PR21015, and PR20993.
Patch by Jun Koi
llvm-svn: 218745
2014-10-01 08:26:55 +00:00
92c816c68f
Thumb2 M-class MSR instruction support changes
...
This patch implements a few changes related to the Thumb2 M-class MSR instruction:
* better handling of unpredictable encodings,
* recognition of the _g and _nzcvqg variants by the asm parser only if the DSP
extension is available, preferred output of MSR APSR moves with the _<bits>
suffix for v7-M.
Patch by Petr Pavlu.
llvm-svn: 216874
2014-09-01 11:25:07 +00:00
584a70c820
[PowerPC] Add support for dcbtst and icbt (prefetch)
...
Adds code generation support for dcbtst (data cache prefetch for write) and
icbt (instruction cache prefetch for read - Book E cores only).
We still end up with a 'cannot select' error for the non-supported prefetch
intrinsic forms. This will be fixed in a later commit.
Fixes PR20692.
llvm-svn: 216339
2014-08-23 23:21:04 +00:00
ee843ef0fa
ARM: implement MRS/MSR (banked reg) system instructions.
...
These are system-only instructions for CPUs with virtualization
extensions, allowing a hypervisor easy access to all of the various
different AArch32 registers.
rdar://problem/17861345
llvm-svn: 215700
2014-08-15 10:47:12 +00:00
5f6b6cec70
Update disassembler test to check the full dccci/iccci form.
...
llvm-svn: 215283
2014-08-09 14:01:10 +00:00
a3d4dc9eb4
Add RFID instruction.
...
llvm-svn: 215105
2014-08-07 12:39:59 +00:00
412471271e
Add dci/ici instructions for PPC 476 and friends.
...
llvm-svn: 214864
2014-08-05 14:40:32 +00:00
9dedceb71d
Add lswi / stswi for assembler use with a warning to not add patterns
...
for them.
llvm-svn: 214862
2014-08-05 13:34:01 +00:00
5995e0021d
Add PPC 603's tlbld and tlbli instructions.
...
llvm-svn: 214825
2014-08-04 23:49:45 +00:00
6c3e38522a
tlbre / tlbwe / tlbsx / tlbsx. variants for the PPC 4xx CPUs.
...
llvm-svn: 214784
2014-08-04 21:28:22 +00:00
0b2ebcb49d
Add features for PPC 4xx and e500/e500mc instructions.
...
Move the test cases for them into separate files.
llvm-svn: 214724
2014-08-04 15:47:38 +00:00
c03105ba8e
tlbia support
...
llvm-svn: 214640
2014-08-02 20:16:29 +00:00
e8a167ce8f
mfdcr / mtdcr support
...
llvm-svn: 214639
2014-08-02 20:00:26 +00:00
99ab590ac9
Don't use additional arguments for dss and friends to satisfy DSS_Form,
...
when let can do the same thing. Keep the 64bit variants as codegen-only.
While they have a different register class, the encoding is the same for
32bit and 64bit mode. Having both present would otherwise confuse the
disassembler.
llvm-svn: 214636
2014-08-02 15:09:41 +00:00
Jozef Kolek