1c5b7d12df
Incorrect SETCC CondCode used for FP comparisons.
...
llvm-svn: 28433
2006-05-23 06:40:47 +00:00
7949c2e8b2
Fix the result of the call to use a correct vbitconvert. There is no need to
...
use getPackedTypeBreakdown at all here.
llvm-svn: 28365
2006-05-17 20:49:36 +00:00
938155ca57
Correct a previous patch which broke CodeGen/PowerPC/vec_call.ll
...
llvm-svn: 28364
2006-05-17 20:43:21 +00:00
751cd7653d
Fixed a LowerCallTo and LowerArguments bug. They were introducing illegal
...
VBIT_VECTOR nodes. There were some confusion about the semantics of
getPackedTypeBreakdown(). e.g. for <4 x f32> it returns 1 and v4f32, not 4,
and f32.
llvm-svn: 28352
2006-05-17 18:16:39 +00:00
b77ba73a29
Add support for calls that pass and return legal vectors.
...
llvm-svn: 28340
2006-05-16 23:39:44 +00:00
aaa23d953f
Add a new ISD::CALL node, make the default impl of TargetLowering::LowerCallTo
...
produce it.
llvm-svn: 28338
2006-05-16 22:53:20 +00:00
3d82699605
Add a chain to FORMAL_ARGUMENTS. This is a minimal port of the X86 backend,
...
it doesn't currently use/maintain the chain properly. Also, make the
X86ISelLowering.cpp file 80-col clean.
llvm-svn: 28320
2006-05-16 06:45:34 +00:00
957cb6733a
Move function-live-in-handling code from the sdisel code to the scheduler.
...
This code should be emitted after legalize, so it can't be in sdisel.
Note that the EmitFunctionEntryCode hook should be updated to operate on the
DAG. The X86 backend is the only one currently using this hook.
llvm-svn: 28315
2006-05-16 06:10:58 +00:00
d1915cfa6f
Revert an un-intended change
...
llvm-svn: 28278
2006-05-13 05:53:47 +00:00
53cdb2f2b0
Remove dead vars
...
llvm-svn: 28255
2006-05-12 18:06:45 +00:00
d38c22bdd3
Refactor scheduler code. Move register-reduction list scheduler to a
...
separate file. Added an initial implementation of top-down register pressure
reduction list scheduler.
llvm-svn: 28226
2006-05-11 23:55:42 +00:00
d7a19102d1
Make emission of jump tables a bit less conservative; they are now required
...
to be only 31.25% dense, rather than 75% dense.
llvm-svn: 28165
2006-05-08 16:51:36 +00:00
21cd99024a
When inserting casts, be careful of where we put them. We cannot insert
...
a cast immediately before a PHI node.
This fixes Regression/CodeGen/Generic/2006-05-06-GEP-Cast-Sink-Crash.ll
llvm-svn: 28143
2006-05-06 09:10:37 +00:00
3e3f2c63c3
More aggressively sink GEP offsets into loops. For example, before we
...
generated:
movl 8(%esp), %eax
movl %eax, %edx
addl $4316, %edx
cmpb $1, %cl
ja LBB1_2 #cond_false
LBB1_1: #cond_true
movl L_QuantizationTables720$non_lazy_ptr, %ecx
movl %ecx, (%edx)
movl L_QNOtoQuantTableShift720$non_lazy_ptr, %edx
movl %edx, 4460(%eax)
ret
...
Now we generate:
movl 8(%esp), %eax
cmpb $1, %cl
ja LBB1_2 #cond_false
LBB1_1: #cond_true
movl L_QuantizationTables720$non_lazy_ptr, %ecx
movl %ecx, 4316(%eax)
movl L_QNOtoQuantTableShift720$non_lazy_ptr, %ecx
movl %ecx, 4460(%eax)
ret
... which uses one fewer register.
llvm-svn: 28129
2006-05-05 21:17:49 +00:00
7a3ecf7993
Sink noop copies into the basic block that uses them. This reduces the number
...
of cross-block live ranges, and allows the bb-at-a-time selector to always
coallesce these away, at isel time.
This reduces the load on the coallescer and register allocator. For example
on a codec on X86, we went from:
1643 asm-printer - Number of machine instrs printed
419 liveintervals - Number of loads/stores folded into instructions
1144 liveintervals - Number of identity moves eliminated after coalescing
1022 liveintervals - Number of interval joins performed
282 liveintervals - Number of intervals after coalescing
1304 liveintervals - Number of original intervals
86 regalloc - Number of times we had to backtrack
1.90232 regalloc - Ratio of intervals processed over total intervals
40 spiller - Number of values reused
182 spiller - Number of loads added
121 spiller - Number of stores added
132 spiller - Number of register spills
6 twoaddressinstruction - Number of instructions commuted to coalesce
360 twoaddressinstruction - Number of two-address instructions
to:
1636 asm-printer - Number of machine instrs printed
403 liveintervals - Number of loads/stores folded into instructions
1155 liveintervals - Number of identity moves eliminated after coalescing
1033 liveintervals - Number of interval joins performed
279 liveintervals - Number of intervals after coalescing
1312 liveintervals - Number of original intervals
76 regalloc - Number of times we had to backtrack
1.88998 regalloc - Ratio of intervals processed over total intervals
1 spiller - Number of copies elided
41 spiller - Number of values reused
191 spiller - Number of loads added
114 spiller - Number of stores added
128 spiller - Number of register spills
4 twoaddressinstruction - Number of instructions commuted to coalesce
356 twoaddressinstruction - Number of two-address instructions
On this testcase, this change provides a modest reduction in spill code,
regalloc iterations, and total instructions emitted. It increases the number
of register coallesces.
llvm-svn: 28115
2006-05-05 01:04:50 +00:00
df4883971e
Finish up the initial jump table implementation by allowing jump tables to
...
not be 100% dense. Increase the minimum threshold for the number of cases
in a switch statement from 4 to 6 in order to create a jump table.
llvm-svn: 28079
2006-05-03 03:48:02 +00:00
20a631fde7
Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference.
...
This fixes PR 759.
llvm-svn: 28074
2006-05-03 01:29:57 +00:00
c5e8ce8b8c
Remove the temporary option: -no-isel-fold-inflight
...
llvm-svn: 28012
2006-04-28 18:54:11 +00:00
d43c5c6046
TargetLowering::LowerArguments should return a VBIT_CONVERT of
...
FORMAL_ARGUMENTS SDOperand in the return result vector.
llvm-svn: 28009
2006-04-28 05:25:15 +00:00
51ab4498e7
Added a temporary option -no-isel-fold-inflight to control whether a "inflight"
...
node can be folded.
llvm-svn: 28003
2006-04-28 02:09:19 +00:00
3784f3c57c
Insert a VBIT_CONVERT between a FORMAL_ARGUMENT node and its vector uses
...
(VAND, VADD, etc.). Legalizer will assert otherwise.
llvm-svn: 27991
2006-04-27 08:29:42 +00:00
9618df1190
Don't forget return void.
...
llvm-svn: 27974
2006-04-25 23:03:35 +00:00
866b4b4d45
Fix the updating of the machine CFG when a PHI node was in a successor of
...
the jump table's range check block. This re-enables 100% dense jump tables
by default on PPC & x86
llvm-svn: 27952
2006-04-23 06:26:20 +00:00
ecb1dafd3d
Turn of jump tables for a bit, there are still some issues to work out with
...
updating the machine CFG.
llvm-svn: 27949
2006-04-22 23:51:56 +00:00
4ca2ea5b43
JumpTable support! What this represents is working asm and jit support for
...
x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.
llvm-svn: 27947
2006-04-22 18:53:45 +00:00
b21d3bfd1f
The BFS scheduler is apparently nondeterminstic (causes many llvmgcc bootstrap
...
miscompares). Switch RISC targets to use the list-td scheduler, which isn't.
llvm-svn: 27933
2006-04-21 17:16:16 +00:00
d3b504ae10
Implement support for the formal_arguments node. To get this, targets shouldcustom legalize it and remove their XXXTargetLowering::LowerArguments overload
...
llvm-svn: 27604
2006-04-12 16:20:43 +00:00
02274a5265
Add code generator support for VSELECT
...
llvm-svn: 27542
2006-04-08 22:22:57 +00:00
098c01e94e
Codegen shufflevector as VVECTOR_SHUFFLE
...
llvm-svn: 27529
2006-04-08 04:15:24 +00:00
aa3185f12e
Stub out shufflevector
...
llvm-svn: 27514
2006-04-08 01:19:25 +00:00
4a2413a590
Make a vector live across blocks have the correct Vec type. This fixes
...
CodeGen/X86/2006-04-04-CrossBlockCrash.ll
llvm-svn: 27436
2006-04-05 06:54:42 +00:00
a9c59156be
Intrinsics that just load from memory can be treated like loads: they don't
...
have to serialize against each other. This allows us to schedule lvx's
across each other, for example.
llvm-svn: 27346
2006-04-02 03:41:14 +00:00
ef598059f2
Add a new -view-legalize-dags command line option
...
llvm-svn: 27342
2006-04-02 03:07:27 +00:00
bec582f4cd
Prefer larger register classes over smaller ones when a register occurs in
...
multiple register classes. This fixes PowerPC/2006-04-01-FloatDoubleExtend.ll
llvm-svn: 27334
2006-04-02 00:24:45 +00:00
ba38035e21
Make sure to pass enough values to phi nodes when we are dealing with
...
decimated vectors. This fixes UnitTests/Vector/sumarray-dbl.c
llvm-svn: 27280
2006-03-31 02:12:18 +00:00
5fe1f54c17
Significantly improve handling of vectors that are live across basic blocks,
...
handling cases where the vector elements need promotion, expansion, and when
the vector type itself needs to be decimated.
llvm-svn: 27278
2006-03-31 02:06:56 +00:00
67271869a8
Bug fixes: handle constantexpr insert/extract element operations
...
Handle constantpacked vectors with constantexpr elements.
This fixes CodeGen/Generic/vector-constantexpr.ll
llvm-svn: 27241
2006-03-29 00:11:43 +00:00
67a636c587
More bulletproofing of llvm.dbg.declare.
...
llvm-svn: 27224
2006-03-28 13:45:20 +00:00
e55d171ccd
Tblgen doesn't like multiple SDNode<> definitions that map to the sameenum value. Split them into separate enums.
...
llvm-svn: 27201
2006-03-28 00:40:33 +00:00
d387cc5cde
Reactivate llvm.dbg.declare.
...
llvm-svn: 27192
2006-03-27 23:31:10 +00:00
5bb1d90afd
Disable dbg_declare, it currently breaks the CFE build
...
llvm-svn: 27182
2006-03-27 21:36:03 +00:00
ed728c1291
SelectionDAGISel can now natively handle Switch instructions, in the same
...
manner that the LowerSwitch LLVM to LLVM pass does: emitting a binary
search tree of basic blocks. The new approach has several advantages:
it is faster, it generates significantly smaller code in many cases, and
it paves the way for implementing dense switch tables as a jump table by
handling switches directly in the instruction selector.
This functionality is currently only enabled on x86, but should be safe for
every target. In anticipation of making it the default, the cfg is now
properly updated in the x86, ppc, and sparc select lowering code.
llvm-svn: 27156
2006-03-27 01:32:24 +00:00
7092888bcc
Bullet proof against undefined args produced by upgrading ols-style debug info.
...
llvm-svn: 27155
2006-03-26 22:46:27 +00:00
313229c74b
fix inverted conditional
...
llvm-svn: 27089
2006-03-24 22:49:42 +00:00
53f1ecc560
Rename for truth in advertising.
...
llvm-svn: 27063
2006-03-24 09:50:27 +00:00
d96b09a7b9
Lower target intrinsics into an INTRINSIC node
...
llvm-svn: 27035
2006-03-24 02:22:33 +00:00
a8bdac875d
Handle new forms of llvm.dbg intrinsics.
...
llvm-svn: 26988
2006-03-23 18:06:46 +00:00
b893d04a67
Fix a typo
...
llvm-svn: 26965
2006-03-22 22:20:49 +00:00
2f4119a608
Implement simple support for vector casting. This can currently only handle
...
casts between legal vector types.
llvm-svn: 26961
2006-03-22 20:09:35 +00:00
7c0cd8cafc
add some trivial support for extractelement.
...
llvm-svn: 26928
2006-03-21 20:44:12 +00:00
672a42d731
Add a hacky workaround for crashes due to vectors live across blocks.
...
Note that this code won't work for vectors that aren't legal on the
target. Improvements coming.
llvm-svn: 26925
2006-03-21 19:20:37 +00:00
29b2301460
implement basic support for INSERT_VECTOR_ELT.
...
llvm-svn: 26849
2006-03-19 01:17:20 +00:00
f4e1a53647
Rename ConstantVec -> BUILD_VECTOR and VConstant -> VBUILD_VECTOR. Allow*BUILD_VECTOR to take variable inputs.
...
llvm-svn: 26847
2006-03-19 00:52:58 +00:00
c16b05e67d
implement vector.ll:test_undef
...
llvm-svn: 26845
2006-03-19 00:20:20 +00:00
32206f54c6
Change the structure of lowering vector stuff. Note: This breaks some
...
things.
llvm-svn: 26840
2006-03-18 01:44:44 +00:00
bb01d4f272
Remove BRTWOWAY*
...
Make the PPC backend not dependent on BRTWOWAY_CC and make the branch
selector smarter about the code it generates, fixing a case in the
readme.
llvm-svn: 26814
2006-03-17 01:40:33 +00:00
7ececaad83
Fix a problem fully scalarizing values.
...
llvm-svn: 26811
2006-03-16 23:05:19 +00:00
8471b15706
Add support for CopyFromReg from vector values. Note: this doesn't support
...
illegal vector types yet!
llvm-svn: 26799
2006-03-16 19:57:50 +00:00
49409cb925
Teach CreateRegForValue how to handle vector types.
...
llvm-svn: 26798
2006-03-16 19:51:18 +00:00
4024c00ce7
add support for vector->vector casts
...
llvm-svn: 26788
2006-03-15 22:19:46 +00:00
acb6e34277
Handle the removal of the debug chain.
...
llvm-svn: 26729
2006-03-13 13:07:37 +00:00
38280c0020
Added a parameter to control whether Constant::getStringValue() would chop
...
off the result string at the first null terminator.
llvm-svn: 26704
2006-03-10 23:52:03 +00:00
d3ef6c290a
scrape out bits of llvm-db
...
llvm-svn: 26701
2006-03-10 22:48:19 +00:00
5255d04357
Simplify the interface to the schedulers, to not pass the selected heuristicin.
...
llvm-svn: 26692
2006-03-10 07:49:12 +00:00
213209a248
remove dbg_declare, it's not used yet.
...
llvm-svn: 26659
2006-03-09 20:02:42 +00:00
2698f0de7a
Get rid of the multiple copies of getStringValue. Now a Constant:: method.
...
llvm-svn: 26616
2006-03-08 18:11:07 +00:00
543832d39d
Change the interface for getting a target HazardRecognizer to be more clean.
...
llvm-svn: 26608
2006-03-08 04:25:59 +00:00
47639dbb93
Hoist the HazardRecognizer out of the ScheduleDAGList.cpp file to where
...
targets can implement them. Make the top-down scheduler non-g5-specific.
Remove the old testing hazard recognizer.
llvm-svn: 26569
2006-03-06 00:22:00 +00:00
98ecb8ec61
Split the list scheduler into top-down and bottom-up pieces. The priority
...
function of the top-down scheduler are completely bogus currently, and
having (future) PPC specific in this file is also wrong, but this is a
small incremental step.
llvm-svn: 26552
2006-03-05 21:10:33 +00:00
5c1ba2ac08
Codegen copysign[f] into a FCOPYSIGN node
...
llvm-svn: 26542
2006-03-05 05:09:38 +00:00
3bf916ddd9
Add more vector NodeTypes: VSDIV, VUDIV, VAND, VOR, and VXOR.
...
llvm-svn: 26504
2006-03-03 07:01:07 +00:00
ad3c974a77
remove the read/write port/io intrinsics.
...
llvm-svn: 26479
2006-03-03 00:19:58 +00:00
093c159efb
Split memcpy/memset/memmove intrinsics into i32/i64 versions, resolving
...
PR709, and paving the way for future progress.
llvm-svn: 26476
2006-03-03 00:00:25 +00:00
b97aab4371
Vector ops lowering.
...
llvm-svn: 26436
2006-03-01 01:09:54 +00:00
9fed5b6122
Add support for output memory constraints.
...
llvm-svn: 26410
2006-02-27 23:45:39 +00:00
83c22e0d75
Get VC++ building again.
...
llvm-svn: 26351
2006-02-24 02:52:40 +00:00
dcf785bf46
Implement (most of) selection of inline asm memory operands.
...
llvm-svn: 26350
2006-02-24 02:13:54 +00:00
7ef7a64ebb
Lower C_Memory operands.
...
llvm-svn: 26346
2006-02-24 01:11:24 +00:00
e7c0ffb3a0
Fix an endianness problem on big-endian targets with expanded operands
...
to inline asms. Mark some methods const.
llvm-svn: 26334
2006-02-23 20:06:57 +00:00
571d9647c6
Record all of the expanded registers in the DAG and machine instr, fixing
...
several bugs in inline asm expanded operands.
llvm-svn: 26332
2006-02-23 19:21:04 +00:00
b1124f3c76
This fixes a couple of problems with expansion
...
llvm-svn: 26318
2006-02-22 23:09:03 +00:00
6f87d18be9
Change a whole bunch of code to be built around RegsForValue instead of
...
a single register number. This fully implements promotion for inline asms,
expand is close but not quite right yet.
llvm-svn: 26316
2006-02-22 22:37:12 +00:00
7ad77dfc2a
split register class handling from explicit physreg handling.
...
llvm-svn: 26308
2006-02-22 00:56:39 +00:00
5c79f98f15
Adjust to changes in getRegForInlineAsmConstraint prototype
...
llvm-svn: 26306
2006-02-21 23:12:12 +00:00
c3dcf5a4d7
Dumb bug. Code sees a memcpy from X+c so it increments src offset. But it
...
turns out not to point to a constant string but it forgot change the offset
back.
llvm-svn: 26242
2006-02-16 23:11:42 +00:00
42c01c8d39
If the false case is the current basic block, then this is a self loop.
...
We do not want to emit "Loop: ... brcond Out; br Loop", as it adds an extra
instruction in the loop. Instead, invert the condition and emit
"Loop: ... br!cond Loop; br Out.
Generalize the fix by moving it from PPCDAGToDAGISel to SelectionDAGLowering.
llvm-svn: 26231
2006-02-16 08:27:56 +00:00
93e4865d4b
Remove an unused function parameter.
...
llvm-svn: 26221
2006-02-15 22:12:35 +00:00
6781b6e62e
Turn a memcpy from string constant into a series of stores of constant values.
...
llvm-svn: 26219
2006-02-15 21:59:04 +00:00
e2038bdeee
Lower memcpy with small constant size operand into a series of load / store
...
ops.
llvm-svn: 26195
2006-02-15 01:54:51 +00:00
0451499b3c
Doh again!
...
llvm-svn: 26188
2006-02-14 23:05:54 +00:00
db2a7a736a
Keep to < 80 cols
...
llvm-svn: 26177
2006-02-14 20:12:38 +00:00
038521ef76
Missed a break so memcpy cases fell through to memset. Doh.
...
llvm-svn: 26176
2006-02-14 19:45:56 +00:00
d502610604
Fixed a build breakage.
...
llvm-svn: 26175
2006-02-14 09:11:59 +00:00
4b40a42653
Rename maxStoresPerMemSet to maxStoresPerMemset, etc.
...
llvm-svn: 26174
2006-02-14 08:38:30 +00:00
81fcea8aa2
Expand memset dst, c, size to a series of stores if size falls below the
...
target specific theshold, e.g. 16 for x86.
llvm-svn: 26171
2006-02-14 08:22:34 +00:00
1784a9d267
now that libcalls don't suck, we can remove this hack
...
llvm-svn: 26164
2006-02-14 05:39:35 +00:00
390c63e9d9
Rename to better reflect usage (current and planned.)
...
llvm-svn: 26145
2006-02-13 12:50:39 +00:00
5995d0160c
Reorg for integration with gcc4. Old style debug info will not be passed though
...
to SelIDAG.
llvm-svn: 26115
2006-02-11 01:01:30 +00:00
f9adce90bf
Get rid of some memory leaks identified by Valgrind
...
llvm-svn: 25960
2006-02-04 06:49:00 +00:00
3b48431333
Add initial support for immediates. This allows us to compile this:
...
int %rlwnm(int %A, int %B) {
%C = call int asm "rlwnm $0, $1, $2, $3, $4", "=r,r,r,n,n"(int %A, int %B, int 4, int 17)
ret int %C
}
into:
_rlwnm:
or r2, r3, r3
or r3, r4, r4
rlwnm r2, r2, r3, 4, 17 ;; note the immediates :)
or r3, r2, r2
blr
llvm-svn: 25955
2006-02-04 02:26:14 +00:00
65ad53feb3
Initial early support for non-register operands, like immediates
...
llvm-svn: 25952
2006-02-04 02:16:44 +00:00
f68fd20286
remove some #ifdef'd out code, which should properly be in the dag combiner anyway.
...
llvm-svn: 25941
2006-02-03 20:13:59 +00:00
7f5880b1c7
Implement matching constraints. We can now say things like this:
...
%C = call int asm "xyz $0, $1, $2, $3", "=r,r,r,0"(int %A, int %B, int 4)
and get:
xyz r2, r3, r4, r2
note that the r2's are pinned together. Yaay for 2-address instructions.
2342 ----------------------------------------------------------------------
llvm-svn: 25893
2006-02-02 00:25:23 +00:00
1558fc64f9
Implement simple register assignment for inline asms. This allows us to compile:
...
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
into:
(0x8906130, LLVM BB @0x8902220):
%r2 = OR4 %r3, %r3
%r3 = OR4 %r4, %r4
INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
%r3 = OR4 %r2, %r2
BLR
which asmprints as:
_test:
or r2, r3, r3
or r3, r4, r4
xyz $0, $1, $2 ;; need to print the operands now :)
or r3, r2, r2
blr
llvm-svn: 25878
2006-02-01 18:59:47 +00:00
3a5ed55187
adjust to changes in InlineAsm interface. Fix a few minor bugs.
...
llvm-svn: 25865
2006-02-01 01:28:23 +00:00
2e56e89452
Handle physreg input/outputs. We now compile this:
...
int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = alloca int
%A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
%Bv = load int* %B
%Cv = load int* %C
%Dv = load int* %D
%x = add int %A, %Bv
%y = add int %x, %Cv
%z = add int %y, %Dv
ret int %z
}
to this:
_test_cpuid:
sub %ESP, 16
mov DWORD PTR [%ESP], %EBX
mov %EAX, DWORD PTR [%ESP + 20]
cpuid
mov DWORD PTR [%ESP + 8], %ECX
mov DWORD PTR [%ESP + 12], %EBX
mov DWORD PTR [%ESP + 4], %EDX
mov %ECX, DWORD PTR [%ESP + 12]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 8]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 4]
add %EAX, %ECX
mov %EBX, DWORD PTR [%ESP]
add %ESP, 16
ret
... note the proper register allocation. :)
it is unclear to me why the loads aren't folded into the adds.
llvm-svn: 25827
2006-01-31 02:03:41 +00:00
98ed05c81d
remove method I just added
...
llvm-svn: 25728
2006-01-28 03:43:09 +00:00
43b867dd3b
add a new callback
...
llvm-svn: 25727
2006-01-28 03:37:03 +00:00
595ec734fc
Implement Promote for VAARG, and allow it to be custom promoted for people
...
who don't want the default behavior (Alpha).
llvm-svn: 25726
2006-01-28 03:14:31 +00:00
8c47c3a3b1
Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for
...
the same functionality. This addresses another piece of bug 680. Next,
on to fixing Alpha VAARG, which I broke last time.
llvm-svn: 25696
2006-01-27 21:09:22 +00:00
476e67be14
initial selectiondag support for new INLINEASM node. Note that inline asms
...
with outputs or inputs are not supported yet. :)
llvm-svn: 25664
2006-01-26 22:24:51 +00:00
e74795cd70
First part of bug 680:
...
Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same
way as everything else.
llvm-svn: 25606
2006-01-25 18:21:52 +00:00
a6eff8a432
If scheduler choice is the default (-sched=default), use target scheduling
...
preference to determine which scheduler to use. SchedulingForLatency ==
Breadth first; SchedulingForRegPressure == bottom up register reduction list
scheduler.
llvm-svn: 25599
2006-01-25 09:12:57 +00:00
b8566fa10a
Typo.
...
llvm-svn: 25545
2006-01-23 13:34:04 +00:00
31272347d4
Skeleton of the list schedule.
...
llvm-svn: 25544
2006-01-23 08:26:10 +00:00
c1e1d9724d
Factor out more instruction scheduler code to the base class.
...
llvm-svn: 25532
2006-01-23 07:01:07 +00:00
deda32a786
Fix bugs lowering stackrestore, fixing 2004-08-12-InlinerAndAllocas.c on
...
PPC.
llvm-svn: 25522
2006-01-23 05:22:07 +00:00
e23928c67f
Fix a bug in a recent refactor that caused a bunch of programs to miscompile
...
or the compiler to crash.
llvm-svn: 25503
2006-01-21 19:12:11 +00:00
739a6a456e
Do some code refactoring on Jim's scheduler in preparation of the new list
...
scheduler.
llvm-svn: 25493
2006-01-21 02:32:06 +00:00
222ceabbee
If the target doesn't support f32 natively, insert the FP_EXTEND in target-indep
...
code, so that the LowerReturn code doesn't have to handle it.
llvm-svn: 25482
2006-01-20 18:38:32 +00:00
e2ee190821
Temporary work around for a libcall insertion bug: If a target doesn't
...
support FSIN/FCOS nodes, do not lower sin/cos to them.
llvm-svn: 25425
2006-01-18 21:50:14 +00:00
03e95af9f7
Support for the insertelement operation.
...
llvm-svn: 25405
2006-01-17 20:06:42 +00:00
b4f9a6f110
For PR411:
...
This patch is an incremental step towards supporting a flat symbol table.
It de-overloads the intrinsic functions by providing type-specific intrinsics
and arranging for automatically upgrading from the old overloaded name to
the new non-overloaded name. Specifically:
llvm.isunordered -> llvm.isunordered.f32, llvm.isunordered.f64
llvm.sqrt -> llvm.sqrt.f32, llvm.sqrt.f64
llvm.ctpop -> llvm.ctpop.i8, llvm.ctpop.i16, llvm.ctpop.i32, llvm.ctpop.i64
llvm.ctlz -> llvm.ctlz.i8, llvm.ctlz.i16, llvm.ctlz.i32, llvm.ctlz.i64
llvm.cttz -> llvm.cttz.i8, llvm.cttz.i16, llvm.cttz.i32, llvm.cttz.i64
New code should not use the overloaded intrinsic names. Warnings will be
emitted if they are used.
llvm-svn: 25366
2006-01-16 21:12:35 +00:00
542c3c17a9
Remove some duplicated code
...
llvm-svn: 25313
2006-01-14 03:18:27 +00:00
2fba8a3aaa
bswap implementation
...
llvm-svn: 25312
2006-01-14 03:14:10 +00:00
b32664583b
Compile llvm.stacksave/restore into STACKSAVE/STACKRESTORE nodes, and allow
...
targets to custom expand them as they desire.
llvm-svn: 25273
2006-01-13 02:50:02 +00:00
6c9c250dcd
Add "support" for stacksave/stackrestore to the dag isel
...
llvm-svn: 25268
2006-01-13 02:24:42 +00:00
2c966e7617
Added selection DAG support for the extractelement operation.
...
llvm-svn: 25179
2006-01-10 19:04:57 +00:00
219d559824
Applied some recommend changes from sabre. The dominate one beginning "let the
...
pass manager do it's thing." Fixes crash when compiling -g files and suppresses
dwarf statements if no debug info is present.
llvm-svn: 25100
2006-01-04 22:28:25 +00:00
44c07ed61a
enable the gep isel opt
...
llvm-svn: 24910
2005-12-21 19:36:36 +00:00
803a575616
Lower ConstantAggregateZero into zeros
...
llvm-svn: 24890
2005-12-21 02:43:26 +00:00
7c462768ed
Added source file/line correspondence for dwarf (PowerPC only at this point.)
...
llvm-svn: 24748
2005-12-16 22:45:29 +00:00
5d4e61dd87
Don't lump the filename and working dir together
...
llvm-svn: 24697
2005-12-13 17:40:33 +00:00
9e8b633ec1
Accept and ignore prefetches for now
...
llvm-svn: 24678
2005-12-12 22:51:16 +00:00
f1a54c0d14
Minor tweak to get isel opt
...
llvm-svn: 24663
2005-12-11 09:05:13 +00:00
be73d6eece
improve code insertion in two ways:
...
1. Only forward subst offsets into loads and stores, not into arbitrary
things, where it will likely become a load.
2. If the source is a cast from pointer, forward subst the cast as well,
allowing us to fold the cast away (improving cases when the cast is
from an alloca or global).
This hasn't been fully tested, but does appear to further reduce register
pressure and improve code. Lets let the testers grind on it a bit. :)
llvm-svn: 24640
2005-12-08 08:00:12 +00:00
ae89d862f5
Fix a crash where ConstantVec nodes were being generated with the wrong
...
type when the target did not support them. Also teach Legalize how to
expand ConstantVecs.
This allows us to generate
_test:
lwz r2, 12(r3)
lwz r4, 8(r3)
lwz r5, 4(r3)
lwz r6, 0(r3)
addi r2, r2, 4
addi r4, r4, 3
addi r5, r5, 2
addi r6, r6, 1
stw r2, 12(r3)
stw r4, 8(r3)
stw r5, 4(r3)
stw r6, 0(r3)
blr
For:
void %test(%v4i *%P) {
%T = load %v4i* %P
%S = add %v4i %T, <int 1, int 2, int 3, int 4>
store %v4i %S, %v4i * %P
ret void
}
On PowerPC.
llvm-svn: 24633
2005-12-07 19:48:11 +00:00
41b1cdc771
Teach the SelectionDAG ISel how to turn ConstantPacked values into
...
constant nodes with vector types. Also teach the asm printer how to print
ConstantPacked constant pool entries. This allows us to generate altivec
code such as the following, which adds a vector constantto a packed float.
LCPI1_0: <4 x float> < float 0.0e+0, float 0.0e+0, float 0.0e+0, float 1.0e+0 >
.space 4
.space 4
.space 4
.long 1065353216 ; float 1
.text
.align 4
.globl _foo
_foo:
lis r2, ha16(LCPI1_0)
la r2, lo16(LCPI1_0)(r2)
li r4, 0
lvx v0, r4, r2
lvx v1, r4, r3
vaddfp v0, v1, v0
stvx v0, r4, r3
blr
For the llvm code:
void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = add <4 x float> %tmp1, < float 0.0, float 0.0, float 0.0, float 1.0 >
store <4 x float> %tmp2, <4 x float> *%a
ret void
}
llvm-svn: 24616
2005-12-06 06:18:55 +00:00
3539778883
Fix the #1 code quality problem that I have seen on X86 (and it also affects
...
PPC and other targets). In a particular, consider code like this:
struct Vector3 { double x, y, z; };
struct Matrix3 { Vector3 a, b, c; };
double dot(Vector3 &a, Vector3 &b) {
return a.x * b.x + a.y * b.y + a.z * b.z;
}
Vector3 mul(Vector3 &a, Matrix3 &b) {
Vector3 r;
r.x = dot( a, b.a );
r.y = dot( a, b.b );
r.z = dot( a, b.c );
return r;
}
void transform(Matrix3 &m, Vector3 *x, int n) {
for (int i = 0; i < n; i++)
x[i] = mul( x[i], m );
}
we compile transform to a loop with all of the GEP instructions for indexing
into 'm' pulled out of the loop (9 of them). Because isel occurs a bb at a time
we are unable to fold the constant index into the loads in the loop, leading to
PPC code that looks like this:
LBB3_1: ; no_exit.preheader
li r2, 0
addi r6, r3, 64 ;; 9 values live across the loop body!
addi r7, r3, 56
addi r8, r3, 48
addi r9, r3, 40
addi r10, r3, 32
addi r11, r3, 24
addi r12, r3, 16
addi r30, r3, 8
LBB3_2: ; no_exit
lfd f0, 0(r30)
lfd f1, 8(r4)
fmul f0, f1, f0
lfd f2, 0(r3) ;; no constant indices folded into the loads!
lfd f3, 0(r4)
lfd f4, 0(r10)
lfd f5, 0(r6)
lfd f6, 0(r7)
lfd f7, 0(r8)
lfd f8, 0(r9)
lfd f9, 0(r11)
lfd f10, 0(r12)
lfd f11, 16(r4)
fmadd f0, f3, f2, f0
fmul f2, f1, f4
fmadd f0, f11, f10, f0
fmadd f2, f3, f9, f2
fmul f1, f1, f6
stfd f0, 0(r4)
fmadd f0, f11, f8, f2
fmadd f1, f3, f7, f1
stfd f0, 8(r4)
fmadd f0, f11, f5, f1
addi r29, r4, 24
stfd f0, 16(r4)
addi r2, r2, 1
cmpw cr0, r2, r5
or r4, r29, r29
bne cr0, LBB3_2 ; no_exit
uh, yuck. With this patch, we now sink the constant offsets into the loop, producing
this code:
LBB3_1: ; no_exit.preheader
li r2, 0
LBB3_2: ; no_exit
lfd f0, 8(r3)
lfd f1, 8(r4)
fmul f0, f1, f0
lfd f2, 0(r3)
lfd f3, 0(r4)
lfd f4, 32(r3) ;; much nicer.
lfd f5, 64(r3)
lfd f6, 56(r3)
lfd f7, 48(r3)
lfd f8, 40(r3)
lfd f9, 24(r3)
lfd f10, 16(r3)
lfd f11, 16(r4)
fmadd f0, f3, f2, f0
fmul f2, f1, f4
fmadd f0, f11, f10, f0
fmadd f2, f3, f9, f2
fmul f1, f1, f6
stfd f0, 0(r4)
fmadd f0, f11, f8, f2
fmadd f1, f3, f7, f1
stfd f0, 8(r4)
fmadd f0, f11, f5, f1
addi r6, r4, 24
stfd f0, 16(r4)
addi r2, r2, 1
cmpw cr0, r2, r5
or r4, r6, r6
bne cr0, LBB3_2 ; no_exit
This is much nicer as it reduces register pressure in the loop a lot. On X86,
this takes the function from having 9 spilled registers to 2. This should help
some spec programs on X86 (gzip?)
This is currently only enabled with -enable-gep-isel-opt to allow perf testing
tonight.
llvm-svn: 24606
2005-12-05 07:10:48 +00:00
8782b782cd
dbg.stoppoint returns a value, don't forget to init it
...
llvm-svn: 24583
2005-12-03 18:50:48 +00:00
1064d6ec43
First chunk of actually generating vector code for packed types. These
...
changes allow us to generate the following code:
_foo:
li r2, 0
lvx v0, r2, r3
vaddfp v0, v0, v0
stvx v0, r2, r3
blr
for this llvm:
void %foo(<4 x float>* %a) {
entry:
%tmp1 = load <4 x float>* %a
%tmp2 = add <4 x float> %tmp1, %tmp1
store <4 x float> %tmp2, <4 x float>* %a
ret void
}
llvm-svn: 24534
2005-11-30 08:22:07 +00:00
3fd1b4c9bf
Fix a problem with llvm-ranlib that (on some platforms) caused the archive
...
file to become corrupted due to interactions between mmap'd memory segments
and file descriptors closing. The problem is completely avoiding by using
a third temporary file.
Patch provided by Evan Jones
llvm-svn: 24527
2005-11-30 05:21:10 +00:00
435b402e1f
Add support for a new STRING and LOCATION node for line number support, patch
...
contributed by Daniel Berlin, with a few cleanups here and there by me.
llvm-svn: 24515
2005-11-29 06:21:05 +00:00
d37c13154a
Check in code to scalarize arbitrarily wide packed types for some simple
...
vector operations (load, add, sub, mul).
This allows us to codegen:
void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = add <4 x float> %tmp1, %tmp1
store <4 x float> %tmp2, <4 x float> *%a
ret void
}
on ppc as:
_foo:
lfs f0, 12(r3)
lfs f1, 8(r3)
lfs f2, 4(r3)
lfs f3, 0(r3)
fadds f0, f0, f0
fadds f1, f1, f1
fadds f2, f2, f2
fadds f3, f3, f3
stfs f0, 12(r3)
stfs f1, 8(r3)
stfs f2, 4(r3)
stfs f3, 0(r3)
blr
llvm-svn: 24484
2005-11-22 18:16:00 +00:00
07890bbec4
Rather than attempting to legalize 1 x float, make sure the SD ISel never
...
generates it. Make MVT::Vector expand-only, and remove the code in
Legalize that attempts to legalize it.
The plan for supporting N x Type is to continually epxand it in ExpandOp
until it gets down to 2 x Type, where it will be scalarized into a pair of
scalars.
llvm-svn: 24482
2005-11-22 01:29:36 +00:00
19baba67b5
Unbreak codegen of bools. This should fix the llc/jit/llc-beta failures
...
from last night.
llvm-svn: 24427
2005-11-19 18:40:42 +00:00
b2e089c31b
Teach LLVM how to scalarize packed types. Currently, this only works on
...
packed types with an element count of 1, although more generic support is
coming. This allows LLVM to turn the following code:
void %foo(<1 x float> * %a) {
entry:
%tmp1 = load <1 x float> * %a;
%tmp2 = add <1 x float> %tmp1, %tmp1
store <1 x float> %tmp2, <1 x float> *%a
ret void
}
Into:
_foo:
lfs f0, 0(r3)
fadds f0, f0, f0
stfs f0, 0(r3)
blr
llvm-svn: 24416
2005-11-19 00:36:38 +00:00
127321b14c
Split out the shift code from visitBinary.
...
llvm-svn: 24412
2005-11-18 07:42:56 +00:00
f2b62f317c
when debugging lower dbg intrinsics to calls
...
llvm-svn: 24377
2005-11-16 07:22:30 +00:00
de1b5d6baa
added a chain output
...
llvm-svn: 24306
2005-11-11 22:48:54 +00:00
01aa56397d
continued readcyclecounter support
...
llvm-svn: 24300
2005-11-11 16:47:30 +00:00
cd6f0f47f2
Refactor intrinsic lowering stuff out of visitCall
...
llvm-svn: 24261
2005-11-09 19:44:01 +00:00
41fd6d5d27
Fix CodeGen/X86/shift-folding.ll:test3 on X86
...
llvm-svn: 24256
2005-11-09 16:50:40 +00:00
b7cad90e55
Avoid creating a token factor node in trivially redundant cases. This
...
eliminates almost one node per block in common cases.
llvm-svn: 24254
2005-11-09 05:03:03 +00:00
43535a19b1
Handle GEP's a bit more intelligently. Fold constant indices early and
...
turn power-of-two multiplies into shifts early to improve compile time.
llvm-svn: 24253
2005-11-09 04:45:33 +00:00
3ee3e69556
Add the necessary support to the ISel to allow targets to codegen the new
...
alignment information appropriately. Includes code for PowerPC to support
fixed-size allocas with alignment larger than the stack. Support for
arbitrarily aligned dynamic allocas coming soon.
llvm-svn: 24224
2005-11-06 09:00:38 +00:00
6871b23d02
Significantly simplify this code and make it more aggressive. Instead of having
...
a special case hack for X86, make the hack more general: if an incoming argument
register is not used in any block other than the entry block, don't copy it to
a vreg. This helps us compile code like this:
%struct.foo = type { int, int, [0 x ubyte] }
int %test(%struct.foo* %X) {
%tmp1 = getelementptr %struct.foo* %X, int 0, uint 2, int 100
%tmp = load ubyte* %tmp1 ; <ubyte> [#uses=1]
%tmp2 = cast ubyte %tmp to int ; <int> [#uses=1]
ret int %tmp2
}
to:
_test:
lbz r3, 108(r3)
blr
instead of:
_test:
lbz r2, 108(r3)
or r3, r2, r2
blr
The (dead) copy emitted to copy r3 into a vreg for extra-block uses was
increasing the live range of r3 past the load, preventing the coallescing.
This implements CodeGen/PowerPC/reg-coallesce-simple.ll
llvm-svn: 24115
2005-10-30 19:42:35 +00:00
78afac2ddd
Add the ability to lower return instructions to TargetLowering. This
...
allows us to lower legal return types to something else, to meet ABI
requirements (such as that i64 be returned in two i32 regs on Darwin/ppc).
llvm-svn: 23802
2005-10-18 23:23:37 +00:00
0a71a9ac86
Fix Generic/2005-10-18-ZeroSizeStackObject.ll by not requesting a zero
...
sized stack object if either the array size or the type size is zero.
llvm-svn: 23801
2005-10-18 22:14:06 +00:00
8396a308a7
remove hack
...
llvm-svn: 23797
2005-10-18 22:11:42 +00:00
bcfebebf22
Enable Nate's excellent DAG combiner work by default. This allows the
...
removal of a bunch of ad-hoc and crufty code from SelectionDAG.cpp.
llvm-svn: 23682
2005-10-10 16:47:10 +00:00
6bd8fd09b6
make sure that -view-isel-dags is the input to the isel, not the input to
...
the second phase of dag combining
llvm-svn: 23631
2005-10-05 06:09:10 +00:00
f8a5e5ae6e
Fix VC++ warnings.
...
llvm-svn: 23579
2005-10-01 03:57:14 +00:00
6f3b577ee6
Add FP versions of the binary operators, keeping the int and fp worlds seperate.
...
Though I have done extensive testing, it is possible that this will break
things in configs I can't test. Please let me know if this causes a problem
and I'll fix it ASAP.
llvm-svn: 23504
2005-09-28 22:28:18 +00:00
0fd8f9fbc9
If the target prefers it, use _setjmp/_longjmp should be used instead of setjmp/longjmp for llvm.setjmp/llvm.longjmp.
...
llvm-svn: 23481
2005-09-27 22:15:53 +00:00
d4382f0afa
If a function has liveins, and if the target requested that they be plopped
...
into particular vregs, emit copies into the entry MBB.
llvm-svn: 23331
2005-09-13 19:30:54 +00:00
007c650699
Add an option to the DAG Combiner to enable it for beta runs, and turn on
...
that option for PowerPC's beta.
llvm-svn: 23253
2005-09-07 00:15:36 +00:00
b0b4ec5655
Don't create zero sized stack objects even for array allocas with a zero
...
number of elements.
llvm-svn: 23219
2005-09-02 18:41:28 +00:00
b6cde17d29
Fix the release build, noticed by Eric van Riet Paap
...
llvm-svn: 23215
2005-09-02 07:09:28 +00:00
a66403dbf7
For values that are live across basic blocks and need promotion, use ANY_EXTEND
...
instead of ZERO_EXTEND to eliminate extraneous extensions. This eliminates
dead zero extensions on formal arguments and other cases on PPC, implementing
the newly tightened up test/Regression/CodeGen/PowerPC/small-arguments.ll test.
llvm-svn: 23205
2005-09-02 00:19:37 +00:00
975f5c9f46
It is NDEBUG not _NDEBUG
...
llvm-svn: 23186
2005-09-01 18:44:10 +00:00
075250bda1
Disable this code, which broke many tests last night
...
llvm-svn: 23114
2005-08-27 16:16:51 +00:00
e7a2998064
Don't copy regs that are only used in the entry block into a vreg. This
...
changes the code generated for:
short %test(short %A) {
%B = xor short %A, -32768
ret short %B
}
to:
_test:
xori r2, r3, 32768
xoris r2, r2, 65535
extsh r3, r2
blr
instead of:
_test:
rlwinm r2, r3, 0, 16, 31
xori r2, r3, 32768
xoris r2, r2, 65535
extsh r3, r2
blr
llvm-svn: 23109
2005-08-26 22:49:59 +00:00
13d7c252e5
Call the InsertAtEndOfBasicBlock hook if the usesCustomDAGSchedInserter
...
flag is set on an instruction.
llvm-svn: 23098
2005-08-26 20:54:47 +00:00
99282c7b92
Make -view-isel-dags show the dag before instruction selecting, in case
...
the target isel crashes due to unimplemented features like calls :)
llvm-svn: 22997
2005-08-24 00:34:29 +00:00
7f9e078d11
Fix a problem where constant expr shifts would not have their shift amount
...
promoted to the right type. This fixes: IA64/2005-08-22-LegalizerCrash.ll
llvm-svn: 22969
2005-08-22 17:28:31 +00:00
1a908c8920
Enable critical edge splitting by default
...
llvm-svn: 22863
2005-08-18 17:35:14 +00:00
c9950c11a9
Add a new beta option for critical edge splitting, to avoid a problem that
...
Nate noticed in yacr2 (and I know occurs in other places as well).
This is still rough, as the critical edge blocks are not intelligently placed
but is added to get some idea to see if this improves performance.
llvm-svn: 22825
2005-08-17 06:37:43 +00:00
ba28c2733f
Fix a regression on X86, where FP values can be promoted too.
...
llvm-svn: 22822
2005-08-17 06:06:25 +00:00
33182325f5
Eliminate the RegSDNode class, which 3 nodes (CopyFromReg/CopyToReg/ImplicitDef)
...
used to tack a register number onto the node.
Instead of doing this, make a new node, RegisterSDNode, which is a leaf
containing a register number. These three operations just become normal
DAG nodes now, instead of requiring special handling.
Note that with this change, it is no longer correct to make illegal
CopyFromReg/CopyToReg nodes. The legalizer will not touch them, and this
is bad, so don't do it. :)
llvm-svn: 22806
2005-08-16 21:55:35 +00:00
d47675ed24
Eliminate the SetCCSDNode in favor of a CondCodeSDNode class. This pulls the
...
CC out of the SetCC operation, making SETCC a standard ternary operation and
CC's a standard DAG leaf. This will make it possible for other node to use
CC's as operands in the future...
llvm-svn: 22728
2005-08-09 20:20:18 +00:00
5f4ef3c5a8
Eliminate all remaining tabs and trailing spaces.
...
llvm-svn: 22523
2005-07-27 06:12:32 +00:00
1ac40a1245
Remove unnecessary FP_EXTEND. This causes worse codegen for SSE.
...
llvm-svn: 22469
2005-07-19 16:50:03 +00:00
f5473e44a9
Make several cleanups to Andrews varargs change:
...
1. Pass Value*'s into lowering methods so that the proper pointers can be
added to load/stores from the valist
2. Intrinsics that return void should only return a token chain, not a token
chain/retval pair.
3. Rename LowerVAArgNext -> LowerVAArg, because VANext is long gone.
llvm-svn: 22338
2005-07-05 19:57:53 +00:00
2edc1881ac
restore old srcValueNode behavior and try to to work around it
...
llvm-svn: 22315
2005-06-29 18:54:02 +00:00
8192568fbc
tracking the instructions causing loads and stores provides more information than just the pointer being loaded or stored
...
llvm-svn: 22311
2005-06-29 15:57:19 +00:00
253145299b
If we support structs as va_list, we must pass pointers to them to va_copy
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See last commit for LangRef, this implements it on all targets.
llvm-svn: 22273
2005-06-22 21:04:42 +00:00
9144ec4764
core changes for varargs
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llvm-svn: 22254
2005-06-18 18:34:52 +00:00
e4f71d036f
Fix construction of ioport intrinsics, fixing X86/io.llx and io-port.llx
...
llvm-svn: 22026
2005-05-14 13:56:55 +00:00
96c262e24b
Eliminate special purpose hacks for dynamic_stack_alloc.
...
llvm-svn: 22015
2005-05-14 07:29:57 +00:00
29dcc71d83
LowerOperation takes a dag
...
llvm-svn: 22004
2005-05-14 05:50:48 +00:00
cbefe72fb2
Align doubles on 8-byte boundaries if possible.
...
llvm-svn: 21993
2005-05-13 23:14:17 +00:00
2e77db6af6
Add an isTailCall flag to LowerCallTo
...
llvm-svn: 21958
2005-05-13 18:50:42 +00:00
d0b0ecca3f
Emit function entry code after lowering hte arguments.
...
llvm-svn: 21931
2005-05-13 07:33:32 +00:00
0220b2952f
Allow targets to emit code into the entry block of each function
...
llvm-svn: 21930
2005-05-13 07:23:21 +00:00
111778e665
Pass calling convention to use into lower call to
...
llvm-svn: 21900
2005-05-12 19:56:57 +00:00
490769c5b6
wrap long line
...
llvm-svn: 21870
2005-05-11 18:57:06 +00:00
2d8b55c476
The semantics of cast X to bool are a comparison against zero, not a truncation!
...
llvm-svn: 21833
2005-05-09 22:17:13 +00:00
20eaeae966
Add support for matching the READPORT, WRITEPORT, READIO, WRITEIO intrinsics
...
llvm-svn: 21825
2005-05-09 20:22:36 +00:00
57d294f2ac
Don't use the load/store instruction as the source pointer, use the pointer
...
being stored/loaded through!
llvm-svn: 21806
2005-05-09 04:28:51 +00:00
f5675a0813
wrap long lines
...
llvm-svn: 21804
2005-05-09 04:08:33 +00:00
7876156ba0
When hitting an unsupported intrinsic, actually print it
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Lower debug info to noops.
llvm-svn: 21698
2005-05-05 17:55:17 +00:00
5e177826fd
Implement count leading zeros (ctlz), count trailing zeros (cttz), and count
...
population (ctpop). Generic lowering is implemented, however only promotion
is implemented for SelectionDAG at the moment.
More coming soon.
llvm-svn: 21676
2005-05-03 17:19:30 +00:00
8002640eab
Codegen and legalize sin/cos/llvm.sqrt as FSIN/FCOS/FSQRT calls. This patch
...
was contributed by Morten Ofstad, with some minor tweaks and bug fixes added
by me.
llvm-svn: 21636
2005-04-30 04:43:14 +00:00
4a73c2cfdc
Implement Value* tracking for loads and stores in the selection DAG. This enables one to use alias analysis in the backends.
...
(TRUNK)Stores and (EXT|ZEXT|SEXT)Loads have an extra SDOperand which is a SrcValueSDNode which contains the Value*. Note that if the operation is introduced by the backend, it will still have the operand, but the value* will be null.
llvm-svn: 21599
2005-04-27 20:10:01 +00:00
774511633d
Convert tabs to spaces
...
llvm-svn: 21439
2005-04-22 04:01:18 +00:00
835702a094
Remove trailing whitespace
...
llvm-svn: 21420
2005-04-21 22:36:52 +00:00
af1c0f7a00
Fold shift by size larger than type size to undef
...
Make llvm undef values generate ISD::UNDEF nodes
llvm-svn: 21261
2005-04-12 23:12:17 +00:00
8a98c7f337
Emit BRCONDTWOWAY when possible.
...
llvm-svn: 21167
2005-04-09 03:30:29 +00:00
0c14000760
transform fabs/fabsf calls into FABS nodes.
...
llvm-svn: 21014
2005-04-02 05:26:53 +00:00
f68fd0b533
Turn -0.0 - X -> fneg
...
llvm-svn: 21011
2005-04-02 05:04:50 +00:00
dec53920b4
PCMarker support for DAG and Alpha
...
llvm-svn: 20965
2005-03-31 21:24:06 +00:00
5ca31d9831
Instead of setting up the CFG edges at selectiondag construction time, set
...
them up after the code has been emitted. This allows targets to select one
mbb as multiple mbb's as needed.
llvm-svn: 20937
2005-03-30 01:10:47 +00:00
db45f7d763
Fix a bug that andrew noticed where we do not correctly sign/zero extend
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returned integer values all of the way to 64-bits (we only did it to 32-bits
leaving the top bits undefined). This causes problems for targets like alpha
whose ABI's define the top bits too.
llvm-svn: 20926
2005-03-29 19:09:56 +00:00
f656525cb6
Change interface to LowerCallTo to take a boolean isVarArg argument.
...
llvm-svn: 20842
2005-03-26 01:29:23 +00:00
531f9e92d4
This mega patch converts us from using Function::a{iterator|begin|end} to
...
using Function::arg_{iterator|begin|end}. Likewise Module::g* -> Module::global_*.
This patch is contributed by Gabor Greif, thanks!
llvm-svn: 20597
2005-03-15 04:54:21 +00:00
73e929f89d
Fix compilation errors with VS 2005, patch by Aaron Gray.
...
llvm-svn: 20231
2005-02-17 21:39:27 +00:00
0c56a548ed
Don't sink argument loads into loops or other bad places. This disables folding of argument loads with instructions that are not in the entry block.
...
llvm-svn: 20228
2005-02-17 19:40:32 +00:00
ffcb0ae329
Adjust to changes in SelectionDAG interface.
...
llvm-svn: 19779
2005-01-23 04:36:26 +00:00
eccb73d57f
Get this to work for 64-bit systems.
...
llvm-svn: 19763
2005-01-22 23:04:37 +00:00
96c26751ec
Support targets that do not use i8 shift amounts.
...
llvm-svn: 19707
2005-01-19 22:31:21 +00:00
9f2c4a5200
Teach legalize to promote copy(from|to)reg, instead of making the isel pass
...
do it. This results in better code on X86 for floats (because if strict
precision is not required, we can elide some more expensive double -> float
conversions like the old isel did), and allows other targets to emit
CopyFromRegs that are not legal for arguments.
llvm-svn: 19668
2005-01-18 17:54:55 +00:00
b07e2d2084
Allow setcc operations to have nonbool types.
...
llvm-svn: 19656
2005-01-18 02:52:03 +00:00
4d9651c760
Non-volatile loads can be freely reordered against each other. This fixes
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X86/reg-pressure.ll again, and allows us to do nice things in other cases.
For example, we now codegen this sort of thing:
int %loadload(int *%X, int* %Y) {
%Z = load int* %Y
%Y = load int* %X ;; load between %Z and store
%Q = add int %Z, 1
store int %Q, int* %Y
ret int %Y
}
Into this:
loadload:
mov %EAX, DWORD PTR [%ESP + 4]
mov %EAX, DWORD PTR [%EAX]
mov %ECX, DWORD PTR [%ESP + 8]
inc DWORD PTR [%ECX]
ret
where we weren't able to form the 'inc [mem]' before. This also lets the
instruction selector emit loads in any order it wants to, which can be good
for register pressure as well.
llvm-svn: 19644
2005-01-17 22:19:26 +00:00
4108bb01cf
Don't call SelectionDAG.getRoot() directly, go through a forwarding method.
...
llvm-svn: 19642
2005-01-17 19:43:36 +00:00
e3c2cf4854
Implement a target independent optimization to codegen arguments only into
...
the basic block that uses them if possible. This is a big win on X86, as it
lets us fold the argument loads into instructions and reduce register pressure
(by not loading all of the arguments in the entry block).
For this (contrived to show the optimization) testcase:
int %argtest(int %A, int %B) {
%X = sub int 12345, %A
br label %L
L:
%Y = add int %X, %B
ret int %Y
}
we used to produce:
argtest:
mov %ECX, DWORD PTR [%ESP + 4]
mov %EAX, 12345
sub %EAX, %ECX
mov %EDX, DWORD PTR [%ESP + 8]
.LBBargtest_1: # L
add %EAX, %EDX
ret
now we produce:
argtest:
mov %EAX, 12345
sub %EAX, DWORD PTR [%ESP + 4]
.LBBargtest_1: # L
add %EAX, DWORD PTR [%ESP + 8]
ret
This also fixes the FIXME in the code.
BTW, this occurs in real code. 164.gzip shrinks from 8623 to 8608 lines of
.s file. The stack frame in huft_build shrinks from 1644->1628 bytes,
inflate_codes shrinks from 116->108 bytes, and inflate_block from 2620->2612,
due to fewer spills.
Take that alkis. :-)
llvm-svn: 19639
2005-01-17 17:55:19 +00:00
16f64df93a
Refactor code into a new method.
...
llvm-svn: 19635
2005-01-17 17:15:02 +00:00
897cd7dc0a
add method stub
...
llvm-svn: 19612
2005-01-16 07:28:41 +00:00
209f585033
Add support for promoted registers being live across blocks.
...
llvm-svn: 19595
2005-01-16 02:23:07 +00:00
d58384fca6
Use the new TLI method to get this.
...
llvm-svn: 19582
2005-01-16 01:11:19 +00:00
a8d34fb8c6
Add support for targets that require promotions.
...
llvm-svn: 19579
2005-01-16 00:37:38 +00:00
1001c6e2cd
Add new SIGN_EXTEND_INREG, ZERO_EXTEND_INREG, and FP_ROUND_INREG operators.
...
llvm-svn: 19568
2005-01-15 06:17:04 +00:00
3b8e719d1d
Adjust to CopyFromReg changes, implement deletion of truncating/extending
...
stores/loads.
llvm-svn: 19562
2005-01-14 22:38:01 +00:00
e727af06c8
Add new ImplicitDef node, rename CopyRegSDNode class to RegSDNode.
...
llvm-svn: 19535
2005-01-13 20:50:02 +00:00
2451684678
Don't forget the existing root.
...
llvm-svn: 19531
2005-01-13 19:53:14 +00:00
718b5c2f82
Codegen independent ops as being independent.
...
llvm-svn: 19528
2005-01-13 17:59:43 +00:00
e05a461f1d
Add an option to view the selection dags as they are generated.
...
llvm-svn: 19498
2005-01-12 03:41:21 +00:00
613f79fcbb
add an assertion, avoid creating copyfromreg/copytoreg pairs that are the
...
same for PHI nodes.
llvm-svn: 19484
2005-01-11 22:03:46 +00:00
875def9b71
Turn memset/memcpy/memmove into the corresponding operations.
...
llvm-svn: 19463
2005-01-11 05:56:49 +00:00
a2c5d9168c
Handle static alloca arguments to PHI nodes.
...
llvm-svn: 19409
2005-01-09 01:16:24 +00:00
58cfd7945d
Use new interfaces to correctly lower varargs and return/frame address intrinsics.
...
llvm-svn: 19407
2005-01-09 00:00:49 +00:00
18d2b34637
Add support for llvm.setjmp and longjmp. Only 3 SingleSource/UnitTests fail now.
...
llvm-svn: 19404
2005-01-08 22:48:57 +00:00
d006195517
Silence VS warnings.
...
llvm-svn: 19384
2005-01-08 19:52:31 +00:00
1f45cd7418
Adjust to changes in LowerCAllTo interfaces
...
llvm-svn: 19374
2005-01-08 19:26:18 +00:00
2a6db3c351
Add support for FP->INT conversions and back.
...
llvm-svn: 19369
2005-01-08 08:08:56 +00:00
19a83990e1
Implement support for long GEP indices on 32-bit archs and support for
...
int GEP indices on 64-bit archs.
llvm-svn: 19354
2005-01-07 21:56:57 +00:00
8ea875fb05
Fix handling of dead PHI nodes.
...
llvm-svn: 19349
2005-01-07 21:34:19 +00:00
7a60d91953
Initial implementation of the SelectionDAGISel class. This contains most
...
of the code for lowering from LLVM code to a SelectionDAG.
llvm-svn: 19331
2005-01-07 07:47:53 +00:00
Evan Cheng