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Commit Graph

Author	SHA1	Message	Date
David Sherwood	a65092040a	[SVE] Fix inline assembly parsing crash This patch fixes a crash encountered when compiling this code: ... float16_t a; __asm__("fminv %h[a], %[b], %[c].h" : [a] "=r" (a) : [b] "Upl" (b), [c] "w" (c)) The issue here is when using the 'h' modifier for a register constraint 'r'. Differential Revision: https://reviews.llvm.org/D93537	2021-01-04 09:11:05 +00:00
David Sherwood	59f17b57d9	[SVE] Fix crashes with inline assembly All the crashes found compiling inline assembly are fixed in this patch by changing AArch64TargetLowering::getRegForInlineAsmConstraint to be more resilient to mismatched value and register types. For example, it makes no sense to request a predicate register for a nxv2i64 type and so on. Tests have been added here: test/CodeGen/AArch64/inline-asm-constraints-bad-sve.ll Differential Revision: https://reviews.llvm.org/D92554	2020-12-08 13:48:43 +00:00

Author

SHA1

Message

Date

David Sherwood

a65092040a

[SVE] Fix inline assembly parsing crash

This patch fixes a crash encountered when compiling this code:

  ...
  float16_t a;
  __asm__("fminv %h[a], %[b], %[c].h"
          : [a] "=r" (a)
          : [b] "Upl" (b), [c] "w" (c))

The issue here is when using the 'h' modifier for a register
constraint 'r'.

Differential Revision: https://reviews.llvm.org/D93537

2021-01-04 09:11:05 +00:00

David Sherwood

59f17b57d9

[SVE] Fix crashes with inline assembly

All the crashes found compiling inline assembly are fixed in this
patch by changing AArch64TargetLowering::getRegForInlineAsmConstraint
to be more resilient to mismatched value and register types. For
example, it makes no sense to request a predicate register for
a nxv2i64 type and so on.

Tests have been added here:

  test/CodeGen/AArch64/inline-asm-constraints-bad-sve.ll

Differential Revision: https://reviews.llvm.org/D92554

2020-12-08 13:48:43 +00:00

2 Commits