llvm-project

Commit Graph

Author	SHA1	Message	Date
Hsiangkai Wang	8b33839f01	[RISCV] Rename vector inline constraint from 'v' to 'vr' and 'vm' in IR. Differential Revision: https://reviews.llvm.org/D107139	2021-08-01 05:58:17 +08:00
Hsiangkai Wang	a81dff1e58	[RISCV] Support inline asm for vector instructions. Types of fractional LMUL and LMUL=1 are all using VR register class. When using inline asm, it will use the first type in the register class as the type for the register. It is not necessary the same as the value type. We need to use INSERT_SUBVECTOR/EXTRACT_SUBVECToR/BITCAST to make it legal to put the value in the corresponding register class. Differential Revision: https://reviews.llvm.org/D97480	2021-03-15 11:02:18 +08:00

Author

SHA1

Message

Date

Hsiangkai Wang

8b33839f01

[RISCV] Rename vector inline constraint from 'v' to 'vr' and 'vm' in IR.

Differential Revision: https://reviews.llvm.org/D107139

2021-08-01 05:58:17 +08:00

Hsiangkai Wang

a81dff1e58

[RISCV] Support inline asm for vector instructions.

Types of fractional LMUL and LMUL=1 are all using VR register class. When
using inline asm, it will use the first type in the register class as the
type for the register. It is not necessary the same as the value type. We
need to use INSERT_SUBVECTOR/EXTRACT_SUBVECToR/BITCAST to make it legal
to put the value in the corresponding register class.

Differential Revision: https://reviews.llvm.org/D97480

2021-03-15 11:02:18 +08:00

2 Commits