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6 Commits

Author SHA1 Message Date
Jim Lin 242ddd5089 [RISCV][NFC] Add a single space after comma for VType 
In most of cases, it has a single space after comma in assembly operands.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D103790
 2021-06-09 11:18:22 +08:00
Craig Topper 262a72f50f [RISCV] Use stack slot to handle SPLAT_VECTOR_PARTS on RV32. 
Reduces the amount of vector ALU operations and reduces vector
register pressure.
 2021-04-26 15:43:02 -07:00
Fraser Cormack c141bd3cf9 [DAGCombiner] Support all-ones/all-zeros SPLAT_VECTOR in more combines 
This patch adds incrementally-better support for SPLAT_VECTOR in a
handful of vector combines by changing a few more
isBuildVectorAllOnes/isBuildVectorAllZeros to the equivalent
isConstantSplatVectorAllOnes/Zeros calls.

Reviewed By: paulwalker-arm

Differential Revision: https://reviews.llvm.org/D100851
 2021-04-21 11:05:37 +01:00
Fraser Cormack 60622b82a7 [RISCV][NFC] Add tests for scalable-vector DAGCombiner improvements 
These will all be improved by future patches.
 2021-04-20 14:26:26 +01:00
Hsiangkai Wang 6e360460f1 [RISCV] Use v8-v23 as argument registers to conform to the proposal. 
The maximum LMUL is 8. We need 16 vector registers for two LMUL-8
arguments. The modification follows the proposal of psABI in
https://github.com/riscv/riscv-elf-psabi-doc/pull/171

Differential Revision: https://reviews.llvm.org/D95134
 2021-01-22 07:55:24 +08:00
Fraser Cormack 9ecc991c55 [RISCV] Add scalable vector vselect ISel patterns 
Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D94294
 2021-01-11 22:41:34 +00:00