50bd686695
Add support for branch forms of ALU instructions to Cortex-A57 model
...
Patch fixes scheduling of ALU instructions which modify pc register. Patch
also fixes computation of mutually exclusive predicates for sequences of
variants to be properly expanded
Differential revision: https://reviews.llvm.org/D91266
2020-11-24 11:43:51 +03:00
885d3f4129
[llvm-mca] Add branch forms of ALU instructions to Cortex-A57 test
2020-11-09 16:53:50 +03:00
cc96a82291
[TableGen][SchedModels] Fix read/write variant substitution
...
Patch fixes case when sched class has write and read variants belonging
to different processor models.
Differential revision: https://reviews.llvm.org/D89777
2020-11-02 17:39:04 +03:00
a877bda397
Fix issue in cortex-a57 sched model
...
Differential revision: https://reviews.llvm.org/D90152
2020-10-26 20:16:40 +03:00
7a78073be7
[ARM][SchedModels] Let ldm* instruction scheduling use MCSchedPredicate
...
Differential revision: https://reviews.llvm.org/D89957
2020-10-23 10:33:20 +03:00
991e86156c
[ARM][SchedModels] Convert IsCPSRDefinedPred to MCSchedPredicate
...
Differential revision: https://reviews.llvm.org/D89460
2020-10-20 11:14:21 +03:00
8a7ca143f8
[ARM][SchedModels] Convert IsPredicatedPred to MCSchedPredicate
...
Differential revision: https://reviews.llvm.org/D89553
2020-10-19 11:37:54 +03:00
6e56046f65
[TableGen][SchedModels] Fix aliasing of SchedWriteVariant
...
Differential revision: https://reviews.llvm.org/D89114
2020-10-13 13:05:24 +03:00
7102793065
Add test for cortex-a57/ARM sched model. NFC
2020-10-12 12:49:56 +03:00
Evgeny Leviant