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251 Commits

Author SHA1 Message Date
Eric Christopher 2ef63183a5 Separate out the AES-NI instructions from the SSE4.2 instructions. Add 
a new subtarget option for AES and check for the support.  Add "westmere"
line of processors and add AES-NI support to the core i7.

Add a couple of TODOs for information I couldn't verify.

llvm-svn: 100231
 2010-04-02 21:54:27 +00:00
Evan Cheng 738b0f9ec7 Nehalem unaligned memory access is fast. 
llvm-svn: 100089
 2010-04-01 05:58:17 +00:00
Evan Cheng bf724b9ee0 Turning off post-ra scheduling for x86. It isn't a consistent win. 
llvm-svn: 98810
 2010-03-18 06:55:42 +00:00
Chris Lattner a30d4ce194 add support for pentium class CPUs which do not have cmov, 
PR4841.  Patch by Craig Smith!

llvm-svn: 98496
 2010-03-14 18:31:44 +00:00
Mikhail Glushenkov abd56bde0e 80-col violations/trailing whitespace. 
llvm-svn: 97427
 2010-02-28 22:54:30 +00:00
Anton Korobeynikov c3c357006e Setup correct data layout to match gcc's expectations on mingw32. 
llvm-svn: 95981
 2010-02-12 15:28:56 +00:00
Duncan Sands 0067d6bbbe Fix typo. 
llvm-svn: 93235
 2010-01-12 08:30:46 +00:00
Duncan Sands fd75e12954 Tweak commit 91745, which changed target data for both Mingw and Cygwin, 
to not touch Cygwin: the change caused llvm-gcc build failures due to
long double getting the wrong size.  Patch by Aaron Gray.

llvm-svn: 93234
 2010-01-12 08:21:07 +00:00
David Greene 206351a1ff Implement a feature (-vector-unaligned-mem) to allow targets to 
ignore alignment requirements for SIMD memory operands.  This
is useful on architectures like the AMD 10h that do not trap on
unaligned references if a status bit is twiddled at startup time.

llvm-svn: 93151
 2010-01-11 16:29:42 +00:00
Evan Cheng 71d7eaa87e Remove target attribute break-sse-dep. Instead, do not fold load into sse partial update instructions unless optimizing for size. 
llvm-svn: 91910
 2009-12-22 17:47:23 +00:00
Anton Korobeynikov 148d87b0b0 Bump alignment requirements for windows targets to achieve compartibility with vcpp. 
Based on patch by Michael Beck!

llvm-svn: 91745
 2009-12-19 02:04:23 +00:00
Evan Cheng 4cf30b72bf On recent Intel u-arch's, folding loads into some unary SSE instructions can 
be non-optimal. To be precise, we should avoid folding loads if the instructions
only update part of the destination register, and the non-updated part is not
needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these instructions breaks
the partial register dependency and it can improve performance. e.g.

movss (%rdi), %xmm0
cvtss2sd %xmm0, %xmm0

instead of
cvtss2sd (%rdi), %xmm0

An alternative method to break dependency is to clear the register first. e.g.
xorps %xmm0, %xmm0
cvtss2sd (%rdi), %xmm0

llvm-svn: 91672
 2009-12-18 07:40:29 +00:00
Dan Gohman 7a6611793f Target-independent support for TargetFlags on BlockAddress operands, 
and support for blockaddresses in x86-32 PIC mode.

llvm-svn: 89506
 2009-11-20 23:18:13 +00:00
David Goodwin b9fe5d5d02 Allow target to specify regclass for which antideps will only be broken along the critical path. 
llvm-svn: 88682
 2009-11-13 19:52:48 +00:00
David Goodwin 0d412c2528 Fixed to address code review. No functional changes. 
llvm-svn: 86634
 2009-11-10 00:48:55 +00:00
David Goodwin cf89db135e Allow targets to specify register classes whose member registers should not be renamed to break anti-dependencies. 
llvm-svn: 86628
 2009-11-10 00:15:47 +00:00
Chris Lattner 8714348afd indicate what the native integer types for the target are. 
Please verify.

llvm-svn: 86397
 2009-11-07 19:07:32 +00:00
Evan Cheng 8b86efefec X86 needs critical path anti-dependency breaking. 
llvm-svn: 84931
 2009-10-23 05:57:35 +00:00
David Goodwin 02ad4cb32e Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none. 
llvm-svn: 84911
 2009-10-22 23:19:17 +00:00
Evan Cheng c436631a9c Turn on post-alloc scheduling for x86. 
llvm-svn: 84431
 2009-10-18 19:57:27 +00:00
Evan Cheng 936d87b39d Oops. I forgot to change the tests first. Disable post-alloc scheduling. 
llvm-svn: 84425
 2009-10-18 18:31:31 +00:00
Evan Cheng 0e9d9ca855 -Revert parts of 84326 and 84411. Distinquishing between fixed and non-fixed 
stack slots and giving them different PseudoSourceValue's did not fix the
problem of post-alloc scheduling miscompiling llvm itself.
- Apply Dan's conservative workaround by assuming any non fixed stack slots can
alias other memory locations. This means a load from spill slot #1 cannot 
move above a store of spill slot #2. 
- Enable post-alloc scheduling for x86 at optimization leverl Default and above.

llvm-svn: 84424
 2009-10-18 18:16:27 +00:00
Evan Cheng 007ceb4603 Change createPostRAScheduler so it can be turned off at llc -O1. 
llvm-svn: 84273
 2009-10-16 21:06:15 +00:00
Evan Cheng e4a2117161 Remove X86Subtarget::IsLinux. It's no longer being used. 
llvm-svn: 84200
 2009-10-15 20:23:21 +00:00
Chris Lattner 46dcaadb4a rearrange X86ATTAsmPrinter::doFinalization, making a scan of 
the global variable list only happen for COFF targets.

llvm-svn: 82010
 2009-09-16 05:20:33 +00:00
Daniel Dunbar c3a0aba120 Make these functions static and local. 
llvm-svn: 80892
 2009-09-03 05:47:34 +00:00
Evan Cheng 47455a79ae X86JITInfo::getLazyResolverFunction() should not read cpu id to determine whether sse is available. Just use consult subtarget. 
No functionality changes.

llvm-svn: 80880
 2009-09-03 04:37:05 +00:00
Chris Lattner cc8c581a5b Add support for modeling whether or not the processor has support for 
conditional moves as a subtarget feature.  This is the easy part of 
PR4841.

llvm-svn: 80763
 2009-09-02 05:53:04 +00:00
Chris Lattner 1e9097e36a change the -x86-asm-syntax=intel/att flag to be in X86TAI 
instead of X86 Subtarget.  This elimianates dependencies on
X86Subtarget from X86TAI.

llvm-svn: 78746
 2009-08-11 23:01:09 +00:00
Daniel Dunbar 31b44e8f6c Normalize Subtarget constructors to take a target triple string instead of 
Module*.

Also, dropped uses of TargetMachine where unnecessary. The only target which
still takes a TargetMachine& is Mips, I would appreciate it if someone would
normalize this to match other targets.

llvm-svn: 77918
 2009-08-02 22:11:08 +00:00
Chris Lattner 21c2940553 remove the now-dead TM argument to these methods. 
llvm-svn: 75276
 2009-07-10 21:00:45 +00:00
Chris Lattner ba4d73310a make PIC vs DynamicNoPIC be explicit in PICStyles. 
llvm-svn: 75275
 2009-07-10 20:58:47 +00:00
Chris Lattner e2f524f176 add a couple of predicates to test for "stub style pic in PIC mode" and "stub style pic in dynamic-no-pic" mode. 
llvm-svn: 75273
 2009-07-10 20:47:30 +00:00
Chris Lattner 20073edf67 simplify fast isel by using ClassifyGlobalReference. This 
elimiantes the last use of GVRequiresExtraLoad, so delete it.

llvm-svn: 75244
 2009-07-10 07:48:51 +00:00
Chris Lattner 93f0f79178 eliminate GVRequiresRegister, replacing it with predicates we 
need for other purposes.

llvm-svn: 75243
 2009-07-10 07:38:24 +00:00
Chris Lattner dc842c06c2 move some classification logic around. Now GVRequiresExtraLoad 
is just a trivial wrapper around "ClassifyGlobalReference", which
stole a ton of logic from LowerGlobalAddress.

llvm-svn: 75237
 2009-07-10 07:20:05 +00:00
Chris Lattner b9af63a4d2 GVRequiresExtraLoad is now never used for calls, simplify it based on this. 
llvm-svn: 75232
 2009-07-10 05:52:02 +00:00
Chris Lattner ace6ec26d9 actually, just eliminate PCRelGVRequiresExtraLoad. It makes the code 
more complex and slow than just directly testing what we care about.

llvm-svn: 75231
 2009-07-10 05:48:03 +00:00
Chris Lattner 7277a807f0 There is only one case where GVRequiresExtraLoad returns true for calls: 
split its handling out to PCRelGVRequiresExtraLoad, and simplify code
based on this.

llvm-svn: 75230
 2009-07-10 05:45:15 +00:00
Chris Lattner 1cc7ae7c3b the "isDirectCall" operand of GVRequiresRegister is always false, eliminate it. 
llvm-svn: 75229
 2009-07-10 05:37:11 +00:00
Chris Lattner 1c5bf9d26d When in -static mode, force the PIC style to none. Doing this requires fixing 
code which conflated RIPRel PIC with x86-64.  Fix these to just check for X86-64
directly.

llvm-svn: 75092
 2009-07-09 03:15:51 +00:00
David Greene a4b8998fbb Fix a subtarget feature bug. 
llvm-svn: 74428
 2009-06-29 16:51:01 +00:00
David Greene 8f6f72cc99 Add feature flags for AVX and FMA and fix some SSE4A feature flag 
initialization problems.

llvm-svn: 74350
 2009-06-26 22:46:54 +00:00
Chris Lattner cfad3f3807 cosmetic changes. 
llvm-svn: 73836
 2009-06-21 01:27:55 +00:00
Stefanus Du Toit 96180b5387 Update CPU capabilities for AMD machines 
- added processors k8-sse3, opteron-sse3, athlon64-sse3, amdfam10, and
barcelona with appropriate sse3/4a levels
- added FeatureSSE4A for amdfam10 processors
in X86Subtarget:
- added hasSSE4A
- updated AutoDetectSubtargetFeatures to detect SSE4A
- updated GetCurrentX86CPU to detect family 15 with sse3 as k8-sse3 and
family 10h as amdfam10

New processor names match those used by gcc.

Patch by Paul Redmond!

llvm-svn: 72434
 2009-05-26 21:04:35 +00:00
Anton Korobeynikov 08bf4c0f5a Propagate CPU string out of SubtargetFeatures 
llvm-svn: 72335
 2009-05-23 19:50:50 +00:00
Evan Cheng 960983371c Try again. Allow call to immediate address for ELF or when in static relocation mode. 
llvm-svn: 72160
 2009-05-20 04:53:57 +00:00
Dan Gohman 906152a20f Tidy up #includes, deleting a bunch of unnecessary #includes. 
llvm-svn: 61715
 2009-01-05 17:59:02 +00:00
Evan Cheng 4c91aa3418 Do not isel load folding bt instructions for pentium m, core, core2, and AMD processors. These are significantly slower than a load followed by a bt of a register. 
llvm-svn: 61557
 2009-01-02 05:35:45 +00:00
Dan Gohman b9a012156b Add initial support for back-scheduling address computations, 
especially in the case of addresses computed from loop induction
variables.

llvm-svn: 61075
 2008-12-16 03:35:01 +00:00
Dale Johannesen b49d7cf19e Forgot a file. 
llvm-svn: 60609
 2008-12-05 21:55:35 +00:00
Duncan Sands 595a4423dc Fix build with gcc-4.4: it doesn't like PICStyle 
being both a namespace and a variable name.

llvm-svn: 60208
 2008-11-28 09:29:37 +00:00
Bill Wendling 1782584f56 Just don't transform this memset into "bzero" if no-builtin is specified. 
llvm-svn: 56888
 2008-09-30 22:05:33 +00:00
Bill Wendling bd09262e97 Add the new `-no-builtin' flag. This flag is meant to mimic the GCC 
`-fno-builtin' flag. Currently, it's used to replace "memset" with "_bzero"
instead of "__bzero" on Darwin10+. This arguably violates the meaning of this
flag, but is currently sufficient. The meaning of this flag should become more
specific over time.

llvm-svn: 56885
 2008-09-30 21:22:07 +00:00
Dan Gohman 6fd71c6512 Use a dedicated IsLinux flag instead of an ELFLinux TargetType. 
llvm-svn: 50649
 2008-05-05 16:11:31 +00:00
Dan Gohman bcde172222 Add AsmPrinter support for emitting a directive to declare that 
the code being generated does not require an executable stack.

Also, add target-specific code to make use of this on Linux
on x86. 

llvm-svn: 50634
 2008-05-05 00:28:39 +00:00
Evan Cheng 6c66bd368e Re-enable SSE4. 
llvm-svn: 49158
 2008-04-03 08:53:29 +00:00
Evan Cheng 3063c5546e Temporarily disabling SSE4 until we fix the encoding issues. 
llvm-svn: 49129
 2008-04-03 04:49:54 +00:00
Dan Gohman 980d7200c1 Speculatively micro-optimize memory-zeroing calls on Darwin 10. 
llvm-svn: 49048
 2008-04-01 20:38:36 +00:00
Anton Korobeynikov 7f125b2ba5 Add convenient helper for win64 check. Simplify things slightly. 
llvm-svn: 48691
 2008-03-22 20:57:27 +00:00
Evan Cheng 352acec37e Update comment. 
llvm-svn: 47002
 2008-02-12 07:59:55 +00:00
Evan Cheng a20a773654 Fix a x86-64 codegen deficiency. Allow gv + offset when using rip addressing mode. 
Before:
_main:
        subq    $8, %rsp
        leaq    _X(%rip), %rax
        movsd   8(%rax), %xmm1
        movss   _X(%rip), %xmm0
        call    _t
        xorl    %ecx, %ecx
        movl    %ecx, %eax
        addq    $8, %rsp
        ret
Now:
_main:
        subq    $8, %rsp
        movsd   _X+8(%rip), %xmm1
        movss   _X(%rip), %xmm0
        call    _t
        xorl    %ecx, %ecx
        movl    %ecx, %eax
        addq    $8, %rsp
        ret

Notice there is another idiotic codegen issue that needs to be fixed asap:
xorl    %ecx, %ecx
movl    %ecx, %eax

llvm-svn: 46850
 2008-02-07 08:53:49 +00:00
Nate Begeman e14fdfaecd SSE 4.1 Intrinsics and detection 
llvm-svn: 46681
 2008-02-03 07:18:54 +00:00
Chris Lattner cce79c67ca darwin9 and above support aligned common symbols. 
llvm-svn: 45494
 2008-01-02 19:44:55 +00:00
Chris Lattner f3ebc3f3d2 Remove attribution from file headers, per discussion on llvmdev. 
llvm-svn: 45418
 2007-12-29 20:36:04 +00:00
Rafael Espindola 063f177300 Make ARM an X86 memcpy expansion more similar to each other. 
Now both subtarget define getMaxInlineSizeThreshold and the expansion uses it.

This should not change generated code.

llvm-svn: 43552
 2007-10-31 11:52:06 +00:00
Rafael Espindola 1de0c86717 Add support for having different alignment for objects on call frames. 
The x86-64 ABI states that objects passed on the stack have
8 byte alignment. Implement that.

llvm-svn: 41768
 2007-09-07 14:52:14 +00:00
Evan Cheng 623dd88775 Mac OS X X86-64 ABI is same as the standard. 
llvm-svn: 41700
 2007-09-04 16:44:41 +00:00
Rafael Espindola bb8a5cff67 Align i64 and f64 at 8 byte on x86-64. 
This is mandated table 3.1 at
http://www.x86-64.org/documentation/abi.pdf

llvm-svn: 41642
 2007-08-31 12:23:58 +00:00
Dale Johannesen a010822b45 Replace 4-line function with 10-line version per review comment. 
llvm-svn: 40881
 2007-08-06 22:10:35 +00:00
Dale Johannesen d1822ea7d1 Move lengthy conditional down 1 level per review comment. 
llvm-svn: 40878
 2007-08-06 21:48:35 +00:00
Evan Cheng 763cdfd371 Mac OS X X86-64 low 4G address not available. 
llvm-svn: 40701
 2007-08-01 23:45:51 +00:00
Bill Wendling f099841573 Add support for our first SSSE3 instruction "pmulhrsw". 
llvm-svn: 35869
 2007-04-10 22:10:25 +00:00
Chris Lattner 6cc58a0dc5 document some subtlety 
llvm-svn: 33257
 2007-01-16 17:51:40 +00:00
Bill Wendling c7b2ab9bdf Instead of yet another enum indicating the "assembly language flavor", 
just use the one that's in the subtarget.

llvm-svn: 33255
 2007-01-16 09:29:17 +00:00
Anton Korobeynikov a0554d90e8 * PIC codegen for X86/Linux has been implemented 
* PIC-aware internal structures in X86 Codegen have been refactored
* Visibility (default/weak) has been added
* Docs fixes (external weak linkage, visibility, formatting)

llvm-svn: 33136
 2007-01-12 19:20:47 +00:00
Anton Korobeynikov 4efbbc963f Really big cleanup. 
- New target type "mingw" was introduced
- Same things for both mingw & cygwin are marked as "cygming" (as in
gcc)
- .lcomm is supported here, so allow LLVM to use it
- Correctly use underscored versions of setjmp & _longjmp for both mingw
& cygwin

llvm-svn: 32833
 2007-01-03 11:43:14 +00:00
Anton Korobeynikov 430e68a1b9 Refactored JIT codegen for mingw32. Now we're using standart relocation 
type for distinguish JIT & non-JIT instead of "dirty" hacks :)

llvm-svn: 32745
 2006-12-22 22:29:05 +00:00
Anton Korobeynikov 93acb49182 Fixed dllimported symbols support during JIT'ing. JIT on mingw32 
platform should be more or less workable. At least, sim is running fine
under lli :)

llvm-svn: 32711
 2006-12-20 01:03:20 +00:00
Anton Korobeynikov 6dbdfe2baa Factor out GVRequiresExtraLoad() from .h to .cpp 
llvm-svn: 32048
 2006-11-30 22:42:55 +00:00
Anton Korobeynikov 5b96cdebb0 Refactored *GVRequiresExtraLoad() to Subtarget method. 
llvm-svn: 31887
 2006-11-21 00:01:06 +00:00
Evan Cheng a8b4aeace0 Proper fix for rdar://problem/4770604 Thanks to Stuart Hastings! 
llvm-svn: 30985
 2006-10-16 21:00:37 +00:00
Evan Cheng ff1beda569 Still need to support -mcpu=<> or cross compilation will fail. Doh. 
llvm-svn: 30764
 2006-10-06 09:17:41 +00:00
Evan Cheng 9274f72e58 Do away with CPU feature list. Just use CPUID to detect MMX, SSE, SSE2, SSE3, and 64-bit support. 
llvm-svn: 30763
 2006-10-06 08:21:07 +00:00
Anton Korobeynikov d61d39ec53 Adding dllimport, dllexport and external weak linkage types. 
DLL* linkages got full (I hope) codegeneration support in C & both x86
assembler backends.
External weak linkage added for future use, we don't provide any
codegeneration, etc. support for it.

llvm-svn: 30374
 2006-09-14 18:23:27 +00:00
Evan Cheng 11b0a5dbd4 Committing X86-64 support. 
llvm-svn: 30177
 2006-09-08 06:48:29 +00:00
Chris Lattner 2785d55446 add a new value for the command line optn 
llvm-svn: 30165
 2006-09-07 22:32:28 +00:00
Jim Laskey c7abe471fe Make the x86 asm flavor part of the subtarget info. 
llvm-svn: 30146
 2006-09-07 12:23:47 +00:00
Chris Lattner e8ce162969 Add accessor 
llvm-svn: 30080
 2006-09-04 04:08:58 +00:00
Evan Cheng 5588de9415 x86 / Darwin PIC support. 
llvm-svn: 26273
 2006-02-18 00:15:05 +00:00
Evan Cheng 03c1e6f48e A bit more memset / memcpy optimization. 
Turns them into calls to memset / memcpy if 1) buffer(s) are not DWORD aligned,
2) size is not known to be greater or equal to some minimum value (currently 128).

llvm-svn: 26224
 2006-02-16 00:21:07 +00:00
Chris Lattner c642aa5e1c * Fix 80-column violations 
* Rename hasSSE -> hasSSE1 to avoid my continual confusion with 'has any SSE'.
* Add inline asm constraint specification.

llvm-svn: 25854
 2006-01-31 19:43:35 +00:00
Evan Cheng cde9e30bc6 x86 CPU detection and proper subtarget support 
llvm-svn: 25679
 2006-01-27 08:10:46 +00:00
Evan Cheng 54c13da29c Added preliminary x86 subtarget support. 
llvm-svn: 25645
 2006-01-26 09:53:06 +00:00
Chris Lattner 40f8c8450d Simplify the subtarget info, allow the asmwriter to do some target sensing 
based on TargetType.

llvm-svn: 24478
 2005-11-21 22:43:58 +00:00
Chris Lattner 3eb876117a Make the X86 subtarget compute the basic target type: ELF, Cygwin, Darwin, 
or native Win32

llvm-svn: 24476
 2005-11-21 22:31:58 +00:00
Jim Laskey 19058c3989 1. Use SubtargetFeatures in llc/lli. 
2. Propagate feature "string" to all targets.

3. Implement use of SubtargetFeatures in PowerPCTargetSubtarget.

llvm-svn: 23192
 2005-09-01 21:38:21 +00:00
Nate Begeman 3bcfcd9474 Add Subtarget support to PowerPC. Next up, using it. 
llvm-svn: 22644
 2005-08-04 07:12:09 +00:00
Jeff Cohen 33a030e36c Eliminate tabs and trailing spaces. 
llvm-svn: 22520
 2005-07-27 05:53:44 +00:00
Chris Lattner 351817b1f9 Minor changes to improve comments and fix the build on _WIN32 systems. 
llvm-svn: 22391
 2005-07-12 02:36:10 +00:00
Nate Begeman f26625e1de Implement Subtarget support 
Implement the X86 Subtarget.

This consolidates the checks for target triple, and setting options based
on target triple into one place.  This allows us to convert the asm printer
and isel over from being littered with "forDarwin", "forCygwin", etc. into
just having the appropriate flags for each subtarget feature controlling
the code for that feature.

This patch also implements indirect external and weak references in the
X86 pattern isel, for darwin.  Next up is to convert over the asm printers
to use this new interface.

llvm-svn: 22389
 2005-07-12 01:41:54 +00:00