388fa73f03
Minor code simplification.
...
llvm-svn: 104845
2010-05-27 16:25:05 +00:00
1c69646e99
Add the SubRegIndex TableGen class.
...
This is the beginning of purely symbolic subregister indices, but we need a bit
of jiggling before the explicit numeric indices can be completely removed.
llvm-svn: 104492
2010-05-24 14:48:12 +00:00
1a1b51ff59
Add initial kill flag support to FastISel.
...
llvm-svn: 103529
2010-05-11 23:54:07 +00:00
779c69bbc5
Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it
...
doesn't have to guess.
llvm-svn: 103194
2010-05-06 20:33:48 +00:00
6c2d178957
add plumbing for handling multiple result nodes
...
in some more places.
llvm-svn: 99366
2010-03-24 00:41:19 +00:00
f144725ebc
major surgery on tblgen: generalize TreePatternNode
...
to maintain a list of types (one for each result of
the node) instead of a single type. There are liberal
hacks added to emulate the old behavior in various
situations, but they can start disolving now.
llvm-svn: 98999
2010-03-19 21:37:09 +00:00
9aec14b560
look up instructions by record, not by name.
...
llvm-svn: 98904
2010-03-19 00:07:20 +00:00
cabe037b2d
Completely rewrite tblgen's type inference mechanism,
...
changing the primary datastructure from being a
"std::vector<unsigned char>" to being a new TypeSet class
that actually has (gasp) invariants!
This changes more things than I remember, but one major
innovation here is that it enforces that named input
values agree in type with their output values.
This also eliminates code that transparently assumes (in
some cases) that SDNodeXForm input/output types are the
same, because this is wrong in many case.
This also eliminates a bug which caused a lot of ambiguous
patterns to go undetected, where a register class would
sometimes pick the first possible type, causing an
ambiguous pattern to get arbitrary results.
With all the recent target changes, this causes no
functionality change!
llvm-svn: 98534
2010-03-15 06:00:16 +00:00
404a984780
Don't use the ISD::NodeType enum for SDNode opcodes, as CodeGen
...
uses several kinds of opcode values which are not declared within
that enum. This fixes PR5946.
llvm-svn: 92794
2010-01-05 22:26:32 +00:00
2fbeaf084f
Remove some unused variables and methods warned about by
...
icc (#177 , partial). Patch by Erick Tryzelaar.
llvm-svn: 81106
2009-09-06 08:33:48 +00:00
9f94459d24
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
...
the latter is capable of representing either a primitive or an extended type.
llvm-svn: 78713
2009-08-11 20:47:22 +00:00
53aa7a960c
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
...
llvm-svn: 78610
2009-08-10 22:56:29 +00:00
38a22bffdc
Replace std::iostreams with raw_ostream in TableGen.
...
- Sorry, I can't help myself.
- No intended functionality change.
llvm-svn: 74742
2009-07-03 00:10:29 +00:00
4ff70e389e
TableGen for fast isel seems to assume an 'imm'
...
operand is the last in a pattern. There is no
reason this should be true (although apparently
it always is right now).
llvm-svn: 72232
2009-05-21 22:25:49 +00:00
4a0bf66eb8
Eliminate a couple of fields from TargetRegisterClass: SubRegClasses and SuperRegClasses. These are not necessary. Also eliminate getSubRegisterRegClass and getSuperRegisterRegClass. These are slow and their results can change if register file names change. Just use TargetLowering::getRegClassFor() to get the right TargetRegisterClass instead.
...
llvm-svn: 62762
2009-01-22 09:10:11 +00:00
6e979020cd
Add support for having multiple predicates on a TreePatternNode.
...
This will allow predicates to be composed, which will allow the
predicate definitions to become less redundant, and eventually
will allow DAGISelEmitter.cpp to emit less redundant code.
llvm-svn: 57562
2008-10-15 06:17:21 +00:00
b486350b15
Move the primary fast-isel top-level comments to FastISel.cpp, where
...
they'll be a little more visible. Also, update and reword them a bit.
llvm-svn: 56877
2008-09-30 20:48:29 +00:00
ca14c07175
Correctly handle physical register inputs. They are not explicit input operands in the resulting machine instrs.
...
llvm-svn: 55893
2008-09-08 08:39:33 +00:00
09638d34a5
Fix indentation of generated code.
...
llvm-svn: 55876
2008-09-07 08:23:06 +00:00
7cab17af29
Ignore multi-instruction patterns. e.g.
...
def : Pat<(i8 (trunc GR32:$src)),
(i8 (EXTRACT_SUBREG (MOV32to32_ GR32:$src), x86_subreg_8bit))>
llvm-svn: 55875
2008-09-07 08:19:51 +00:00
24422d4928
Let tblgen only generate fastisel routines, not the class definition. This makes it easier for targets to define its own fastisel class.
...
llvm-svn: 55679
2008-09-03 00:03:49 +00:00
0673a8af14
Add initial support for fast isel of instructions that have inputs pinned to physical registers.
...
llvm-svn: 55545
2008-08-29 17:45:56 +00:00
d58f3e36d0
Add a target callback for FastISel.
...
llvm-svn: 55512
2008-08-28 23:21:34 +00:00
787f100462
Add support for fast-isel of opcodes that require use of extract_subreg. Because of how extract_subreg is treated, it requires special case handling.
...
llvm-svn: 55480
2008-08-28 18:06:12 +00:00
6d153b02c9
Update a comment to reflect recent changes.
...
llvm-svn: 55418
2008-08-27 16:18:22 +00:00
5ca269e684
Basic FastISel support for floating-point constants.
...
llvm-svn: 55401
2008-08-27 01:09:54 +00:00
44003cc354
Refactor a bunch of FastISelEmitter code into a helper class, and
...
put each major step in a separate function. This makes the high
level sequence of events easier to follow.
llvm-svn: 55385
2008-08-26 21:21:20 +00:00
3ea3efec44
We need to check that the return type is correct, even in cases where we don't
...
have a return type that differs from the operand types.
llvm-svn: 55376
2008-08-26 18:50:00 +00:00
6f2db7238b
Throw the switch to allow FastISel to emit instructions whose return types different from their inputs. Next step: adding lowering pattens in FastISel that actually use these newly available opcodes.
...
llvm-svn: 55349
2008-08-26 01:22:59 +00:00
5f334d8215
Enhance TableGen to emit code for FastISel of opcodes with variadic return types without slowing down opcodes that are not variadic. No such opcodes are currently generated, but in theory it should be a matter of just hitting the switch.
...
llvm-svn: 55347
2008-08-26 00:42:26 +00:00
8dd01ccdd8
Add a RetVT parameter to emitted FastISel methods, so that we will be able to pass the desired return
...
type down. This is not currently used.
llvm-svn: 55345
2008-08-25 23:58:18 +00:00
5952cca7d1
Deepen the map structure tablegen uses to compute FastISel patterns, in preparation for having patterns
...
with return types that differ from their input types. This is not yet used.
llvm-svn: 55344
2008-08-25 23:43:09 +00:00
32635dbfb2
Add support for fast isel of (integer) immediate materialization pattens, and use them to support
...
bitcast of constants in fast isel.
llvm-svn: 55325
2008-08-25 20:20:32 +00:00
9b29ec7ba9
Add a few comments.
...
llvm-svn: 55157
2008-08-22 00:28:15 +00:00
49e19e906f
Factor out the predicate check code from DAGISelEmitter.cpp
...
and use it in FastISelEmitter.cpp, and make FastISel
subtarget aware. Among other things, this lets it work
properly on x86 targets that don't have SSE, where it
successfully selects x87 instructions.
llvm-svn: 55156
2008-08-22 00:20:26 +00:00
fe9056584b
Basic fast-isel support for instructions with constant int operands.
...
llvm-svn: 55099
2008-08-21 01:41:07 +00:00
7b3932e5d8
Remove the code that limited FastISel to certain fixed signatures.
...
llvm-svn: 55096
2008-08-21 00:35:26 +00:00
7170623b16
Begin making more use of the FastISelEmitter class.
...
llvm-svn: 55093
2008-08-21 00:19:05 +00:00
e6724d404b
Remove an obsolete todo comment.
...
llvm-svn: 55080
2008-08-20 21:47:28 +00:00
3e2225dfd6
Factor the code for determining the target-specific instruction
...
namespace out of the isel emitters and into common code.
llvm-svn: 55079
2008-08-20 21:45:57 +00:00
02c84b8910
Simplify FastISel's constructor argument list, make the FastISel
...
class hold a MachineRegisterInfo member, and make the
MachineBasicBlock be passed in to SelectInstructions rather
than the FastISel constructor.
llvm-svn: 55076
2008-08-20 21:05:57 +00:00
2dbebd7db5
For now, restrict FastISel to instructions that only involve one
...
register class.
llvm-svn: 55008
2008-08-19 20:58:14 +00:00
98e6f1c48a
Factor out the code to scan an instruction's operands into a
...
helper function.
llvm-svn: 55007
2008-08-19 20:56:30 +00:00
aa13b6f71b
Add more comments.
...
llvm-svn: 55004
2008-08-19 20:36:33 +00:00
49520b99a3
Fix indentation in FastISel tablegen-emitted code.
...
llvm-svn: 55003
2008-08-19 20:31:38 +00:00
a6c14d0ddb
Add more checking to filter out more kinds of things that
...
FastISel doesn't support yet.
llvm-svn: 55002
2008-08-19 20:30:54 +00:00
6a36fe912c
80 columns.
...
llvm-svn: 54998
2008-08-19 18:07:49 +00:00
dbd5328238
Add a few doxygen comments.
...
llvm-svn: 54997
2008-08-19 18:06:12 +00:00
b2226e21c3
Initial checkin of the new "fast" instruction selection support. See
...
the comments in FastISelEmitter.cpp for details on what this is.
This is currently experimental and unusable.
llvm-svn: 54751
2008-08-13 20:19:35 +00:00
Dan Gohman