Commit Graph

7 Commits

Author SHA1 Message Date
Carl Ritson d538c5837a [AMDGPU] Fix missed SI_RETURN_TO_EPILOG in pre-emit peephole
SIPreEmitPeephole does not process all terminators, which means
it can fail to handle SI_RETURN_TO_EPILOG if immediately preceeded
by a branch to the early exit block.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D85872
2020-08-13 21:52:41 +09:00
Carl Ritson 3a18665748 [AMDGPU] Translate s_and/s_andn2 to s_mov in vcc optimisation
When SCC is dead, but VCC is required then replace s_and / s_andn2
with s_mov into VCC when mask value is 0 or -1.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D83850
2020-07-17 11:48:57 +09:00
Carl Ritson 674226126d [AMDGPU] Apply pre-emit s_cbranch_vcc optimation to more patterns
Add handling of s_andn2 and mask of 0.
This eliminates redundant instructions from uniform control flow.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D83641
2020-07-15 11:02:35 +09:00
Christudasan Devadasan 226cda58d5 [AMDGPU] Moving SI_RETURN_TO_EPILOG handling out of SIInsertSkips.
For now, moving it to SIPreEmitPeephole.
Should find a right place to have this code.

Reviewed By: nhaehnle

Differential revision: https://reviews.llvm.org/D77544
2020-06-29 20:41:53 +05:30
Stanislav Mekhanoshin 677929e352 [AMDGPU] Process V_MOV_B32_indirect in SET_GPR_IDX optimization
Differential Revision: https://reviews.llvm.org/D80256
2020-05-19 21:37:14 -07:00
Stanislav Mekhanoshin 7d16a22eb0 [AMDGPU] Peephole adjacent equivalent S_SET_GPR_IDX_ON
Differential Revision: https://reviews.llvm.org/D79907
2020-05-14 15:44:33 -07:00
cdevadas ce984129ea [AMDGPU] Add SIPreEmitPeephole pass.
This pass can handle all the optimization
opportunities found just before code emission.
Presently it includes the handling of vcc branch
optimization that was handled earlier in SIInsertSkips.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D76712
2020-03-25 15:35:35 +00:00