d28888dd77
ARM case-insensitive checking for APSR_nzcv.
...
rdar://11056591
llvm-svn: 152846
2012-03-15 21:34:14 +00:00
d74560b170
ARM aliases for pre-unified syntax fcmpz[sd] mnemonics.
...
rdar://11056647
llvm-svn: 152834
2012-03-15 20:48:18 +00:00
ed428bc1ce
ARM more NEON VLD/VST composite physical register refactoring.
...
Register pair, all lanes subscripting.
llvm-svn: 152157
2012-03-06 23:10:38 +00:00
13a292cc74
ARM refactor more NEON VLD/VST instructions to use composite physregs
...
Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the
pseudos as a result.
llvm-svn: 152150
2012-03-06 22:01:44 +00:00
e5307f9019
ARM Refactor VLD/VST spaced pair instructions.
...
Use the new composite physical registers.
llvm-svn: 152063
2012-03-05 21:43:40 +00:00
c71bf4739a
ARM Remove a bit of dead code.
...
llvm-svn: 152061
2012-03-05 21:09:58 +00:00
c988e0c521
ARM refactor away a bunch of VLD/VST pseudo instructions.
...
With the new composite physical registers to represent arbitrary pairs
of DPR registers, we don't need the pseudo-registers anymore. Get rid of
a bunch of them that use DPR register pairs and just use the real
instructions directly instead.
llvm-svn: 152045
2012-03-05 19:33:30 +00:00
e55c556a24
Convert assert(0) to llvm_unreachable
...
llvm-svn: 149961
2012-02-07 02:50:20 +00:00
a2147ce313
Tidy up. One more return type mismatch fix.
...
llvm-svn: 149452
2012-01-31 23:51:09 +00:00
5e5eabb5ab
Keep source information, if available, around for ARM Fixups.
...
Adjust an example MachObjectWriter diagnostic to use the information
to issue a better message.
Before:
LLVM ERROR: unknown ARM fixup kind!
After:
x.s:6:5: error: unsupported relocation on symbol
beq bar
^
rdar://9800182
llvm-svn: 149093
2012-01-26 23:20:15 +00:00
c8f2b7877b
Tidy up. Fix mismatched return types for error handling.
...
llvm-svn: 149062
2012-01-26 15:56:45 +00:00
82f76d1275
ARM assemly parsing and validation of IT instruction.
...
"Although a Thumb2 instruction, the IT mnemonic shall be permitted in
ARM mode, and the condition verified to match the condition code(s)
on the following instruction(s)."
PR11853
llvm-svn: 148969
2012-01-25 19:52:01 +00:00
086cbfac7d
NEON VLD4(all lanes) assembly parsing and encoding.
...
llvm-svn: 148884
2012-01-25 00:01:08 +00:00
b78403ce48
NEON VLD3(all lanes) assembly parsing and encoding.
...
llvm-svn: 148882
2012-01-24 23:47:04 +00:00
8e2722cdb0
NEON VST4(one lane) assembly parsing and encoding.
...
llvm-svn: 148836
2012-01-24 18:53:13 +00:00
14952a0e32
NEON VLD4(one lane) assembly parsing and encoding.
...
llvm-svn: 148832
2012-01-24 18:37:25 +00:00
da70eac268
NEON VST4(multiple 4 element structures) assembly parsing.
...
llvm-svn: 148764
2012-01-24 00:58:13 +00:00
ed561fc850
NEON VLD4(multiple 4 element structures) assembly parsing.
...
llvm-svn: 148762
2012-01-24 00:43:17 +00:00
1e946a4f91
Tidy up. Remove some vertical space for readability.
...
llvm-svn: 148761
2012-01-24 00:43:12 +00:00
d3d36d9315
NEON VST3(single element from one lane) assembly parsing.
...
llvm-svn: 148755
2012-01-24 00:07:41 +00:00
1a74724fc9
NEON VST3(multiple 3-element structures) assembly parsing.
...
llvm-svn: 148748
2012-01-23 23:45:44 +00:00
ac2af3ffab
NEON VLD3(multiple 3-element structures) assembly parsing.
...
llvm-svn: 148745
2012-01-23 23:20:46 +00:00
a8b444b08b
NEON VLD3 lane-indexed assembly parsing and encoding.
...
llvm-svn: 148734
2012-01-23 21:53:26 +00:00
d28ef9ac46
Simplify some NEON assembly pseudo definitions.
...
Let the generic token alias definitions handle the data subtype
suffices. We don't need explicit versions for each.
llvm-svn: 148718
2012-01-23 19:39:08 +00:00
78dcaed8ca
Thumb2 'add rd, pc, imm' alternate form for 'adr' instruction.
...
llvm-svn: 148601
2012-01-21 00:07:56 +00:00
46a9f016c5
More dead code removal (using -Wunreachable-code)
...
llvm-svn: 148578
2012-01-20 21:51:11 +00:00
a9d36fbca7
NEON use vmov.i32 to splat some f32 values into vectors.
...
For bit patterns that aren't representable using the 8-bit floating point
representation for vmov.f32, but are representable via vmov.i32, treat
the .f32 syntax as an alias. Most importantly, this covers the case
'vmov.f32 Vd, #0.0'.
rdar://10616677
llvm-svn: 148556
2012-01-20 18:09:51 +00:00
235c8d2d94
ARM assembly diagnostic caret in better position for FPImm.
...
llvm-svn: 148459
2012-01-19 02:47:30 +00:00
94298a906a
Thumb2 alternate syntax for LDR(literal) and friends.
...
Explicit pc-relative syntax. For example, "ldrb r2, [pc, #-22]".
rdar://10250964
llvm-svn: 148432
2012-01-18 22:46:46 +00:00
486df738c3
Removing unused default switch cases in switches over enums that already account for all enumeration values explicitly.
...
(This time I believe I've checked all the -Wreturn-type warnings from GCC & added the couple of llvm_unreachables necessary to silence them. If I've missed any, I'll happily fix them as soon as I know about them)
llvm-svn: 148262
2012-01-16 23:24:27 +00:00
b982d8eb65
Fix malformed assert.
...
If anybody has strong feelings about 'default: assert(0 && "blah")' vs
'default: llvm_unreachable("blah")', feel free to regularize the instances of
each in this file.
llvm-svn: 147459
2012-01-03 19:03:59 +00:00
ea2319112f
ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point).
...
rdar://10558523
llvm-svn: 147189
2011-12-22 22:19:05 +00:00
c4d8d2f155
Tidy up. Use predicate function a bit more liberally.
...
llvm-svn: 147184
2011-12-22 22:02:35 +00:00
489ed5929e
ARM pre-UAL aliases. fcmp[sd].
...
llvm-svn: 147158
2011-12-22 19:20:45 +00:00
12ccf45bbb
ARM assembler should accept shift-by-zero for any shifted-immediate operand.
...
Just treat it as-if the shift wasn't there at all. 'as' compatibility.
rdar://10604767
llvm-svn: 147153
2011-12-22 18:04:04 +00:00
21488b8839
ARM assembly parser canonicallize on 'lsl' for shift-by-zero form.
...
llvm-svn: 147152
2011-12-22 17:37:00 +00:00
3794d82af5
Tidy up. Trailing whitespace.
...
llvm-svn: 147151
2011-12-22 17:17:10 +00:00
62bffd8827
Nuke invalid comment from copy/paste.
...
llvm-svn: 147150
2011-12-22 17:04:50 +00:00
1152cc0cad
ARM asm parser should be more lenient w/ .thumb_func directive.
...
Rather than require the symbol to be explicitly an argument of the directive,
allow it to look ahead and grab the symbol from the next non-whitespace
line.
rdar://10611140
llvm-svn: 147100
2011-12-21 22:30:16 +00:00
8c59bbc1ed
Thumb2 assembly parsing of 'mov rd, rn, rrx'.
...
Maps to the RRX instruction. Missed this case earlier.
rdar://10615373
llvm-svn: 147096
2011-12-21 21:04:19 +00:00
b3ef713e44
Thumb2 assembly parsing of 'mov(register shifted register)' aliases.
...
These map to the ASR, LSR, LSL, ROR instruction definitions.
rdar://10615373
llvm-svn: 147094
2011-12-21 20:54:00 +00:00
7de7ab83fa
ARM assembly parsing allows constant expressions for lane indices.
...
llvm-svn: 147028
2011-12-21 01:19:23 +00:00
c5af54ec89
ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback.
...
llvm-svn: 147025
2011-12-21 00:38:54 +00:00
cd22e4a81e
ARM .req register name aliases are case insensitive, just like regnames.
...
llvm-svn: 147009
2011-12-20 23:11:00 +00:00
4eda145c7f
Move comment to appropriate place.
...
llvm-svn: 147000
2011-12-20 22:26:38 +00:00
2c59052984
ARM assembly parsing and encoding for VST2 single-element, double spaced.
...
llvm-svn: 146990
2011-12-20 20:46:29 +00:00
75e2ab5db2
ARM assembly parsing and encoding for VLD2 single-element, double spaced.
...
llvm-svn: 146983
2011-12-20 19:21:26 +00:00
135d244b56
First steps in ARM AsmParser support for .eabi_attribute and .arch
...
(Both used for Linux gnueabi)
No behavioral change yet (no tests need so far)
llvm-svn: 146977
2011-12-20 17:38:12 +00:00
e2ca9e5b5f
ARM assembly shifts by zero should be plain 'mov' instructions.
...
"mov r1, r2, lsl #0" should assemble as "mov r1, r2" even though it's
not strictly legal UAL syntax. It's a common extension and the friendly
thing to do.
rdar://10604663
llvm-svn: 146937
2011-12-20 00:59:38 +00:00
045b6c71a6
ARM NEON assembly aliases for VMOV<-->VMVN for i32 immediates.
...
e.g., "vmov.i32 d4, #-118" can be assembled as "vmvn.i32 d4, #117"
rdar://10603913
llvm-svn: 146925
2011-12-19 23:51:07 +00:00
8648c10184
ARM assembly parsing and encoding support for LDRD(label).
...
rdar://9932658
llvm-svn: 146921
2011-12-19 23:06:24 +00:00
e16acacc3a
ARM VFP pre-UAL mnemonic aliases for fmul[sd].
...
llvm-svn: 146892
2011-12-19 19:43:50 +00:00
92a939ae73
ARM VFP pre-UAL mnemonic aliases for fcpy[sd] and fdiv[sd].
...
llvm-svn: 146887
2011-12-19 19:02:41 +00:00
cef98cddbe
ARM NEON relax parse time diagnostics for alignment specifiers.
...
There's more variation that we need to handle. Error checking will need
to be on operand predicates.
llvm-svn: 146884
2011-12-19 18:31:43 +00:00
c2f16a3499
Silence warning.
...
llvm-svn: 146686
2011-12-15 21:54:55 +00:00
2f50e92f40
ARM NEON two-register double spaced register list parsing support.
...
llvm-svn: 146685
2011-12-15 21:44:33 +00:00
da51104282
ARM NEON better assembly operand range checking for lane indices of VLD/VST.
...
llvm-svn: 146608
2011-12-14 23:35:06 +00:00
a8aa30b620
ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding.
...
llvm-svn: 146605
2011-12-14 23:25:46 +00:00
ab5830e51b
ARM assembler support for the target-specific .req directive.
...
rdar://10549683
llvm-svn: 146543
2011-12-14 02:16:11 +00:00
485e5622f4
Thumb2 assembler aliases for "mov(shifted register)"
...
rdar://10549767
llvm-svn: 146520
2011-12-13 22:45:11 +00:00
18bf363078
ARM LDM/STM system instruction variants.
...
rdar://10550269
llvm-svn: 146519
2011-12-13 21:48:29 +00:00
5ac89675a0
Thumb2 tweak for ccout handling in RSB parsing.
...
llvm-svn: 146516
2011-12-13 21:06:41 +00:00
1f1a3598c2
ARM thumb2 parsing of "rsb rd, rn, #0".
...
rdar://10549741
llvm-svn: 146515
2011-12-13 20:50:38 +00:00
2a2348e6c2
ARM add some more pre-UAL VFP mnemonics for convenience when porting old code.
...
llvm-svn: 146508
2011-12-13 20:13:48 +00:00
54337b8617
ARM add some more pre-UAL VFP mnemonics for convenience when porting old code.
...
llvm-svn: 146300
2011-12-10 00:01:02 +00:00
8be2f6577e
ARM add some pre-UAL VFP mnemonics for convenience when porting old code.
...
llvm-svn: 146296
2011-12-09 23:34:09 +00:00
ef70e9b704
ARM allows '' syntax, not just '#imm' for assembly.
...
Backwards compatibility with 'gas'. #imm is the preferered and documented
syntax, but lots of existing code uses the '$' prefix, so we should
support it if we can.
llvm-svn: 146285
2011-12-09 22:25:03 +00:00
8cc83fa1b7
ARM convenience aliases for VSQRT.
...
llvm-svn: 146201
2011-12-08 22:51:25 +00:00
ba7d6ed05d
ARM VSHR implied destination operand form aliases.
...
llvm-svn: 146192
2011-12-08 22:06:06 +00:00
98bc797b4d
ARM asm parser, just issue a warning for a duplicate reg in a list.
...
For better 'gas' compatibility.
llvm-svn: 146185
2011-12-08 21:34:20 +00:00
4edc7360c7
ARM assembler support for register name aliases.
...
rdar://10550084
llvm-svn: 146170
2011-12-08 19:27:38 +00:00
00326406d4
ARM NEON two-operand aliases for VSHL(immediate).
...
llvm-svn: 146125
2011-12-08 01:30:04 +00:00
9a6ba3c94e
ARM VFP support 'fmrs/fmsr' aliases for 'vldr'
...
llvm-svn: 146116
2011-12-08 00:52:55 +00:00
086d013e56
ARM VFP support 'flds/fldd' aliases for 'vldr'
...
llvm-svn: 146115
2011-12-08 00:49:29 +00:00
3050625a50
ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm".
...
llvm-svn: 146111
2011-12-08 00:31:07 +00:00
3b559ff3c5
ARM assembly, allow 'asl' as a synonym for 'lsl' in shifted-register operands.
...
For 'gas' compatibility.
llvm-svn: 146106
2011-12-07 23:40:58 +00:00
7f882399b8
ARM support the .arm and .thumb directives for assembly mode switching.
...
llvm-svn: 146042
2011-12-07 18:04:19 +00:00
d4b8249434
ARM: NEON SHLL instruction immediate operand range checking.
...
llvm-svn: 146003
2011-12-07 01:07:24 +00:00
175c7d0da5
Thumb2 encoding choice correction for PLD.
...
Using encoding T1 for offset of #0 and encoding T2 for #-0.
rdar://10532413
llvm-svn: 145919
2011-12-06 04:49:29 +00:00
b8c719ccc6
Tweak ADDrr fix. Bad check for explicit .w
...
llvm-svn: 145863
2011-12-05 22:27:04 +00:00
e489babf9b
Thumb2 prefer ADD register encoding T2 to T3 when possible.
...
rdar://10529664
llvm-svn: 145860
2011-12-05 22:16:39 +00:00
ec9ba98299
Thumb2 prefer encoding T3 to T4 for ADD/SUB immediate instructions.
...
rdar://10529348
llvm-svn: 145851
2011-12-05 21:06:26 +00:00
9dff9f4c41
ARM NEON VEXT aliases for data type suffices.
...
llvm-svn: 145726
2011-12-02 23:34:39 +00:00
eb53822f5a
ARM VST1 single lane assembly parsing.
...
llvm-svn: 145718
2011-12-02 22:34:51 +00:00
dda976b804
ARM VLD1 single lane assembly parsing.
...
llvm-svn: 145712
2011-12-02 22:01:52 +00:00
e7dcbc8691
Clean up aliases for ARM VLD1 single-lane assembly parsing a bit.
...
Add the 16-bit lane variants while I'm at it.
llvm-svn: 145693
2011-12-02 18:52:30 +00:00
04945c42c6
ARM start parsing VLD1 single lane instructions.
...
The alias pseudos need cleaned up for size suffix handling, but this gets
the basics working. Will be cleaning up and adding more.
llvm-svn: 145655
2011-12-02 00:35:16 +00:00
3ecf976ca9
ARM parsing for VLD1 two register all lanes, no writeback.
...
llvm-svn: 145504
2011-11-30 18:21:25 +00:00
cd6f5e757c
ARM parsing aliases for VLD1 single register all lanes.
...
llvm-svn: 145464
2011-11-30 01:09:44 +00:00
182b6a077e
Tidy up a bit.
...
llvm-svn: 145458
2011-11-29 23:51:09 +00:00
01e0439240
Clean up debug printing of ARM shifted operands.
...
llvm-svn: 144836
2011-11-16 21:46:50 +00:00
1a2f9ee3c8
ARM assembly parsing for RRX mnemonic.
...
rdar://9704684
llvm-svn: 144812
2011-11-16 19:05:59 +00:00
abcac56869
ARM mode aliases for bitwise instructions w/ register operands.
...
rdar://9704684
llvm-svn: 144803
2011-11-16 18:31:45 +00:00
e891fe8d6c
ARM assembly parsing for register range syntax for VLD/VST register lists.
...
For example,
vld1.f64 {d2-d5}, [r2,:128]!
Should be equivalent to:
vld1.f64 {d2,d3,d4,d5}, [r2,:128]!
It's not documented syntax in the ARM ARM, but it is consistent with what's
accepted for VLDM/VSTM and is unambiguous in meaning, so it's a good thing to
support.
rdar://10451128
llvm-svn: 144727
2011-11-15 23:19:15 +00:00
8279c1828f
ARM accept an immediate offset in memory operands w/o the '#'.
...
llvm-svn: 144709
2011-11-15 22:14:41 +00:00
8d579230c6
ARM enclosing curly braces optional on one-register VLD/VST instruction lists.
...
'vld1.f32 d4, [r7]' should be parsed as equivalent to 'vld1.f32 {d4}, [r7]'
rdar://10450488.
llvm-svn: 144701
2011-11-15 21:45:55 +00:00
a92a5d8548
Fix typo.
...
llvm-svn: 144695
2011-11-15 21:01:30 +00:00
efa7e95d06
Thumb2 two-operand 'mul' instruction wide encoding parsing.
...
rdar://10449724
llvm-svn: 144684
2011-11-15 19:55:16 +00:00
6efa7b9852
Thumb2 assembly parsing for mul.w in IT block fix.
...
When the 3rd operand is not a low-register, and the first two operands are
the same low register, the parser was incorrectly trying to use the 16-bit
instruction encoding.
rdar://10449281
llvm-svn: 144679
2011-11-15 19:29:45 +00:00
ee201faeac
Tidy up. 80 column.
...
llvm-svn: 144538
2011-11-14 17:52:47 +00:00
Jim Grosbach