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290 Commits

Author SHA1 Message Date
Chad Rosier 6f8d8b2406 [ms-inline asm] Add support for .att_syntax directive. 
llvm-svn: 163542
 2012-09-10 20:54:39 +00:00
Benjamin Kramer e3d658bb6c PR13754: llvm-mc/x86 crashes on .cfi directives without the % prefix for registers. 
gas accepts this and it seems to be common enough to be worth supporting. This
doesn't affect the parsing of reg operands outside of .cfi directives.

llvm-svn: 163390
 2012-09-07 14:51:35 +00:00
Chad Rosier a05ea0f3e3 Fix function name per coding standard. 
llvm-svn: 163187
 2012-09-05 01:15:43 +00:00
Chad Rosier 9e2aff8b6d [ms-inline asm] Asm operands can map to one or more MCOperands. Therefore, add 
the NumMCOperands argument to the GetMCInstOperandNum() function that is set
to the number of MCOperands this asm operand mapped to.

llvm-svn: 163124
 2012-09-03 20:31:23 +00:00
Chad Rosier 391d299737 [ms-inline asm] Add an interface to the GetMCInstOperandNum() function in the 
MCTargetAsmParser class.

llvm-svn: 163122
 2012-09-03 18:47:45 +00:00
Chad Rosier a353dba17d Removed unused argument. 
llvm-svn: 163104
 2012-09-03 03:16:09 +00:00
Chad Rosier e38bb6a34e [ms-inline asm] Expose the Kind and Opcode variables from the 
MatchInstructionImpl() function.

These values are used by the ConvertToMCInst() function to index into the
ConversionTable.  The values are also needed to call the GetMCInstOperandNum()
function.

llvm-svn: 163101
 2012-09-03 02:06:46 +00:00
Chad Rosier a8f3c4fe35 The ConvertToMCInst() function can't fail, so remove the now dead Match_ConversionFail enum. 
llvm-svn: 163002
 2012-08-31 16:41:07 +00:00
Chad Rosier 3b1336ceb9 Typo. 
llvm-svn: 162807
 2012-08-28 23:57:47 +00:00
Chad Rosier cf172e5e28 [ms-inline asm] Avoid a false positive assertion 
Assertion failed: (Start.isValid() == End.isValid() && "Start and end should 
either both be valid or both be invalid!")

when parsing inline asm.  SMLoc assumes that the first char * in the source is
invalid.  However, when parsing an inline asm the mnemonic is at this location.
I don't want to change SMLoc, so use a trivial workaround.

llvm-svn: 162381
 2012-08-22 19:14:29 +00:00
Chad Rosier 3d4bc62a5c [ms-inline asm] Do not report a Parser error when matching inline assembly. 
llvm-svn: 162306
 2012-08-21 19:36:59 +00:00
Chad Rosier 79e766c38e [ms-inline asm] Expose the ErrorInfo from the MatchInstructionImpl. In general, 
this is the index of the operand that failed to match.

Note: This may cause a buildbot failure due to an API mismatch in clang.  Should
recover with my next commit to clang.

llvm-svn: 162295
 2012-08-21 18:14:59 +00:00
Chad Rosier 9cb988f3aa [ms-inline asm] Extend the MC AsmParser API to match MCInsts (but not emit). 
This new API will be used by clang to parse ms-style inline asms.

One goal of this project is to use this style of inline asm for targets other
then x86.  Therefore, this API needs to be implemented for non-x86 targets at
some point in the future.

llvm-svn: 161624
 2012-08-09 22:04:55 +00:00
Craig Topper 6bf3ed454a Remove tab characters. 
llvm-svn: 160425
 2012-07-18 04:59:16 +00:00
Craig Topper 8532423268 Fix typo in error message and remove some tab characters. 
llvm-svn: 160423
 2012-07-18 04:36:35 +00:00
Craig Topper 01deb5f2df Make x86 asm parser to check for xmm vs ymm for index register in gather instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas. 
llvm-svn: 160420
 2012-07-18 04:11:12 +00:00
Chad Rosier 51afe6397b Whitespace. 
llvm-svn: 159300
 2012-06-27 22:34:28 +00:00
Manman Ren a09820414a X86: add GATHER intrinsics (AVX2) in LLVM 
Support the following intrinsics:
llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd
llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256
llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps
llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256

Modified Disassembler to handle VSIB addressing mode.

llvm-svn: 159221
 2012-06-26 19:47:59 +00:00
Craig Topper a0a603e582 Only allow symbolic names for (v)cmpss/sd/ps/pd encodings 8-31 to be used with 'v' version of instructions. 
llvm-svn: 153636
 2012-03-29 07:11:23 +00:00
Craig Topper 1fcf5bcae1 Prune some includes 
llvm-svn: 153502
 2012-03-27 07:54:11 +00:00
Kevin Enderby 1ef22f33d0 Change the X86 assembler to not require a segment register on string 
instruction's destination operand like it does for the source operand.
Also fix a typo in the comment for X86AsmParser::isSrcOp().

llvm-svn: 152654
 2012-03-13 19:47:55 +00:00
Kevin Enderby fb3110b5d2 Added a missing error check for X86 assembly with mismatched base and index 
registers not both being 64-bit or both being 32-bit registers.

llvm-svn: 152580
 2012-03-12 21:32:09 +00:00
Kevin Enderby deed5aaa41 Add the missing call to Error when a bad X86 scale expression is parsed. 
llvm-svn: 152443
 2012-03-09 22:24:10 +00:00
Kevin Enderby 6fbcd8d439 Updated the llvm-mc disassembler C API to support for the X86 target. 
rdar://10873652

As part of this I updated the llvm-mc disassembler C API to always call the
SymbolLookUp call back even if there is no getOpInfo call back.  If there is a
getOpInfo call back that is tried first and then if that gets no information
then the  SymbolLookUp is called.  I also made the code more robust by
memset(3)'ing to zero the LLVMOpInfo1 struct before then setting
SymbolicOp.Value before for the call to getOpInfo.  And also don't use any
values from the  LLVMOpInfo1 struct if getOpInfo returns 0.  And also don't
use any of the ReferenceType or ReferenceName values from SymbolLookUp if it
returns NULL. rdar://10873563 and rdar://10873683

For the X86 target also fixed bugs so the annotations get printed. 

Also fixed a few places in the ARM target that was not producing symbolic
operands for some instructions.  rdar://10878166

llvm-svn: 151267
 2012-02-23 18:18:17 +00:00
Ahmed Charles 636a3d618c Remove dead code. Improve llvm_unreachable text. Simplify some control flow. 
llvm-svn: 150918
 2012-02-19 11:37:01 +00:00
Devang Patel a173ee56fd Add assembler dialect attribute in asm parser which lets target specific asm parser change dialect on the fly. 
llvm-svn: 149396
 2012-01-31 18:14:05 +00:00
Devang Patel 7cdb2ff6b5 Intel syntax. Adjust special code, used to recognize cmp<comparison code>{ss,sd,ps,pd}, for intel syntax. 
llvm-svn: 149291
 2012-01-30 22:47:12 +00:00
Devang Patel 9a9bb5c5db Intel syntax. Support .intel_syntax directive. 
llvm-svn: 149270
 2012-01-30 20:02:42 +00:00
Devang Patel 63fe5697f4 Intel Syntax: Parse mem operand with seg reg. QWORD PTR FS:[320] 
llvm-svn: 149142
 2012-01-27 19:48:28 +00:00
Jim Grosbach 8f28dbdde5 Keep source location information for X86 MCFixup's. 
llvm-svn: 149106
 2012-01-27 00:51:27 +00:00
Devang Patel a410ed3ced Intel Syntax: Extend special hand coded logic, to recognize special instructions, for intel syntax. 
llvm-svn: 148864
 2012-01-24 21:43:36 +00:00
Devang Patel eba7d3dba9 Fix typo. 
llvm-svn: 148751
 2012-01-23 23:56:33 +00:00
Devang Patel cf893a437e Intel syntax: Robustify parsing of memory operand's displacement experssion. 
llvm-svn: 148737
 2012-01-23 22:35:25 +00:00
Devang Patel e660fdd953 Intel syntax: Parse memory operand with empty base reg, e.g. DWORD PTR [4*RDI] 
llvm-svn: 148721
 2012-01-23 20:20:06 +00:00
Devang Patel 880bc1644b Intel syntax: Parse segment registers. 
llvm-svn: 148712
 2012-01-23 18:31:58 +00:00
Benjamin Kramer 5cff13a3fb Remove unused variables. 
llvm-svn: 148635
 2012-01-21 10:42:44 +00:00
Devang Patel ce6a2ca8c8 Intel syntax: Robustify register parsing. 
llvm-svn: 148591
 2012-01-20 22:32:05 +00:00
Devang Patel d0930fff85 Intel syntax: Parse ... PTR [-8] 
llvm-svn: 148570
 2012-01-20 21:21:01 +00:00
Devang Patel f83dcfd052 Post process 'and', 'sub' instructions and select better encoding, if available. 
llvm-svn: 148489
 2012-01-19 18:40:55 +00:00
Devang Patel 2529dd9e00 Intel syntax: There is no need to create unary expr for simple negative displacement. 
llvm-svn: 148486
 2012-01-19 18:15:51 +00:00
Devang Patel 4a62ff9bcb Post process 'xor', 'or' and 'cmp' instructions and select better encoding, if available. 
llvm-svn: 148485
 2012-01-19 17:53:25 +00:00
Devang Patel de47cced25 Process instructions after match to select alternative encoding which may be more desirable. 
llvm-svn: 148431
 2012-01-18 22:42:29 +00:00
Devang Patel a7143b6a2b Intel syntax: Parse "BYTE PTR [RDX + RCX]" 
llvm-svn: 148334
 2012-01-17 21:25:10 +00:00
Devang Patel 2ed6718616 Untabify. 
llvm-svn: 148322
 2012-01-17 19:09:22 +00:00
Devang Patel 8b39be79ad Intel syntax: Do not unncessarily create plus expression for memory operand displacement. 
llvm-svn: 148321
 2012-01-17 19:08:07 +00:00
Devang Patel 41b9ddeb7a Intel syntax: Robustify memory operand parsing. 
llvm-svn: 148312
 2012-01-17 18:00:18 +00:00
Devang Patel 7066d28043 Revert r148131, it was committed before it was ready. 
llvm-svn: 148134
 2012-01-13 19:28:58 +00:00
Devang Patel 7ecdc6d4f5 Refactor. 
llvm-svn: 148131
 2012-01-13 19:12:18 +00:00
Devang Patel 4a6e778aae Rename X86ATTAsmParser -> X86AsmParser 
We are using one parser to parse att as well as intel style syntax.

llvm-svn: 148032
 2012-01-12 18:03:40 +00:00
Devang Patel fc6be102ae Add predicate method check match memory operand size, if available. 
In att style asm syntax memory operand size is derived from suffix attached with mnemonic.  In intel style asm syntax it is part of memory operand hence predicate method check is required to select appropriate instruction.

llvm-svn: 148006
 2012-01-12 01:51:42 +00:00