3b1336ceb9
Typo.
...
llvm-svn: 162807
2012-08-28 23:57:47 +00:00
407d659fa5
Add comments on the literal value used.
...
llvm-svn: 162805
2012-08-28 23:42:17 +00:00
710e1a594b
Explicitly update the number of nodes to be traversed
...
llvm-svn: 162780
2012-08-28 19:20:29 +00:00
cc56718038
The commutative flag is already correctly set within the multiclass. If we set
...
it here, then a 'register-memory' version would wrongly get the commutative
flag.
<rdar://problem/12180135>
llvm-svn: 162741
2012-08-28 07:36:46 +00:00
72f51c3986
Convert V_SETALLONES/AVX_SETALLONES/AVX2_SETALLONES to Post-RA pseudos.
...
llvm-svn: 162740
2012-08-28 07:30:47 +00:00
bd509eea4a
Merge AVX_SET0PSY/AVX_SET0PDY/AVX2_SET0 into a single post-RA pseudo.
...
llvm-svn: 162738
2012-08-28 07:05:28 +00:00
b7d85b6328
Fix PR12312
...
- Add a target-specific DAG optimization to recognize a pattern PTEST-able.
Such a pattern is a OR'd tree with X86ISD::OR as the root node. When
X86ISD::OR node has only its flag result being used as a boolean value and
all its leaves are extracted from the same vector, it could be folded into an
X86ISD::PTEST node.
llvm-svn: 162735
2012-08-28 03:34:40 +00:00
89d6b29d16
More missing mayLoad flags on AVX multiclasses.
...
llvm-svn: 162714
2012-08-28 00:02:01 +00:00
a737ef8964
Remove MMX shift intrinsic handling code that also exists in SelectionDAGBuilder.
...
llvm-svn: 162661
2012-08-27 08:08:30 +00:00
5af2fed5f2
Don't allow vextractf128 to be folded with unaligned stores. We don't fold unaligned loads so shouldn't fold unaligned stores as it can cause an alignment fault to occur.
...
llvm-svn: 162658
2012-08-27 07:19:59 +00:00
6d44554cd4
Fold some patterns into instruction definitons so tablegen can infer flags removing the need for an explicit 'neverHasSideEffects = 1'
...
llvm-svn: 162656
2012-08-27 07:04:50 +00:00
f7828f91ee
Add HasAVX1Only predicate and use it for patterns that have an AVX1 instruction and an AVX2 instruction rather than relying on AddedComplexity.
...
llvm-svn: 162654
2012-08-27 06:08:57 +00:00
228e6d4cf3
Fix integer undefined behavior due to signed left shift overflow in LLVM.
...
Reviewed offline by chandlerc.
llvm-svn: 162623
2012-08-24 23:29:28 +00:00
3d91b43ad2
Add missing mayLoad flags to a large class of AVX *_Int instructions.
...
llvm-svn: 162622
2012-08-24 23:29:07 +00:00
b50cf8b30f
Mark X86::RET and RETI instructions as variadic.
...
There is special magic happening when returning floating point values on
the x87 stack. The RET instructions get extra f80 operands.
llvm-svn: 162592
2012-08-24 20:52:44 +00:00
8ff666fcb6
Remove more mayLoad workarounds.
...
llvm-svn: 162556
2012-08-24 14:43:22 +00:00
663d160adb
Custom lower FMA intrinsics to target specific nodes and remove the patterns.
...
llvm-svn: 162534
2012-08-24 04:03:22 +00:00
d3511235d1
Remove some spurious mayLoad = 0 flags.
...
They were inserted to silence TableGen's warning about
redundant properties. That warning is now gone.
llvm-svn: 162517
2012-08-24 00:31:20 +00:00
df1faa0503
X86MemBarrier has unmodeled side effects.
...
llvm-svn: 162514
2012-08-24 00:31:10 +00:00
7030427623
Preserve operand flags in convertToThreeAddress() by copying operands.
...
No test case, this is a generalization of r160260.
llvm-svn: 162485
2012-08-23 22:36:31 +00:00
4a4634d6de
Favor FMA3 over FMA4 if both are enabled.
...
llvm-svn: 162454
2012-08-23 18:14:30 +00:00
f911597494
Use a switch statement instead of a bunch of if-else checks and pull out the common function call.
...
llvm-svn: 162428
2012-08-23 04:57:36 +00:00
cf172e5e28
[ms-inline asm] Avoid a false positive assertion
...
Assertion failed: (Start.isValid() == End.isValid() && "Start and end should
either both be valid or both be invalid!")
when parsing inline asm. SMLoc assumes that the first char * in the source is
invalid. However, when parsing an inline asm the mnemonic is at this location.
I don't want to change SMLoc, so use a trivial workaround.
llvm-svn: 162381
2012-08-22 19:14:29 +00:00
a538d831e6
Add a getName function to MachineFunction. Use it in places that previously did getFunction()->getName(). Remove includes of Function.h that are no longer needed.
...
llvm-svn: 162347
2012-08-22 06:07:19 +00:00
056dfcccb7
Don't cache the MBB in the class. Its only used by one function. Change a for loop over operands to use unsigned instead of int.
...
llvm-svn: 162344
2012-08-22 05:59:59 +00:00
455bcafa3b
Mark a function as static since it doesn't use anything in the class.
...
llvm-svn: 162342
2012-08-22 05:36:44 +00:00
13473857a7
Fix unaligned memory accesses when performing relocations in X86 JIT. There's
...
no cost to using memcpy here: the fixed code is optimized by LLVM to perfect
machine code.
llvm-svn: 162311
2012-08-21 20:48:36 +00:00
3d4bc62a5c
[ms-inline asm] Do not report a Parser error when matching inline assembly.
...
llvm-svn: 162306
2012-08-21 19:36:59 +00:00
79e766c38e
[ms-inline asm] Expose the ErrorInfo from the MatchInstructionImpl. In general,
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this is the index of the operand that failed to match.
Note: This may cause a buildbot failure due to an API mismatch in clang. Should
recover with my next commit to clang.
llvm-svn: 162295
2012-08-21 18:14:59 +00:00
bab0c76674
Fix up indentation and remove a couple else's after returns.
...
llvm-svn: 162270
2012-08-21 08:29:51 +00:00
bfcfdeb563
Use uint16_t for tables of opcodes.
...
llvm-svn: 162267
2012-08-21 08:23:21 +00:00
a0cabf19f8
Fix up indentation. No functional change.
...
llvm-svn: 162264
2012-08-21 08:17:07 +00:00
4bc3e5a1bf
Add a couple llvm_unreachables. Add a message to several others.
...
llvm-svn: 162263
2012-08-21 08:16:16 +00:00
653e759046
Replace a break with llvm_unreachable in the default case of a nested switch. Condense code a bit. No functional change.
...
llvm-svn: 162261
2012-08-21 07:32:16 +00:00
384fae2f0d
Cleanup the scalar FMA3 definitions. Add patterns to fold loads with scalar forms.
...
llvm-svn: 162260
2012-08-21 07:11:11 +00:00
4f3879dfa7
Merge FMA3 instructions with and without patterns into single classes using null_frag.
...
llvm-svn: 162257
2012-08-21 05:56:45 +00:00
10ff96ce8c
fix a case where all operands of BUILD_VECTOR are undefined
...
llvm-svn: 162214
2012-08-20 17:59:18 +00:00
b58eec4eaf
Remove FMA3 intrinsic instructions in favor of patterns.
...
llvm-svn: 162194
2012-08-20 06:21:25 +00:00
37eca54912
Use correct intrinsic for 256-bit VFMSUBADDPS.
...
llvm-svn: 162193
2012-08-20 06:03:04 +00:00
5122e9f194
Remove trailing white space and tab characters. No functional change.
...
llvm-svn: 162192
2012-08-19 23:37:46 +00:00
178250ad87
When unsafe math is used, we can use commutative FMAX and FMIN. In some cases
...
this allows for better code generation.
Added a new DAGCombine transformation to convert FMAX and FMIN to FMANC and
FMINC, which are commutative.
For example:
movaps %xmm0, %xmm1
movsd LC(%rip), %xmm0
minsd %xmm1, %xmm0
becomes:
minsd LC(%rip), %xmm0
llvm-svn: 162187
2012-08-19 13:06:16 +00:00
a136939fa9
Reapply r162160 with a fix: Optimize Arith->Trunc->SETCC sequence to allow better compare/branch code.
...
llvm-svn: 162172
2012-08-18 17:53:03 +00:00
0128f9bad7
Refactor code a bit to reduce number of calls in the final compiled code. No functional change intended.
...
llvm-svn: 162166
2012-08-18 06:39:34 +00:00
c324af609e
Revert r162160 because it made a few buildbots fail.
...
llvm-svn: 162164
2012-08-18 05:02:36 +00:00
2cb14a5c4b
The X86 backend has a number of optimizations for SETCC nodes which use
...
arithmetic instructions. However, when small data types are used, a truncate
node appears between the SETCC node and the arithmetic operation. This patch
adds support for this pattern.
Before:
xorl %esi, %edi
testb %dil, %dil
setne %al
ret
After:
xorb %dil, %sil
setne %al
ret
rdar://12081007
llvm-svn: 162160
2012-08-18 02:43:28 +00:00
31625574db
Use nested switch to select arguments to reduce calls to EmitPCMP.
...
llvm-svn: 162089
2012-08-17 07:15:56 +00:00
602e1abe0d
Make ReplaceATOMIC_BINARY_64 a static function. Use a nested switch to reduce to only a single call to it thus allowing it to be inlined by the compiler.
...
llvm-svn: 162088
2012-08-17 06:55:11 +00:00
af3e98347f
Patch to enable FMA on bdver2 target. Make XOP feature enable FMA4 as well.
...
llvm-svn: 162012
2012-08-16 04:04:02 +00:00
426feb61b9
(no commit message)
...
llvm-svn: 162010
2012-08-16 03:50:04 +00:00
06f6fe875a
minor fix of X86ISD::VSEXT_MOVL dump
...
llvm-svn: 161902
2012-08-14 22:53:17 +00:00
34107b9177
fix PR11334
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- FP_EXTEND only support extending from vectors with matching elements.
This results in the scalarization of extending to v2f64 from v2f32,
which will be legalized to v4f32 not matching with v2f64.
- add X86-specific VFPEXT supproting extending from v4f32 to v2f64.
- add BUILD_VECTOR lowering helper to recover back the original
extending from v4f32 to v2f64.
- test case is enhanced to include different vector width.
llvm-svn: 161894
2012-08-14 21:24:47 +00:00
925a281b00
Factor duplicate calls to getUNDEF in several functions.
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llvm-svn: 161860
2012-08-14 08:18:43 +00:00
d0d4b11f66
Re-factor intrinsic lowering to combine common parts of similar intrinsics. Reduces compiled code size a little bit.
...
llvm-svn: 161859
2012-08-14 07:43:25 +00:00
959acb106b
X86: move Int_CVTSD2SSrr, Int_CVTSI2SSrr, Int_CVTSI2SDrr, Int_CVTSS2SDrr from
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OpTbl1 to OpTbl2 since they have 3 operands and the last operand can be changed
to a memory operand.
PR13576
llvm-svn: 161769
2012-08-13 18:29:41 +00:00
e90e94f117
X86: when auto-detecting the subtarget features, make sure use IsIntel to detect
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Nehalem, Westmere and Sandy Bridge. AMD also has processor family 6.
llvm-svn: 161763
2012-08-13 17:26:46 +00:00
4e5eb72735
Tidy up VSETCC lowering code a bit more by adding an llvm_unreachable and putting an a couple if conditions in a better order.
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llvm-svn: 161746
2012-08-13 03:42:38 +00:00
5145a0d967
Refactor code a bit to share commonalities. No functional change intended.
...
llvm-svn: 161745
2012-08-13 02:34:03 +00:00
ff6e4d1928
Fix an unused variable warning from r161742.
...
llvm-svn: 161743
2012-08-13 01:26:45 +00:00
a7aaa62d54
Remove the LowerMMXCONCAT_VECTORS function. It could never execute because there are no legal 64-bit vector types that could be used as inputs to a 128-bit concat_vectors. Remove a target specific SDNode and its patterns that become unused as a result.
...
llvm-svn: 161742
2012-08-13 01:23:55 +00:00
3d2b271362
Remove call to setOperationAction for SETCC of v4f32. SETCC returns an integer type not an FP type.
...
llvm-svn: 161738
2012-08-12 05:31:32 +00:00
498228d089
Remove unnecessary call to setOperationAction for SETCC of v2i64 under SSE42. It was already called for the same under SSE2.
...
llvm-svn: 161737
2012-08-12 05:15:16 +00:00
10a8bf3b8c
Make replace many calls to getSizeInBits() with is128BitVector/is256BitVector
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llvm-svn: 161734
2012-08-12 02:23:29 +00:00
03d2787275
Use MVT.isXBitVector instead of EVT.isXBitVector when setting up operation actions. Compiles to smaller code.
...
llvm-svn: 161733
2012-08-12 00:34:56 +00:00
e7e828fd64
fix PR13577, an issue introduced by r161687
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- FCMOV only supports a subset of X86 conditions. Skip boolean
simplification if X86 condition is not valid for FCMOV.
- add a minimal test case for PR13577.
llvm-svn: 161732
2012-08-11 23:47:06 +00:00
b5bcf58ba1
Move setOperationAction for CONCAT_VECTORS for 256-bit vectors into loop since all 256-bit types are supported.
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llvm-svn: 161730
2012-08-11 22:34:26 +00:00
490c45c06c
Tidy up indentation. No functional change.
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llvm-svn: 161727
2012-08-11 17:53:00 +00:00
55406d9f78
Fix a cast that was casting away 'const' unnecessarily
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llvm-svn: 161726
2012-08-11 17:46:16 +00:00
22cb0c572b
Add a couple default: llvm_unreachable() to some switch statements. Fix a bad message in an existing llvm_unreachable.
...
llvm-svn: 161725
2012-08-11 17:44:14 +00:00
1acb6707cd
X86: when we are auto-detecting the subtarget features, make sure we turn on
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FeatureFastUAMem for Nehalem, Westmere and Sandy Bridge.
FeatureFastUAMem is already on if we pass in nehalem or westmere as a command
argument.
rdar: 7252306
llvm-svn: 161717
2012-08-10 23:43:32 +00:00
5248e9913f
add X86-specific DAG optimization to simplify boolean test
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- if a boolean test (X86ISD::CMP or X86ISD:SUB) checks a boolean value
generated from X86ISD::SETCC, try to simplify the boolean value
generation and checking by reusing the original EFLAGS with proper
condition code
- add hooks to X86 specific SETCC/BRCOND/CMOV, the major 3 places
consuming EFLAGS
part of patches fixing PR12312
llvm-svn: 161687
2012-08-10 19:58:13 +00:00
ea7d906b0f
remove tailing whitespaces and test commit
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llvm-svn: 161664
2012-08-10 14:39:24 +00:00
aa2f801ca3
Add some missing includes for the build against stdcxx.
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llvm-svn: 161657
2012-08-10 10:53:56 +00:00
9cb988f3aa
[ms-inline asm] Extend the MC AsmParser API to match MCInsts (but not emit).
...
This new API will be used by clang to parse ms-style inline asms.
One goal of this project is to use this style of inline asm for targets other
then x86. Therefore, this API needs to be implemented for non-x86 targets at
some point in the future.
llvm-svn: 161624
2012-08-09 22:04:55 +00:00
1be131ba27
X86: enable CSE between CMP and SUB
...
We perform the following:
1> Use SUB instead of CMP for i8,i16,i32 and i64 in ISel lowering.
2> Modify MachineCSE to correctly handle implicit defs.
3> Convert SUB back to CMP if possible at peephole.
Removed pattern matching of (a>b) ? (a-b):0 and like, since they are handled
by peephole now.
rdar://11873276
llvm-svn: 161462
2012-08-08 00:51:41 +00:00
3b9a442841
Don't scan physreg use-def chains looking for a PIC base.
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We can't rematerialize a PIC base after register allocation anyway, and
scanning physreg use-def chains is very expensive in a function with
many calls.
<rdar://problem/12047515>
llvm-svn: 161461
2012-08-08 00:40:47 +00:00
fbdd25c135
X86 cmp lowering is looking past truncate on the condition node. It should only
...
do so when the high bits are known zero. This caused a subtle miscompilation.
rdar://12027825
llvm-svn: 161451
2012-08-07 22:21:00 +00:00
e0c83b1f3b
Allow x86 subtargets to use the GenericModel defined in X86Schedule.td.
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This allows codegen passes to query properties like
InstrItins->SchedModel->IssueWidth. It also ensure's that
computeOperandLatency returns the X86 defaults for loads and "high
latency ops". This should have no significant impact on existing
schedulers because X86 defaults happen to be the same as global
defaults.
llvm-svn: 161370
2012-08-07 00:25:30 +00:00
22738d00a3
Add support for the OpenBSD for Bitrig.
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Patch by David Hill.
llvm-svn: 161344
2012-08-06 20:52:18 +00:00
ab47fe4e16
Implement proper handling for pcmpistri/pcmpestri intrinsics. Requires custom handling in DAGISelToDAG due to limitations in TableGen's implicit def handling. Fixes PR11305.
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llvm-svn: 161318
2012-08-06 06:22:36 +00:00
6d0408d3a5
Remove custom inserter for MWAIT. It doesn't do anything that couldn't be represented in a pattern.
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llvm-svn: 161306
2012-08-05 00:36:57 +00:00
43ee9fae92
Use a COPY node instead of an explicit MOVA opcode in the custom insterter for pcmpestrm/pcmpistrm. Allows the register allocator to handle it better and prevent wasted identity moves.
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llvm-svn: 161305
2012-08-05 00:17:48 +00:00
3e6fa462f3
Fall back to selection DAG isel for calls to builtin functions.
...
Fast isel doesn't currently have support for translating builtin function
calls to target instructions. For embedded environments where the library
functions are not available, this is a matter of correctness and not
just optimization. Most of this patch is just arranging to make the
TargetLibraryInfo available in fast isel. <rdar://problem/12008746>
llvm-svn: 161232
2012-08-03 04:06:28 +00:00
ba8122cc25
X86 Peephole: fold loads to the source register operand if possible.
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Add more comments and use early returns to reduce nesting in isLoadFoldable.
Also disable folding for V_SET0 to avoid introducing a const pool entry and
a const pool load.
rdar://10554090 and rdar://11873276
llvm-svn: 161207
2012-08-02 19:37:32 +00:00
5759d01230
X86 Peephole: fold loads to the source register operand if possible.
...
Machine CSE and other optimizations can remove instructions so folding
is possible at peephole while not possible at ISel.
This patch is a rework of r160919 and was tested on clang self-host on my local
machine.
rdar://10554090 and rdar://11873276
llvm-svn: 161152
2012-08-02 00:56:42 +00:00
4059145396
X86: mark GATHER instructios as mayLoad
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llvm-svn: 161143
2012-08-01 23:28:59 +00:00
24c19d20c0
Whitespace.
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llvm-svn: 161122
2012-08-01 18:39:17 +00:00
3cb3b0045c
Added FMA functionality to X86 target.
...
llvm-svn: 161110
2012-08-01 12:06:00 +00:00
b8aec08819
Add more indirection to the disassembler tables to reduce amount of space used to store the operand types and encodings. Store only the unique combinations in a separate table and store indices in the instruction table. Saves about 32K of static data.
...
llvm-svn: 161101
2012-08-01 07:39:18 +00:00
710be7df71
[x86 frame lowering] In 32-bit mode, use ESI as the base pointer.
...
Previously, we were using EBX, but PIC requires the GOT to be in EBX before
function calls via PLT GOT pointer.
llvm-svn: 161066
2012-07-31 18:29:21 +00:00
c2efce404e
Make INSTRUCTION_SPECIFIER_FIELDS match X86DisassemblerCommon.h. Also remove trailing whitespace.
...
llvm-svn: 161029
2012-07-31 05:18:26 +00:00
fb39f97d4c
Tidy up trailing whitespace
...
llvm-svn: 161027
2012-07-31 04:58:05 +00:00
5f33d90214
Tidy up trailing whitespace
...
llvm-svn: 161026
2012-07-31 04:38:27 +00:00
efd97044a3
Mark MOVZX16/MOVSX16 as neverHasSideEffects/mayLoad
...
llvm-svn: 160953
2012-07-30 07:14:07 +00:00
c6b7ef61f4
Mark MOVZX32_NOREX as isCodeGenOnly and neverHasSideEffects. The isCodeGenOnly change allows special detection of _NOREX instructions to be removed from tablegen disassembler code.
...
llvm-svn: 160951
2012-07-30 06:48:11 +00:00
14eac5dda8
Give VCVTTPD2DQ priority over CVTTPD2DQ.
...
llvm-svn: 160942
2012-07-30 02:20:32 +00:00
f881d385da
Fix patterns for CVTTPS2DQ to specify SSE2 instead of SSE1.
...
llvm-svn: 160941
2012-07-30 02:14:02 +00:00
415b3586d0
Fix up patterns for VCVTSS2SD. Specifically give it priority over SSE form. Add an OptForSpeed to explicitly pair up with an OptForSize that was already on another pattern.
...
llvm-svn: 160939
2012-07-30 01:38:57 +00:00
28402efcb6
Fix load types on intrinsic forms of SS2SD and SD2SS AVX/SSE convert instruction patterns.
...
llvm-svn: 160938
2012-07-29 23:26:34 +00:00
b6767f3acd
Move more SSE/AVX convert instruction patterns into their definitions.
...
llvm-svn: 160937
2012-07-29 22:30:06 +00:00
f87dd7c01b
Revert r160920 and r160919 due to dragonegg and clang selfhost failure
...
llvm-svn: 160927
2012-07-29 02:44:09 +00:00
Chad Rosier