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4093 Commits

Author SHA1 Message Date
Jim Grosbach 87055ed6f4 Let target asm backends see assembler flags as they go by. Use that to handle 
thumb vs. arm mode differences in WriteNopData().

llvm-svn: 121219
 2010-12-08 01:16:55 +00:00
Owen Anderson 72ce453c73 Simplify the byte reordering logic slightly. 
llvm-svn: 121216
 2010-12-08 00:21:33 +00:00
Owen Anderson 0f7142d808 VLDR fixups need special handling under Thumb. While the encoding is the same, 
the order of the bytes in the data stream is flipped around.

llvm-svn: 121215
 2010-12-08 00:18:36 +00:00
Matt Beaumont-Gay 56de7c2773 Fix a warning about a variable which is only used in an assertion. 
llvm-svn: 121206
 2010-12-07 23:26:21 +00:00
Bill Wendling f09c44c7ab Cleanup in the Darwin end. No functionality change. 
llvm-svn: 121198
 2010-12-07 23:11:00 +00:00
Evan Cheng 775ead3293 Fix a bad prologue / epilogue codegen bug where the compiler would emit illegal 
vpush instructions to save / restore VFP / NEON registers like this:
vpush {d8,d10,d11}
vpop {d8,d10,d11}

vpush and vpop do not allow gaps in the register list.
rdar://8728956

llvm-svn: 121197
 2010-12-07 23:08:38 +00:00
Bill Wendling 721724e643 A bit of cleanup: early exit ApplyFixup and cache the Fixup offset. No 
functionality change.

llvm-svn: 121195
 2010-12-07 23:05:20 +00:00
Jim Grosbach 49bcd6ff85 Binary encoding for ARM tLDRspi and tSTRspi. 
llvm-svn: 121186
 2010-12-07 21:50:47 +00:00
Owen Anderson cf096a431a Fix Thumb2 encoding of the S bit. 
llvm-svn: 121182
 2010-12-07 20:50:15 +00:00
Jim Grosbach 327cf8ee5f Refactor the ARM CMPz* patterns to just use the normal CMP instructions when 
possible. They were duplicates for everything exception the source pattern
before.

llvm-svn: 121179
 2010-12-07 20:41:06 +00:00
Evan Cheng de75ab9a09 Code clean up; no functionality change. 
llvm-svn: 121176
 2010-12-07 20:11:46 +00:00
Evan Cheng c27c956966 Code clean up; no functionality change. 
llvm-svn: 121172
 2010-12-07 19:59:34 +00:00
Jim Grosbach 6e517d658e Encode the literal field for tCMPzi instruction. 
llvm-svn: 121153
 2010-12-07 17:48:24 +00:00
Benjamin Kramer cfa9a893df Add parens to pacify gcc. 
llvm-svn: 121142
 2010-12-07 15:50:35 +00:00
Jay Foad 583abbc4df PR5207: Change APInt methods trunc(), sext(), zext(), sextOrTrunc() and 
zextOrTrunc(), and APSInt methods extend(), extOrTrunc() and new method
trunc(), to be const and to return a new value instead of modifying the
object in place.

llvm-svn: 121120
 2010-12-07 08:25:19 +00:00
Owen Anderson 99ea8a3510 Second attempt at converting Thumb2's LDRpci, including updating the gazillion places that need to know about it. 
llvm-svn: 121082
 2010-12-07 00:45:21 +00:00
Jim Grosbach 9e1994698d Add fixup for Thumb1 BL/BLX instructions. 
llvm-svn: 121072
 2010-12-06 23:57:07 +00:00
Rafael Espindola 0f30fec0bd Remove the instruction fragment to data fragment lowering since it was causing 
freed data to be read. I will open a bug to track it being reenabled.

llvm-svn: 121028
 2010-12-06 19:08:48 +00:00
Owen Anderson c1ee8e35d2 Revert r121021, which broke the buildbots. 
llvm-svn: 121026
 2010-12-06 18:57:40 +00:00
Jim Grosbach 67f13b19b5 Trailing whitespace. 
llvm-svn: 121024
 2010-12-06 18:47:44 +00:00
Owen Anderson bb4a76fc95 Improve handling of Thumb2 PC-relative loads by converting LDRpci (and friends) to Pseudos. 
llvm-svn: 121021
 2010-12-06 18:35:51 +00:00
Jim Grosbach 968c927201 Encode the register operand of ARM CondCode operands correctly. ARM::CPSR if 
the instruction is predicated, reg0 otherwise.

llvm-svn: 121020
 2010-12-06 18:30:57 +00:00
Jim Grosbach 0bfb4d5043 The ARM AsmMatcher needs to know that the CCOut operand is a register value, 
not an immediate. It stores either ARM::CPSR or reg0.

llvm-svn: 121018
 2010-12-06 18:21:12 +00:00
Evan Cheng abd6d2742a Eliminate unneeded #include's. 
llvm-svn: 120971
 2010-12-05 23:41:43 +00:00
NAKAMURA Takumi 70fbbf534b ARM/CMakeLists.txt: Add missing MLxExpansionPass.cpp since r120960. 
llvm-svn: 120966
 2010-12-05 23:08:57 +00:00
Evan Cheng 12f4d615ab Code clean up. 
llvm-svn: 120965
 2010-12-05 23:03:45 +00:00
Evan Cheng b8a662f0d1 Remove an unused variable. 
llvm-svn: 120964
 2010-12-05 23:03:35 +00:00
Evan Cheng 62c7b5bf76 Making use of VFP / NEON floating point multiply-accumulate / subtraction is 
difficult on current ARM implementations for a few reasons.
1. Even though a single vmla has latency that is one cycle shorter than a pair
   of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause
   additional pipeline stall. So it's frequently better to single codegen
   vmul + vadd.
2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to
   stall for 4 cycles. We need to schedule them apart.
3. A vmla followed vmla is a special case. Obvious issuing back to back RAW
   vmla + vmla is very bad. But this isn't ideal either:
     vmul
     vadd
     vmla
   Instead, we want to expand the second vmla:
     vmla
     vmul
     vadd
   Even with the 4 cycle vmul stall, the second sequence is still 2 cycles
   faster.

Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough
but it isn't the optimial solution. This patch attempts to make it possible to
use vmla / vmls in cases where it is profitable.

A. Add missing isel predicates which cause vmla to be codegen'ed.
B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to
   compute a fmul and a fmla.
C. Add additional isel checks for vmla, avoid cases where vmla is feeding into
   fp instructions (except for the #3 exceptional case).
D. Add ARM hazard recognizer to model the vmla / vmls hazards.
E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the
   vmla / vmls will trigger one of the special hazards.

Work in progress, only A+B are enabled.

llvm-svn: 120960
 2010-12-05 22:04:16 +00:00
Bob Wilson ed854baad5 The Thumb tADDrSPi instruction is not valid when the destination is SP. 
Check for that and try narrowing it to tADDspi instead.  Radar 8724703.

llvm-svn: 120892
 2010-12-04 04:40:19 +00:00
Jim Grosbach ce18d7ebb5 Encode condition code for Thumb1 conditional branch instruction. 
llvm-svn: 120865
 2010-12-04 00:20:40 +00:00
Jim Grosbach 5bae054f07 Correctly size-reduce the t2CMPzrr instruction to tCMPzr when possible. 
tCMPzhir has undefined behavior when both source registers are low registers.
rdar://8728577

llvm-svn: 120858
 2010-12-03 23:54:18 +00:00
Bill Wendling 127d7485f1 Use correct variable names to match the patterns. 
llvm-svn: 120857
 2010-12-03 23:44:24 +00:00
Jim Grosbach a09cbbeef5 Match pattern operand names to expected encoding field names. This corrects the 
operand encoding ordering of the instruction.

llvm-svn: 120852
 2010-12-03 23:21:25 +00:00
Jim Grosbach e4fee20498 Remove incorrect BL target encoding (it's similar to, but not the same as the 
ARM instruction). Add encoding of bits 13 and 11.

llvm-svn: 120849
 2010-12-03 22:33:42 +00:00
Jim Grosbach 567ebd0cb5 Encode the 32-bit wide Thumb (and Thumb2) instructions with the high order 
halfword being emitted to the stream first. rdar://8728174

llvm-svn: 120848
 2010-12-03 22:31:40 +00:00
Jim Grosbach ca7eaaafda When using the 'push' mnemonic for Thumb2 stmdb, be explicit when it's the 
32-bit wide version by adding the .w suffix.

llvm-svn: 120838
 2010-12-03 20:33:01 +00:00
Benjamin Kramer eaa536a773 Remove unused variable. 
llvm-svn: 120836
 2010-12-03 19:55:37 +00:00
Jim Grosbach bc6af0ce91 Reduce t2 ldr/str instructions to the correct t1 versions when there's an 
immediate offset.

llvm-svn: 120833
 2010-12-03 19:47:11 +00:00
Jason W Kim d5e6e5459f fix ARM::fixup_arm_branch, cleanup, and share more code between ELF and Darwin 
llvm-svn: 120832
 2010-12-03 19:40:23 +00:00
Jim Grosbach f799579ddd No need to declare EncoderMethod property anymore; just assign to it. 
llvm-svn: 120831
 2010-12-03 19:31:00 +00:00
Jim Grosbach 6423c29e14 Add FIXMEs. 
llvm-svn: 120824
 2010-12-03 18:37:17 +00:00
Jim Grosbach 2a862cd6e1 Size reduction for tPUSH come from t2STMDB_UPD, not t2STMIA_UPD. 
llvm-svn: 120822
 2010-12-03 18:31:03 +00:00
Bill Wendling 36110d5d1a Don't overwrite the opcode passed into the T1Special pattern. 
llvm-svn: 120782
 2010-12-03 02:02:58 +00:00
Bill Wendling 4d8ff86b9e Add Thumb encoding for some more instructions. 
llvm-svn: 120780
 2010-12-03 01:55:47 +00:00
Bill Wendling f0b36a3cfd The tLDR instruction wasn't encoded properly: 
<MCInst 2251 <MCOperand Reg:70> <MCOperand Reg:66> <MCOperand Imm:0> <MCOperand Reg:0> <MCOperand Imm:14> <MCOperand Reg:0>>

Notice that the "reg" here is 0, which is an invalid register. Put a check in
the code for this to prevent crashing.

llvm-svn: 120766
 2010-12-03 00:53:22 +00:00
Jim Grosbach dea4d78fa9 Trailing whitespace. 
llvm-svn: 120748
 2010-12-02 23:05:38 +00:00
Jim Grosbach cdae9242fa When expanding the MOVCCi32imm, make sure to use the ARM movt/movw opcodes, 
not thumb2.

llvm-svn: 120711
 2010-12-02 16:42:25 +00:00
Jim Grosbach 371e586544 Fix copy/pasto in vmin.f32 encoding. 
llvm-svn: 120709
 2010-12-02 16:30:58 +00:00
Jim Grosbach ce2bd8d05f Add support for binary encoding of ARM 'adr' instructions referencing constant 
pool entries (LEApcrel pseudo). Ongoing saga of rdar://8542291.

llvm-svn: 120635
 2010-12-02 00:28:45 +00:00
Evan Cheng 419ea286ee Fix and re-enable tail call optimization of expanded libcalls. 
llvm-svn: 120622
 2010-12-01 22:59:46 +00:00
Jason W Kim fc5c522864 fixing style nit: move class static to global static 
llvm-svn: 120619
 2010-12-01 22:46:50 +00:00
Bill Wendling 87240d4b9c Add a post encoder method to the VFP instructions to convert them to the Thumb2 
encoding if we're in that mode.

llvm-svn: 120608
 2010-12-01 21:54:50 +00:00
Jim Grosbach 30eb6c7e71 Use the correct fixup type for ARM VLDR* 
llvm-svn: 120604
 2010-12-01 21:09:40 +00:00
Jim Grosbach dc35e067c1 Refactor LEApcrelJT as a pseudo-instructionlowered to a cannonical ADR 
instruction at MC lowering. Add binary encoding information for the ADR,
including fixup data for the label operand.

llvm-svn: 120594
 2010-12-01 19:47:31 +00:00
Owen Anderson 943fb60b1f Add correct encodings for STRD and LDRD, including fixup support. Additionally, update these to unified syntax. 
llvm-svn: 120589
 2010-12-01 19:18:46 +00:00
Jason W Kim b5c9cc54d3 kill trailing space 
llvm-svn: 120586
 2010-12-01 19:07:22 +00:00
Jim Grosbach 7f5b475852 10 bits, not 12. 
llvm-svn: 120584
 2010-12-01 18:51:32 +00:00
Jim Grosbach bfbf357c74 Elaborate on FIXME. 
llvm-svn: 120552
 2010-12-01 04:01:17 +00:00
Jim Grosbach d0d1329fc8 Move the ARMAsmPrinter class defintiion into a header file. 
llvm-svn: 120551
 2010-12-01 03:45:07 +00:00
Bill Wendling 901d4d07d8 Remove "comparison of integers of different signs" warning by making the 
variable unsigned.

llvm-svn: 120541
 2010-12-01 02:49:04 +00:00
Bill Wendling cbb08ca08c General cleanups of comments. 
llvm-svn: 120536
 2010-12-01 02:42:55 +00:00
Jason W Kim 29805961d8 ARM/MC/ELF relocation "hello world" for movw/movt. 
Lifted adjustFixupValue() from Darwin for sharing w ELF.
Test added
TODO:
  refactor ELFObjectWriter::RecordRelocation more.
  Possibly share more code with Darwin?
  Lots more relocations...

llvm-svn: 120534
 2010-12-01 02:40:06 +00:00
Bill Wendling 9c25894995 Formatting. It's all the rage! 
llvm-svn: 120533
 2010-12-01 02:36:55 +00:00
Bill Wendling 8ed14ae48a More refactoring. This time the T1pI pattern. 
llvm-svn: 120532
 2010-12-01 02:28:08 +00:00
Eric Christopher 119ff7ff04 Refactor load/store handling again. Simplify and make some room for 
reg+reg handling.

llvm-svn: 120526
 2010-12-01 01:40:24 +00:00
Jan Wen Voung d602c2cc19 Initialize an ARMConstantPoolValue field. 
llvm-svn: 120525
 2010-12-01 01:38:58 +00:00
Bill Wendling c25545a1a7 s/T1pIEncode/T1pILdStEncode/g 
s/T1pIEncodeImm/T1pILdStEncodeImm/g

llvm-svn: 120524
 2010-12-01 01:38:08 +00:00
Bill Wendling 7c646b924b Renaming variables to coincide with documentation. No functionality change. 
llvm-svn: 120522
 2010-12-01 01:32:02 +00:00
Bill Wendling 490240a5d9 Refactor T1sI and T1sIt encodings into helper classes. 
llvm-svn: 120518
 2010-12-01 01:20:15 +00:00
Bill Wendling 4915f56669 Refactor the T1sIt encodings into a parent class to get rid of all of the "let" 
statements.

llvm-svn: 120512
 2010-12-01 00:48:44 +00:00
Owen Anderson 4472801765 Use by-name rather than by-order matching for NEON operands. 
llvm-svn: 120507
 2010-12-01 00:28:25 +00:00
Evan Cheng d4b0873c06 Enable sibling call optimization of libcalls which are expanded during 
legalization time. Since at legalization time there is no mapping from
SDNode back to the corresponding LLVM instruction and the return
SDNode is target specific, this requires a target hook to check for
eligibility. Only x86 and ARM support this form of sibcall optimization
right now.
rdar://8707777

llvm-svn: 120501
 2010-11-30 23:55:39 +00:00
Bill Wendling 05632cb5cc Rename operands to match ARM documentation. No functionality change. 
llvm-svn: 120500
 2010-11-30 23:54:45 +00:00
Jim Grosbach ee48d2daaa Fix typo. 
llvm-svn: 120499
 2010-11-30 23:51:41 +00:00
Jim Grosbach 38d90de7c3 Trailing whitespace. 
llvm-svn: 120497
 2010-11-30 23:29:24 +00:00
Jason W Kim c440e79126 Thanks to JimG for catching this! 
llvm-svn: 120494
 2010-11-30 23:27:18 +00:00
Bill Wendling 5c51fcda81 Inline classes that were used in only one place. 
llvm-svn: 120488
 2010-11-30 23:16:25 +00:00
Bill Wendling a9e3df7aa0 * Add support for encoding t_addrmode_s2 and t_addrmode_s1. They are the same as 
t_addrmode_s4, but with a different scaling factor.

* Encode the Thumb1 load and store instructions. This involved a bit of
  refactoring (hi, Chris! :-). Some of the patterns became dead afterwards and
  were removed.

llvm-svn: 120482
 2010-11-30 22:57:21 +00:00
Owen Anderson 8335e8fa63 Simplify the encoding of reg+/-imm12 values that allow PC-relative encoding. This allows the 
Thumb2 encoding to share code with the ARM encoding, which gets use fixup support for free.
It also allows us to fold away at least one codegen-only pattern.

llvm-svn: 120481
 2010-11-30 22:45:47 +00:00
Jim Grosbach 2d3e5c1aec Fix handling of ARM negative pc-relative fixups for loads and stores. 
llvm-svn: 120480
 2010-11-30 22:40:36 +00:00
Owen Anderson 0dc6246fc0 Provide Thumb2 encodings for a few miscellaneous instructions. 
llvm-svn: 120455
 2010-11-30 20:00:01 +00:00
Jim Grosbach 233890547d Add FIXME 
llvm-svn: 120451
 2010-11-30 19:25:56 +00:00
Owen Anderson 299382e8cb Add encoding support for Thumb2 PLD and PLI instructions. 
llvm-svn: 120449
 2010-11-30 19:19:31 +00:00
Eric Christopher 78b4efb472 Noticed this on inspection, fix and update some comments. 
llvm-svn: 120447
 2010-11-30 19:14:07 +00:00
Jim Grosbach 3b4e2ab5f3 Pseudo-ize ARM MOVPCRX 
llvm-svn: 120442
 2010-11-30 18:56:36 +00:00
Owen Anderson ebcd9c9258 Provide encodings for a few more load/store variants. 
llvm-svn: 120439
 2010-11-30 18:38:28 +00:00
Jim Grosbach cd5e30f6c6 Pseudo-ize BX_CALL and friends. Remove dead instruction format classes. 
rdar://8685712

llvm-svn: 120438
 2010-11-30 18:30:19 +00:00
Bill Wendling 811c936ed5 Add parsing for the Thumb t_addrmode_s4 addressing mode. This can almost 
certainly be made more generic. But it does allow us to parse something like:

          ldr     r3, [r2, r4]

correctly in Thumb mode.

llvm-svn: 120408
 2010-11-30 07:44:32 +00:00
Bill Wendling ddce9f3757 Minor cleanups. No functional change. 
llvm-svn: 120372
 2010-11-30 00:50:22 +00:00
Bill Wendling 8294a30d54 s/ARM::BRIND/ARM::BX/g to coincide with r120366. 
llvm-svn: 120371
 2010-11-30 00:48:15 +00:00
Bill Wendling 62718de2b9 Add correct encoding for "bl __aeabi_read_tp". However, the asm matcher isn't 
able to match this yet.

llvm-svn: 120369
 2010-11-30 00:34:08 +00:00
Jim Grosbach 027bd47e3e Rename BX/BRIND/etc patterns to clarify which is actually the BX instruction 
and which are pseudos.

llvm-svn: 120366
 2010-11-30 00:24:05 +00:00
Bill Wendling 85a8a72d85 Add some encoding for the adr instruction. Labels still need to be finished. 
llvm-svn: 120365
 2010-11-30 00:18:30 +00:00
Owen Anderson e22c7322b8 Correct Thumb2 encodings for a much wider range of loads and stores. 
llvm-svn: 120364
 2010-11-30 00:14:31 +00:00
Jim Grosbach 49408cef39 Make a few more ARM pseudo instructions actually use the PseudoInst base class. 
llvm-svn: 120362
 2010-11-30 00:09:06 +00:00
Bill Wendling ce3d6ca564 Predicate encoding should be withing {}s. And general cleanup. 
llvm-svn: 120361
 2010-11-30 00:08:20 +00:00
Bill Wendling 795f211418 Predicate encoding should be withing {}s. 
llvm-svn: 120360
 2010-11-30 00:05:25 +00:00
Bob Wilson 318ce7cb3f Fix the encoding of VLD4-dup alignment. 
The only reasonable way I could find to do this is to provide an alternate
version of the addrmode6 operand with a different encoding function.  Use it
for all the VLD-dup instructions for the sake of consistency.

llvm-svn: 120358
 2010-11-30 00:00:42 +00:00
Bob Wilson 0b27b68164 Rename VLDnDUP instructions with double-spaced registers 
in an attempt to make things a little more consistent.

llvm-svn: 120357
 2010-11-30 00:00:38 +00:00
Bob Wilson 431ac4ef50 Add support for NEON VLD3-dup instructions. 
The encoding for alignment in VLD4-dup instructions is still a work in progress.

llvm-svn: 120356
 2010-11-30 00:00:35 +00:00
Jim Grosbach 9de9a73433 Simplify definitions of the ARM eh.sjlj.*jmp pseudo instructions. 
llvm-svn: 120354
 2010-11-29 23:51:31 +00:00
Jim Grosbach 0c51bb4b25 Parameterize ARMPseudoInst size property. 
llvm-svn: 120353
 2010-11-29 23:48:41 +00:00
Jim Grosbach cb803b043b Add a few missing initializers. 
llvm-svn: 120350
 2010-11-29 23:41:10 +00:00
Jim Grosbach 32ff5586fc Nuke trailing whitespace. 
llvm-svn: 120344
 2010-11-29 23:18:01 +00:00
Jim Grosbach 9f0356b3cc Nuke a FIXME. No need to be fancier here, as ARM handles constant pools 
locations and formatting specially. rdar://7353441

llvm-svn: 120343
 2010-11-29 23:09:20 +00:00
Owen Anderson 50d662b6cb Provide Thumb2 encodings for basic loads and stores. 
llvm-svn: 120340
 2010-11-29 22:44:32 +00:00
Evan Cheng 9a133f623c Mark Darwin call instructions as using "r7" to prevent the frame-register 
assignment instructions from being moved below / above calls.
rdar://8690640

llvm-svn: 120339
 2010-11-29 22:43:27 +00:00
Jim Grosbach d5cfca1e3d Nuke dead isCodeGenOnly annotation and extraneous comment. 
llvm-svn: 120338
 2010-11-29 22:40:58 +00:00
Jim Grosbach 1883d94630 tidy up. 
llvm-svn: 120335
 2010-11-29 22:38:48 +00:00
Bill Wendling ee7c5659d7 Thumb encodings for conditional moves. 
llvm-svn: 120334
 2010-11-29 22:37:46 +00:00
Jim Grosbach 7ec3d34553 Pseudo-ize Thumb2 jump tables with explicit MC lowering to the raw 
instructions. This simplifies instruction printing and disassembly.

llvm-svn: 120333
 2010-11-29 22:37:40 +00:00
Bill Wendling 5da8cae9ec Refactor some of the "disassembly-only" instructions into a base class. This 
reduces some code duplication.

llvm-svn: 120326
 2010-11-29 22:15:03 +00:00
Eric Christopher 43b0c6d94f Update fastisel for the changes in r120272. 
llvm-svn: 120324
 2010-11-29 21:56:23 +00:00
Jim Grosbach 81af4f9eb1 Rename t2 TBB and TBH instructions to reference that they encode the jump table 
data. Next up, pseudo-izing them.

llvm-svn: 120320
 2010-11-29 21:28:32 +00:00
Owen Anderson ba3a8fa7ab Improving the factoring of several instruction encodings. 
llvm-svn: 120317
 2010-11-29 20:38:48 +00:00
Bob Wilson 77ab165afe Add support for NEON VLD3-dup instructions. 
llvm-svn: 120312
 2010-11-29 19:35:29 +00:00
Bob Wilson 8022367809 Fix copy-and-paste errors in VLD2-dup scheduling itineraries. 
llvm-svn: 120311
 2010-11-29 19:35:23 +00:00
Jim Grosbach 58bc36a3a9 ARM Pseudo-ize tBR_JTr. 
llvm-svn: 120310
 2010-11-29 19:32:47 +00:00
Owen Anderson e9608b3f01 Thumb2 encodings for MSR and MRS. 
llvm-svn: 120309
 2010-11-29 19:29:15 +00:00
Owen Anderson 2fdf32fa2c Thumb2 encodings for system instructions. 
llvm-svn: 120307
 2010-11-29 19:22:08 +00:00
Owen Anderson b044bc67f4 Thumb2 encodings for branches and IT blocks. 
llvm-svn: 120306
 2010-11-29 18:54:38 +00:00
Jim Grosbach 0591656b13 The ARM BR_JT* pseudos don't need to use the printer jtblock_operand node to 
get the pretty-printer. That's handled explicityly by the MC lowering now.

llvm-svn: 120305
 2010-11-29 18:53:24 +00:00
Michael J. Spencer ab425d8360 I swear I did a make clean and make before committing all this... 
llvm-svn: 120304
 2010-11-29 18:47:54 +00:00
Jim Grosbach 150b1ad7f8 Switch ARM BR_JTm and BR_JTr instructions to be MC-expanded pseudos. 
llvm-svn: 120303
 2010-11-29 18:37:44 +00:00
Bill Wendling 232e52cfb7 Add more Thumb encodings. 
llvm-svn: 120279
 2010-11-29 01:07:48 +00:00
Bill Wendling ccba1a8d95 More Thumb encodings. 
llvm-svn: 120278
 2010-11-29 01:00:43 +00:00
Bill Wendling 9600e97c60 Add Thumb encodings for REV instructions. 
llvm-svn: 120277
 2010-11-29 00:42:50 +00:00
Bill Wendling 775899eb2e Add more Thumb encodings. 
llvm-svn: 120272
 2010-11-29 00:18:15 +00:00
Bob Wilson 2d790df105 Add support for NEON VLD2-dup instructions. 
llvm-svn: 120236
 2010-11-28 06:51:26 +00:00
Bob Wilson 04b2c94205 Another minor refactoring for VLD1DUP instructions. 
The op11_8 field is the same for all of them so put it in the instruction
classes instead of specifying it separately for each instruction.

llvm-svn: 120234
 2010-11-28 06:51:15 +00:00
Bob Wilson 62a6f7eda6 Add entry in getTargetNodeName() for ARMISD::VBICIMM. 
llvm-svn: 120233
 2010-11-28 06:51:11 +00:00
Anton Korobeynikov 7283b8d18c Move more PEI-related hooks to TFI 
llvm-svn: 120229
 2010-11-27 23:05:25 +00:00
Anton Korobeynikov d08fbd19f5 Move callee-saved regs spills / reloads to TFI 
llvm-svn: 120228
 2010-11-27 23:05:03 +00:00
Bob Wilson d74cf2c8f6 Refactor. Set alignment bit in VLD1-dup instruction classes. 
llvm-svn: 120197
 2010-11-27 07:12:02 +00:00
Bob Wilson c92eea0175 Add NEON VLD1-dup instructions (load 1 element to all lanes). 
llvm-svn: 120194
 2010-11-27 06:35:16 +00:00
Bob Wilson 3a63f9d852 Fix incorrect scheduling itineraries for NEON vld1/vst1 instructions. 
I added these instructions recently but I have no idea where these "1"
values in the NextCycles field came from.  As far as I can tell now,
these instruction stages are clearly intended to overlap.

llvm-svn: 120193
 2010-11-27 06:35:09 +00:00
Daniel Dunbar a5f50c16f7 MC/Mach-O: Switch to using MachOFormat.h. 
- I'm leaving MachO.h, because I believe it has external consumers, but I would really like to eliminate it (we have stylistic disagreements with one another).

llvm-svn: 120187
 2010-11-27 04:38:36 +00:00
Rafael Espindola bf4a4e4ad9 Remove the unused TheTarget member. 
llvm-svn: 120168
 2010-11-26 04:24:21 +00:00
Jason W Kim 8e21bf84e8 Move the ARM reloc constants to Support/ELF.h 
llvm-svn: 120035
 2010-11-23 19:40:36 +00:00
Bob Wilson d7d2cf7842 Recognize sign/zero-extended constant BUILD_VECTORs for VMULL operations. 
We need to check if the individual vector elements are sign/zero-extended
values.  For now this only handles constants values.  Radar 8687140.

llvm-svn: 120034
 2010-11-23 19:38:38 +00:00
Wesley Peck 527da1b6e2 Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. 
llvm-svn: 119990
 2010-11-23 03:31:01 +00:00
Evan Cheng eb56dca4fd Fix epilogue codegen to avoid leaving the stack pointer in an invalid 
state. Previously Thumb2 would restore sp from fp like this:
mov sp, r7
sub, sp, #4
If an interrupt is taken after the 'mov' but before the 'sub', callee-saved
registers might be clobbered by the interrupt handler. Instead, try
restoring directly from sp:
add sp, #4
Or, if necessary (with VLA, etc.) use a scratch register to compute sp and
then restore it:
sub.w r4, r7, #8
mov sp, r7
rdar://8465407

llvm-svn: 119977
 2010-11-22 18:12:04 +00:00
Duncan Sands 5cadccc4ea Fix a compiler warning about Kind being used uninitialized 
when assertions are disabled.

llvm-svn: 119962
 2010-11-22 09:38:00 +00:00
Eric Christopher 37b0736bdc Pseudos default to 4byte size, let the instruction size field notice 
that branch tables are special.

llvm-svn: 119954
 2010-11-21 23:38:19 +00:00
Bill Wendling 22db31305f More Thumb encodings. 
llvm-svn: 119940
 2010-11-21 11:49:36 +00:00
Bill Wendling c01d679928 Add encoding for ARM "trap" instruction. 
llvm-svn: 119938
 2010-11-21 11:05:29 +00:00
Bill Wendling 219dabdf68 The "trap" instruction is one of this which doesn't have a condition code. Hack 
the code to not add a "condition code" if it's trap.

llvm-svn: 119937
 2010-11-21 10:56:05 +00:00
Bill Wendling 3acd02706a - Give "trap" the correct encoding, at least according to Darwin's assembler. 
- Add comments saying where the encodings for other instructions came from.

llvm-svn: 119936
 2010-11-21 10:55:23 +00:00
Owen Anderson 7e484e0be7 Use by-name rather than by-order operand matching for some NEON encodings. 
llvm-svn: 119923
 2010-11-21 06:47:06 +00:00
Jim Grosbach e040a46eb3 BR_JTadd is ARM-only, so use the proper pseudo class to get the predicate. 
llvm-svn: 119918
 2010-11-21 01:26:01 +00:00
Bill Wendling c31de25137 A few more thumb instruction MC encodings. 
llvm-svn: 119913
 2010-11-20 22:52:33 +00:00
Eric Christopher 0a3c28bd6b Rewrite address handling to use a structure with all the possible address 
mode variables. Handle frame indexes in load/store and allocas again.

llvm-svn: 119912
 2010-11-20 22:38:27 +00:00
Eric Christopher d0aec3bf64 STRH only needs the additional operand, not t2STRH. Also invert conditional 
to match the one from the load emitter above.

llvm-svn: 119911
 2010-11-20 22:01:38 +00:00
Anton Korobeynikov 4687778398 Move some more hooks to TargetFrameInfo 
llvm-svn: 119904
 2010-11-20 15:59:32 +00:00
Bill Wendling 284326bd69 Add more Thumb add instruction encodings. 
llvm-svn: 119883
 2010-11-20 01:18:47 +00:00
Bill Wendling fe1de03629 Add Thumb encodings for some add instructions. 
llvm-svn: 119882
 2010-11-20 01:00:29 +00:00
Bill Wendling e60fd5a9db Add more encodings for Thumb instructions. 
llvm-svn: 119881
 2010-11-20 00:53:35 +00:00
Bill Wendling 0914d44fa4 Have the getAddrMode3OpValue() function in ARMCodeEmitter.cpp produce the same 
value that the one in ARMMCCodeEmitter.cpp does.

llvm-svn: 119878
 2010-11-20 00:26:37 +00:00
Jim Grosbach 2aff392af9 Fix ARM LDR* post-indexed operand encoding. 
llvm-svn: 119869
 2010-11-19 23:14:43 +00:00
Bill Wendling 1825cc74f4 Encodings for the compare instructions. 
llvm-svn: 119868
 2010-11-19 23:14:32 +00:00
Owen Anderson b4fd2c90e9 The Vm and Vn register fields must be the same for a register-register vmov. 
llvm-svn: 119867
 2010-11-19 23:12:43 +00:00
Evan Cheng a5f048485f Fix a cut-n-paste-error. 
llvm-svn: 119866
 2010-11-19 23:01:16 +00:00
Jim Grosbach 785952e5ac Operand names 
llvm-svn: 119864
 2010-11-19 22:43:08 +00:00
Jim Grosbach 5876e41c9f trailing whitespace 
llvm-svn: 119863
 2010-11-19 22:42:55 +00:00
Eric Christopher 35e2d7f610 Don't need to save piecemeal now. 
llvm-svn: 119862
 2010-11-19 22:39:56 +00:00
Eric Christopher cee83d6e6b Update comment. 
llvm-svn: 119861
 2010-11-19 22:37:58 +00:00
Bill Wendling a82fb71324 Add encodings for some of the thumb ADD instructions. Tests will come once the 
asm parser can handle them.

llvm-svn: 119860
 2010-11-19 22:37:33 +00:00
Eric Christopher 558b61e2d4 Update comment. 
llvm-svn: 119859
 2010-11-19 22:36:41 +00:00
Jim Grosbach 7d8df3185f Clarify operand names. 
llvm-svn: 119858
 2010-11-19 22:36:02 +00:00
Eric Christopher fef5f315af Refactor address mode handling into a single struct (ala x86), this 
should give allow a wider range of addressing modes.

No functional change.

llvm-svn: 119856
 2010-11-19 22:30:02 +00:00
Jim Grosbach 48bf4f8e56 Fix encoding for ARM MLS instruction. 
llvm-svn: 119855
 2010-11-19 22:22:37 +00:00
Jim Grosbach 09d7bfd886 Add ARM encoding information for STRD. 
llvm-svn: 119852
 2010-11-19 22:14:31 +00:00
Jim Grosbach 5a77b8b5c4 Shuffle things around a bit to keep like things together. Tidy up formatting. 
llvm-svn: 119851
 2010-11-19 22:06:57 +00:00
Bill Wendling c92a5770df Revert accidental commit. 
llvm-svn: 119850
 2010-11-19 22:06:18 +00:00
Bill Wendling 49a2e2384b Change long binary encodings to use hex instead. It's more readable. Also 
initialize missing bit.

llvm-svn: 119849
 2010-11-19 22:02:18 +00:00
Jim Grosbach 6e9aace4f3 Factor out operand encoding bits for ARM addressing mode 2 store instructions. 
llvm-svn: 119846
 2010-11-19 21:35:06 +00:00
Jim Grosbach 09f6823eb6 Delete another dead class. 
llvm-svn: 119844
 2010-11-19 21:16:08 +00:00
Jim Grosbach e093e5f0dc whitespace tweak. 
llvm-svn: 119843
 2010-11-19 21:14:37 +00:00
Jim Grosbach d6e5c9f2fe Refactor PICSTR* instructions to really be pseudos. Nuke dead classes. 
llvm-svn: 119841
 2010-11-19 21:14:02 +00:00
Jim Grosbach 4a22eba616 Rename ARM .td class AIldst1 to AI2ldst for consistency with the other classes. 
llvm-svn: 119840
 2010-11-19 21:07:51 +00:00
Jim Grosbach 003c6e700b Add ARM binary encoding information for the rest of the indexed loads. 
llvm-svn: 119821
 2010-11-19 19:41:26 +00:00
Jim Grosbach c6ac246671 Remove dead code. 
llvm-svn: 119815
 2010-11-19 18:18:37 +00:00
Jim Grosbach 76aed40813 ARM LDRD binary encoding. 
llvm-svn: 119812
 2010-11-19 18:16:46 +00:00
Jim Grosbach d7a3550a5e Remove hard tabs. 
llvm-svn: 119810
 2010-11-19 18:01:37 +00:00
Jim Grosbach 2bb49e15a6 Remove trailing whitespace. 
llvm-svn: 119806
 2010-11-19 17:11:02 +00:00
Benjamin Kramer 2e49eaa92f Avoid release build warnings. 
llvm-svn: 119804
 2010-11-19 16:36:02 +00:00
Owen Anderson 336021f758 Fix decoding ambiguities of stdrex and ldrex. 
llvm-svn: 119801
 2010-11-19 13:11:50 +00:00
Evan Cheng 2debc86138 These instructions are thumb2 only. 
llvm-svn: 119793
 2010-11-19 06:28:11 +00:00
Evan Cheng 0eb2994626 Fix an obvious oversight. 
llvm-svn: 119792
 2010-11-19 06:15:10 +00:00
Bill Wendling 945b776b6e Add MC encodings for some Thumb instructions. Test for a few of them. The "bx 
lr" instruction cannot be tested just yet. It requires matching a "condition
code", but adding one of those makes things go south quickly...

llvm-svn: 119774
 2010-11-19 01:33:10 +00:00
Bill Wendling 20b5ea9858 Use array_pod_sort because the list is contiguous. 
llvm-svn: 119769
 2010-11-19 00:38:19 +00:00
Owen Anderson f53e4d9fd1 Provide Thumb2 encodings for strex and ldrex. 
llvm-svn: 119768
 2010-11-19 00:28:38 +00:00
Jim Grosbach 2aeb8b9361 Minor cleanups to a few llvm_unreachable() calls. 
llvm-svn: 119767
 2010-11-19 00:27:09 +00:00
Bill Wendling 2ecfcbd2aa An 'unreachable' shouldn't have a '0 &&' prefix. 
llvm-svn: 119762
 2010-11-19 00:05:15 +00:00
Bill Wendling 2063b84297 Add support for parsing the writeback ("!") token. 
llvm-svn: 119761
 2010-11-18 23:43:05 +00:00
Jason W Kim 5a97bd873e Fix .o emission of ARM movt/movw. MCSymbolRefExpr::VK_ARM_(HI||LO)16 for the .o path now works for ARM. 
Note: lo16AllZero remains in ARMInstrInfo.td - It can be factored out when Thumb movt is repaired.
Existing tests cover this update.

llvm-svn: 119760
 2010-11-18 23:37:15 +00:00
Owen Anderson 3517585249 Fix encodings for pkhbt, and fix some tests where I accidentally tested ARM mode instead of Thumb2. 
llvm-svn: 119755
 2010-11-18 23:29:56 +00:00
Jim Grosbach a391c97bd0 ARM Encoding information for UXTAH and friends. 
llvm-svn: 119753
 2010-11-18 23:24:22 +00:00
Tanya Lattner cd68095650 Fix bug in DAGCombiner for ARM that was trying to do a ShiftCombine on illegal types (vector should be split first). 
Added test case.

llvm-svn: 119749
 2010-11-18 22:06:46 +00:00
Bill Wendling 0ab0f67925 Don't allocate the SmallVector of Registers. It gets messy figuring out who 
should delete what when the object gets copied around. It's also making valgrind
upset.

llvm-svn: 119747
 2010-11-18 21:50:54 +00:00