a68e3a5397
Encode the multi-load/store instructions with their respective modes ('ia',
...
'db', 'ib', 'da') instead of having that mode as a separate field in the
instruction. It's more convenient for the asm parser and much more readable for
humans.
<rdar://problem/8654088>
llvm-svn: 119310
2010-11-16 01:16:36 +00:00
578c765fc8
pull the code to get the operand value out of the loop.
...
llvm-svn: 119130
2010-11-15 07:09:28 +00:00
c19d510363
split the giant encoder loop into two new helper functions.
...
llvm-svn: 119129
2010-11-15 06:59:17 +00:00
42c4ac4841
reduce nesting and minor cleanups, no functionality change.
...
llvm-svn: 119128
2010-11-15 06:42:13 +00:00
63274cbc5d
add fields to the .td files unconditionally, simplifying tblgen a bit.
...
Switch the ARM backend to use 'let' instead of 'set' with this change.
llvm-svn: 119120
2010-11-15 05:19:05 +00:00
c33f28bf90
ARM fixup encoding for direct call instructions (BL).
...
llvm-svn: 118829
2010-11-11 20:05:40 +00:00
c88ce8329c
Add support for specifying a PostEncoderMethod, which can perform post-processing after the automated encoding of an instruction.
...
Not yet used.
llvm-svn: 118759
2010-11-11 01:19:24 +00:00
f899c87343
Rename AccessesArguments and AccessesArgumentsReadonly, and rewrite
...
their comments.
llvm-svn: 118696
2010-11-10 18:30:00 +00:00
88d5f7fd95
Translate IntrReadArgMem to AccessesArgumentsReadonly.
...
llvm-svn: 118622
2010-11-09 20:07:20 +00:00
d6746d5b46
pass literals like $$1 through to the asm matcher. This isn't right yet, but doesn't hurt.
...
llvm-svn: 118359
2010-11-06 22:06:03 +00:00
4869d346e3
add (and document) the ability for alias results to have
...
fixed physical registers. Start moving fp comparison
aliases to the .td file (which default to using %st1 if
nothing is specified).
llvm-svn: 118352
2010-11-06 19:57:21 +00:00
b6f8e8248d
generalize alias support to allow the result of an alias to
...
add fixed immediate values. Move the aad and aam aliases to
use this, and document it.
llvm-svn: 118350
2010-11-06 19:25:43 +00:00
db6f90c61c
fix a bug where we had an implicit assumption that the
...
result instruction operand numbering matched the result pattern.
Fixing this allows us to move the xchg/test aliases to the .td file.
llvm-svn: 118334
2010-11-06 08:20:59 +00:00
8188fb264f
fix some bugs in the alias support, unblocking changing of "clr" aliases
...
from c++ hacks to proper .td InstAlias definitions. Change them!
llvm-svn: 118330
2010-11-06 07:31:43 +00:00
fecdad6237
Reimplement BuildResultOperands to be in terms of the result instruction's
...
operand list instead of the operand list redundantly declared on the alias
or instruction.
With this change, we finally remove the ins/outs list on the alias. Before:
def : InstAlias<(outs GR16:$dst), (ins GR8 :$src),
"movsx $src, $dst",
(MOVSX16rr8W GR16:$dst, GR8:$src)>;
After:
def : InstAlias<"movsx $src, $dst",
(MOVSX16rr8W GR16:$dst, GR8:$src)>;
This also makes the alias mechanism more general and powerful, which will
be exploited in subsequent patches.
llvm-svn: 118329
2010-11-06 07:14:44 +00:00
b625dd2d87
implement more checking to reject things like:
...
(someinst GR16:$foo, GR32:$foo)
Reimplement BuildAliasOperandReference to be correctly
based on the names of operands in the result pattern,
instead of on the instruction operand definitions.
llvm-svn: 118328
2010-11-06 07:06:09 +00:00
7603052d49
decode and validate instruction alias result definitions.
...
llvm-svn: 118327
2010-11-06 06:54:38 +00:00
23064cb4e5
simplify
...
llvm-svn: 118326
2010-11-06 06:45:08 +00:00
9f093815fa
fix another fixme, replacing a string with a semantic pointer.
...
llvm-svn: 118325
2010-11-06 06:43:11 +00:00
8ffd129950
disolve a hack, having CodeGenInstAlias decode the alias in the .td
...
file instead of the asmmatcher.
llvm-svn: 118324
2010-11-06 06:39:47 +00:00
71049f78ed
In the calling convention logic, ValVT is always a legal type,
...
and as such can be represented by an MVT - the more complicated
EVT is not needed. Use MVT for ValVT everywhere.
llvm-svn: 118245
2010-11-04 10:49:57 +00:00
4efe13d8d4
partition operand processing between aliases and instructions.
...
Right now the code is partitioned but the behavior is the same.
This should be improved in the near future. This removes some
uses of TheOperandList.
llvm-svn: 118232
2010-11-04 02:11:18 +00:00
ccde463250
pull name slicing out of BuildInstructionOperandReference so
...
it doesn't do any lexical stuff anymore.
llvm-svn: 118230
2010-11-04 01:58:23 +00:00
897a140e2a
cleanups.
...
llvm-svn: 118228
2010-11-04 01:55:23 +00:00
7108dad130
replace SrcOpNum with SrcOpName, eliminating a numering dependency
...
on the incoming operand list. This also makes the code simpler.
llvm-svn: 118225
2010-11-04 01:42:59 +00:00
4779e3e94a
strength reduce some code, resolving a fixme.
...
llvm-svn: 118219
2010-11-04 00:57:06 +00:00
743081d097
take a big step to making aliases more general and less of a hack:
...
now matchables contain an explicit list of how to populate each
operand in the result instruction instead of having them somehow
magically be correlated to the input inst.
llvm-svn: 118217
2010-11-04 00:43:46 +00:00
e4e6bf49f3
Support generating an MC'ized CodeEmitter directly. Maintain a reference to the
...
Fixups list for the instruction so the operand encoders can add to it as
needed.
llvm-svn: 118206
2010-11-03 23:38:14 +00:00
896cf04885
rename Operand -> AsmOperand for clarity.
...
llvm-svn: 118190
2010-11-03 19:47:34 +00:00
f5dda01f33
Inside the calling convention logic LocVT is always a simple
...
value type, so there is no point in passing it around using
an EVT. Use the simpler MVT everywhere. Rather than trying
to propagate this information maximally in all the code that
using the calling convention stuff, I chose to do a mainly
low impact change instead.
llvm-svn: 118167
2010-11-03 11:35:31 +00:00
c6af2b4066
Break ARM addrmode4 (load/store multiple base address) into its constituent
...
parts. Represent the operation mode as an optional operand instead.
rdar://8614429
llvm-svn: 118137
2010-11-03 01:01:43 +00:00
cc5dce89d4
Completely reject instructions that have an operand in their
...
ins/outs list that isn't specified by their asmstring. Previously
the asmmatcher would just force a 0 register into it, which clearly
isn't right. Mark a bunch of ARM instructions that use this as
isCodeGenOnly. Some of them are clearly pseudo instructions (like
t2TBB) others use a weird hasExtraSrcRegAllocReq thing that will
either need to be removed or the asmmatcher will need to be taught
about it (someday).
llvm-svn: 118119
2010-11-02 23:40:41 +00:00
4d23eb2f0e
make MatchableInfo::Validate reject instructions (like LDR_PRE in ARM)
...
that have complicated tying going on.
llvm-svn: 118112
2010-11-02 23:18:43 +00:00
e032dbfd9e
rewrite EmitConvertToMCInst to iterate over the MCInst operands,
...
filling them in one at a time. Previously this iterated over the
asmoperands, which left the problem of "holes". The new approach
simplifies things.
llvm-svn: 118104
2010-11-02 22:55:03 +00:00
5cf8a4a909
merge two large parallel loops in EmitConvertToMCInst, no change
...
in the generated .inc files.
llvm-svn: 118083
2010-11-02 21:49:44 +00:00
77d3ead281
a bunch of random cleanup, move a helper to CGT where it belongs.
...
llvm-svn: 118031
2010-11-02 18:10:06 +00:00
0b7fda23cc
Revert r114340 (improvements in Darwin function prologue/epilogue), as it broke
...
assumptions about stack layout. Specifically, LR must be saved next to FP.
llvm-svn: 118026
2010-11-02 17:35:25 +00:00
a7a903e706
add and update comments.
...
llvm-svn: 118025
2010-11-02 17:34:28 +00:00
28ea9b18cf
refactor/cleanup MatchableInfo by eliminating the Tokens array,
...
merging it into a Token field in Operand, and moving the first
token to an explicit mnemonic field. These were parallel
arrays before (except for the mnemonic) which kept confusing me.
llvm-svn: 118024
2010-11-02 17:30:52 +00:00
d64b7c0685
rename operands -> asmoperands to be more descriptive.
...
llvm-svn: 117993
2010-11-02 01:03:43 +00:00
9a33835caa
Tidy up.
...
llvm-svn: 117987
2010-11-02 00:16:39 +00:00
e3c48deff5
fix computation of ambiguous instructions to not ignore the mnemonic.
...
FWIW, X86 has 254 ambiguous instructions.
llvm-svn: 117979
2010-11-01 23:57:23 +00:00
c28e1db284
give MatchableInfo::Operand a constructor
...
llvm-svn: 117968
2010-11-01 23:08:02 +00:00
dd3b09c234
Implement enough of the missing instalias support to get
...
aliases installed and working. They now work when the
matched pattern and the result instruction have exactly
the same operand list.
This is now enough for us to define proper aliases for
movzx and movsx, implementing rdar://8017633 and PR7459.
Note that we do not accept instructions like:
movzx 0(%rsp), %rsi
GAS accepts this instruction, but it doesn't make any
sense because we don't know the size of the memory
operand. It could be 8/16/32 bits.
llvm-svn: 117901
2010-11-01 05:34:34 +00:00
ad77681253
rename InstructionInfo -> MatchableInfo since it now
...
represents InstAliases as well. Rename
isAssemblerInstruction -> Validate since that is what
it does (modulo the ARM $lane hack).
llvm-svn: 117899
2010-11-01 05:06:45 +00:00
ba465f9a8a
refactor initialization of InstructionInfo to be sharable between
...
instructions and InstAliases. Start creating InstructionInfo's
for Aliases.
llvm-svn: 117898
2010-11-01 04:53:48 +00:00
178f4bb62d
make the asm matcher emitter reject instructions that have comments
...
in their asmstring. Fix the two x86 "NOREX" instructions that have them.
If these comments are important, the instlowering stuff can print them.
llvm-svn: 117897
2010-11-01 04:44:29 +00:00
39bc53b33a
refactor InstructionInfo to not have a pointer to CodeGenInstruction
...
member, and make isAssemblerInstruction() a method (pushing some code
around inside it).
llvm-svn: 117895
2010-11-01 04:34:44 +00:00
488c201bb7
define a new CodeGenInstAlias. It has an asmstring and operand list for now,
...
todo: the result field.
llvm-svn: 117894
2010-11-01 04:05:41 +00:00
d8adec70f3
factor the operand list (and related fields/operations) out of
...
CodeGenInstruction into its own helper class. No functionality change.
llvm-svn: 117893
2010-11-01 04:03:32 +00:00
86e1c9484f
avoid needless throw/catch/rethrow, stringref'ize some simple stuff.
...
llvm-svn: 117892
2010-11-01 03:19:09 +00:00
a397716081
eliminate the old InstFormatName which is always "AsmString",
...
simplify CodeGenInstruction. No functionality change.
llvm-svn: 117891
2010-11-01 02:15:23 +00:00
517dc95d47
all predicates on an MnemonicAlias must be AssemblerPredicates.
...
llvm-svn: 117890
2010-11-01 02:09:21 +00:00
f7a01e9f46
change the singleton register handling code to be based on Record*'s
...
instead of strings, simplifying it.
llvm-svn: 117889
2010-11-01 01:47:07 +00:00
b80ab36179
Give AsmMatcherInfo a CodeGenTarget, which simplifies a bunch of
...
argument passing. Consolidate all SingletonRegister detection
and handling into a new
InstructionInfo::getSingletonRegisterForToken method instead of
having it scattered about. No change in generated .inc files.
llvm-svn: 117888
2010-11-01 01:37:30 +00:00
25d9c7fa2e
move FlattenVariants out of AsmMatcherEmitter into a shared
...
CodeGenInstruction::FlattenAsmStringVariants method. Use it
to simplify the code in AsmWriterInst, which now no longer
needs to worry about variants.
llvm-svn: 117886
2010-11-01 01:07:14 +00:00
40dd3f0939
add a FIXME, $lane in ARM is an issue that needs to be resolved before
...
this can start rejecting instructions.
llvm-svn: 117885
2010-11-01 00:51:32 +00:00
941c19b7ba
reject instructions that contain a \n in their asmstring. Mark
...
various X86 and ARM instructions that are bitten by this as isCodeGenOnly,
as they are.
llvm-svn: 117884
2010-11-01 00:46:16 +00:00
d689026899
fix a crash on:
...
let Constraints = "$val = $dst", Defs = [EFLAGS] in, isCodeGenOnly = 1 {
we now get:
X86InstrCompiler.td:653:52: error: Expected class, def, defm, multiclass or let definition
let Constraints = "$val = $dst", Defs = [EFLAGS] in, isCodeGenOnly = 1 {
^
llvm-svn: 117863
2010-10-31 19:27:15 +00:00
7ff334687d
fix the !eq operator in tblgen to return a bit instead of an int.
...
Use this to make the X86 and ARM targets set isCodeGenOnly=1
automatically for their instructions that have Format=Pseudo,
resolving a hack in tblgen.
llvm-svn: 117862
2010-10-31 19:22:57 +00:00
9492c17baf
two changes: make the asmmatcher generator ignore ARM pseudos properly,
...
and make it a hard error for instructions to not have an asm string.
These instructions should be marked isCodeGenOnly.
llvm-svn: 117861
2010-10-31 19:15:18 +00:00
33fc3e095b
reapply r117858 with apparent editor malfunction fixed (somehow I
...
got a dulicated line).
llvm-svn: 117860
2010-10-31 19:10:56 +00:00
e59eef3dd1
revert r117858 while I check out a failure I missed.
...
llvm-svn: 117859
2010-10-31 19:05:32 +00:00
9293008e90
the asm matcher can't handle operands with modifiers (like ${foo:bar}).
...
Instead of silently ignoring these instructions, emit a hard error and
force the target author to either refactor the target or mark the
instruction 'isCodeGenOnly'.
Mark a few instructions in ARM and MBlaze as isCodeGenOnly the are
doing this.
llvm-svn: 117858
2010-10-31 18:48:12 +00:00
43690071cf
have GetAliasRequiredFeatures get its features from
...
AsmMatcherInfo so we don't have two places that know the
feature -> enum mapping. No functionality change.
llvm-svn: 117845
2010-10-30 20:15:02 +00:00
a0e871901b
simplify code that creates SubtargetFeatureInfo, ensuring that features
...
that are only used by MnemonicAliases will be found.
llvm-svn: 117844
2010-10-30 20:07:57 +00:00
25896af4bb
fix a fixme in stringmatcher, having it generate nice looking code if the
...
'tomatch' code contains \n's.
llvm-svn: 117843
2010-10-30 19:57:17 +00:00
f9ec2fb34a
fix typos and some serious bugs in feature handling (but not for
...
cases that are currently exercised). Thanks to Frits van Bommel for
the great review!
llvm-svn: 117840
2010-10-30 19:47:49 +00:00
aac142cc06
Resolve a terrible hack in tblgen: instead of hardcoding
...
"In32BitMode" and "In64BitMode" into tblgen, allow any
predicate that inherits from AssemblerPredicate.
llvm-svn: 117831
2010-10-30 19:38:20 +00:00
2cb092dc55
Implement (and document!) support for MnemonicAlias's to have Requires
...
directives, allowing things like this:
def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>;
def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>;
Move the rest of the X86 MnemonicAliases over to the .td file.
llvm-svn: 117830
2010-10-30 19:23:13 +00:00
ec56397eb4
fix build problem
...
llvm-svn: 117828
2010-10-30 18:57:07 +00:00
cf9b6e3107
diagnose targets that define two alises with the same 'from' mnemonic
...
with a useful error message instead of having tblgen explode with an
assert.
llvm-svn: 117827
2010-10-30 18:56:12 +00:00
477fba4f54
emit the mnemonic aliases in their own helper function instead of
...
inline into MatchInstructionImpl.
llvm-svn: 117826
2010-10-30 18:48:18 +00:00
ba7b4fea97
implement (and document!) the first kind of MC assembler alias, which
...
just remaps one mnemonic to another. Convert a few of the X86 aliases
from .cpp to .td code.
llvm-svn: 117815
2010-10-30 17:36:36 +00:00
0eccfc2693
trailing whitespace
...
llvm-svn: 117724
2010-10-29 22:13:48 +00:00
1be0697ab9
fix the asmmatcher generator to handle targets with no RegisterPrefix
...
(like ARM) correctly. With this change, we can now match "bx lr"
because we recognize lr as a register.
llvm-svn: 117606
2010-10-28 21:28:42 +00:00
59bbc545e0
Shifter ops are not always free. Do not fold them (especially to form
...
complex load / store addressing mode) when they have higher cost and
when they have more than one use.
llvm-svn: 117509
2010-10-27 23:41:30 +00:00
fadb951e5b
Provide correct encodings for NEON vcvt, which has its own special immediate encoding
...
for specifying fractional bits for fixed point conversions.
llvm-svn: 117501
2010-10-27 22:49:00 +00:00
5e7cb5fc27
Added the x86 instruction ud2b (2nd official undefined instruction).
...
llvm-svn: 117485
2010-10-27 20:46:49 +00:00
1e4d9a17c2
First part of refactoring ARM addrmode2 (load/store) instructions to be more
...
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.
llvm-svn: 117409
2010-10-26 22:37:02 +00:00
34402c4fe4
Constify another 2 disassembler tables.
...
llvm-svn: 117208
2010-10-23 09:28:42 +00:00
de0a4fbf3b
Make the disassembler tables const so they end up in read-only memory.
...
llvm-svn: 117206
2010-10-23 09:10:44 +00:00
f4a6809231
Remove -llvmc-temp-hack from tblgen.
...
llvm-svn: 117197
2010-10-23 07:32:53 +00:00
e9b78186d4
Syntax tweak in llvmc: (something [a,b,c]) -> (something a, b, c).
...
llvm-svn: 117196
2010-10-23 07:32:46 +00:00
de68389cd3
Trailing whitespace.
...
llvm-svn: 117195
2010-10-23 07:32:37 +00:00
9192e7ab12
Make some symbols static, move classes into anonymous namespaces.
...
llvm-svn: 117111
2010-10-22 17:35:07 +00:00
83123a47ce
Add a way to emit StringSwitch of clang attribute spellings.
...
llvm-svn: 116899
2010-10-20 01:21:53 +00:00
889c1e7d80
Build with RTTI and exceptions disabled. Only in GCC for now.
...
llvm-svn: 116682
2010-10-17 02:26:16 +00:00
68a335e185
ARM mode encoding information for UBFX and SBFX instructions.
...
llvm-svn: 116588
2010-10-15 17:15:16 +00:00
7e72ec6626
Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern
...
and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.
llvm-svn: 116432
2010-10-13 21:00:04 +00:00
1e7db68774
Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions.
...
llvm-svn: 116421
2010-10-13 19:56:10 +00:00
51a12eb11d
Allow targets to optionally specify custom binary encoder functions for
...
operand values. This is useful for operands which require additional trickery
to encode into the instruction. For example, the ARM shifted immediate and
shifted register operands.
llvm-svn: 116353
2010-10-12 22:21:57 +00:00
a48349f596
Fix spelling error.
...
llvm-svn: 116282
2010-10-12 00:21:05 +00:00
e61de930bc
The assert() should reference to machine instr operand number, too.
...
llvm-svn: 116243
2010-10-11 21:41:31 +00:00
11ced671be
Make sure to use the machine instruction operand number. It doesn't always
...
map one-to-one with the CodeGenInstruction operand number.
llvm-svn: 116238
2010-10-11 21:31:22 +00:00
806b139bbc
trailing whitespace cleanup
...
llvm-svn: 116215
2010-10-11 19:38:01 +00:00
191ad7c473
When figuring out which operands match which encoding fields in an instruction,
...
try to match them by name first. If there is no by-name match, fall back to
assuming they are in order (this was the previous behavior).
llvm-svn: 116211
2010-10-11 18:25:51 +00:00
b75d0ca38e
A few 80 column cleanups
...
llvm-svn: 116069
2010-10-08 18:13:57 +00:00
2f0be8f404
trailing whitespace
...
llvm-svn: 116068
2010-10-08 18:09:59 +00:00
ba66a81017
Fix -Asserts warning.
...
llvm-svn: 116030
2010-10-08 02:07:22 +00:00
a7b6d58f45
Make <target>CodeEmitter::getBinaryCodeForInstr() a const method.
...
llvm-svn: 116018
2010-10-08 00:21:28 +00:00
33c1eb16e8
Move checking for t2MOVCCi16 to the right place.
...
llvm-svn: 115994
2010-10-07 22:14:01 +00:00
1e00173d20
Fix typo in comment.
...
llvm-svn: 115986
2010-10-07 21:55:16 +00:00
0df7ea4c24
Move tool_output_file into its own file.
...
llvm-svn: 115973
2010-10-07 20:32:40 +00:00
daab660fb1
trailing whitespace
...
llvm-svn: 115923
2010-10-07 16:56:28 +00:00
5b255c2dd6
Allow use of the 16-bit literal move instruction in CMOVs for Thumb2 mode.
...
llvm-svn: 115890
2010-10-07 00:53:56 +00:00
742adc328a
Allow use of the 16-bit literal move instruction in CMOVs for ARM mode.
...
llvm-svn: 115884
2010-10-07 00:42:42 +00:00
b270f28c1a
Now that VDUPfqf and VDUPfdfare properly pseudos, nuke the special handling.
...
llvm-svn: 115841
2010-10-06 21:17:07 +00:00
28f034c21a
Generalize tblgen's dag parsing logic to handle arbitrary expressions
...
as the operator of the dag. Specifically, this allows parsing things
like (F.x 4) in addition to just (a 4).
Unfortunately, this runs afoul of an idiom being used by llvmc. It
is using dags like (foo [1,2,3]) to represent a list of stuff being
passed into foo. With this change, this is parsed as a [1,2,3]
subscript on foo instead of being the first argument to the dag.
Cope with this in the short term by requiring a "-llvmc-temp-hack"
argument to tblgen to get the old parsing behavior.
llvm-svn: 115742
2010-10-06 04:55:48 +00:00
e76cfcf8a8
cleanups
...
llvm-svn: 115739
2010-10-06 04:31:40 +00:00
9402633637
remove the !nameconcat tblgen feature. It "shorthand" and only used in 4 places
...
where !cast is just as short.
llvm-svn: 115722
2010-10-06 00:19:21 +00:00
61ea00b494
allow !strconcat to take more than two operands to eliminate
...
!strconcat(!strconcat(!strconcat(!strconcat
Simplify some x86 td files to use it.
llvm-svn: 115719
2010-10-05 23:58:18 +00:00
b8ff8f0cb6
when david added support for #NAME# he didn't update the comments and
...
tried (but failed) to artificially constrain it to working with #NAME#.
Just allow any # in identifiers, and update the comments.
llvm-svn: 115704
2010-10-05 22:59:29 +00:00
7538ed80a9
enhance tblgen to support anonymous defm's, use this to
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simplify the X86 CMOVmr's.
llvm-svn: 115702
2010-10-05 22:51:56 +00:00
c1526595b3
trailing whitespace
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llvm-svn: 115664
2010-10-05 20:35:57 +00:00
c4abc7036d
Update attribute reading for the changed source location code.
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llvm-svn: 115624
2010-10-05 15:59:36 +00:00
9ddb678d45
Properly deserialize Clang types that are used as attribute arguments
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llvm-svn: 115616
2010-10-05 14:51:48 +00:00
8d302b2e71
Fixed the disassembler to handle two new X86
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instruction forms. Now the ENTER instruction
disassembles correctly.
llvm-svn: 115573
2010-10-04 22:45:51 +00:00
77339c7c98
Fix typo
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llvm-svn: 115348
2010-10-01 21:20:39 +00:00
dd224d2333
Massive rewrite of MMX:
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The x86_mmx type is used for MMX intrinsics, parameters and
return values where these use MMX registers, and is also
supported in load, store, and bitcast.
Only the above operations generate MMX instructions, and optimizations
do not operate on or produce MMX intrinsics.
MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into
smaller pieces. Optimizations may occur on these forms and the
result casted back to x86_mmx, provided the result feeds into a
previous existing x86_mmx operation.
The point of all this is prevent optimizations from introducing
MMX operations, which is unsafe due to the EMMS problem.
llvm-svn: 115243
2010-09-30 23:57:10 +00:00
4a57b76eea
Let a target specify whether it wants an assembly printer to be the MC version
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or not. TableGen needs to generate the printInstruction() function as taking
an MCInstr* or a MachineInstr*, depending. Default to the old non-MC
version so that everything not yet using MC continues to just work without
fidding.
llvm-svn: 115126
2010-09-30 01:29:54 +00:00
4a010fd1ea
Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMP
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pipeline forwarding path.
llvm-svn: 115098
2010-09-29 22:42:35 +00:00
a5497345ad
trailing whitespace
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llvm-svn: 115096
2010-09-29 22:32:50 +00:00
f60062fd55
add basic avx support to the disassembler, also teach it about ssmem/sdmem
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operands.
With this done, we can remove the _Int suffixes from the round instructions
without the disassembler blowing up. This allows the assembler to support
them, implementing rdar://8456376 - llvm-mc rejects 'roundss'
llvm-svn: 115019
2010-09-29 02:57:56 +00:00
0097dd0d5a
Add support to model pipeline bypass / forwarding.
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llvm-svn: 115005
2010-09-28 23:50:49 +00:00
c758311025
Push twines deeper into SourceMgr's error handling methods.
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llvm-svn: 114847
2010-09-27 17:42:11 +00:00
ded5f66813
Get rid of pop_macro warnings on MSVC.
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llvm-svn: 114750
2010-09-24 19:48:47 +00:00
2c5df619c4
Revert r114703 and r114702, removing the isConditionalMove flag from instructions. After further
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reflection, this isn't going to achieve the purpose I intended it for. Back to the drawing board!
llvm-svn: 114710
2010-09-23 23:45:25 +00:00
6e0e8d7d64
Add an TargetInstrDesc bit to indicate that a given instruction is a conditional move.
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Not intended functionality change, as nothing uses this yet.
llvm-svn: 114702
2010-09-23 22:44:10 +00:00
b4e0cc0212
Revert r114596, it's breaking a few tests.
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llvm-svn: 114659
2010-09-23 16:49:17 +00:00
e9e9c08ce2
<rdar://problem/8228022> Wvector-conversions warnings in arm_neon.h
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Explicitly cast arguments to the type the builtin expects, which is <vN x i8>
llvm-svn: 114596
2010-09-22 22:28:42 +00:00
a9e57e0eff
Rework passing parent pointers into complexpatterns, I forgot
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that complex patterns are matched after the entire pattern has
a structural match, therefore the NodeStack isn't in a useful
state when the actual call to the matcher happens.
llvm-svn: 114489
2010-09-21 22:00:25 +00:00
dd83548fea
just like they can opt into getting the root of the pattern being
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matched, allow ComplexPatterns to opt into getting the parent node
of the operand being matched.
llvm-svn: 114472
2010-09-21 20:37:12 +00:00
0e023ea02a
fix a long standing wart: all the ComplexPattern's were being
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passed the root of the match, even though only a few patterns
actually needed this (one in X86, several in ARM [which should
be refactored anyway], and some in CellSPU that I don't feel
like detangling). Instead of requiring all ComplexPatterns to
take the dead root, have targets opt into getting the root by
putting SDNPWantRoot on the ComplexPattern.
llvm-svn: 114471
2010-09-21 20:31:19 +00:00
5be6764363
Trailing whitespace, 80-col violations.
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llvm-svn: 114435
2010-09-21 14:59:50 +00:00
ed79d5f24d
llvmc: Allow multiple output languages.
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llvm-svn: 114433
2010-09-21 14:59:42 +00:00
a573d19662
Handle the odd case where we only have one instruction.
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llvm-svn: 114293
2010-09-18 18:50:27 +00:00
02d6467291
Use float64 instead of int64 vector elements for NEON vget_low and vget_high
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functions, since int64 is not a legal type and using it leads to inefficient
code. PR8036.
llvm-svn: 113919
2010-09-15 01:52:33 +00:00
86ac3fc9af
Tidy whitespace in generated arm_neon.h.
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llvm-svn: 113865
2010-09-14 21:52:34 +00:00
511dce004e
CBackend: Fix MSVC build.
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This may produce warnings on MSVS, but it's better than failures.
llvm-svn: 113834
2010-09-14 04:27:38 +00:00
3a12890338
Add x86mmx to TableGen.
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llvm-svn: 113671
2010-09-11 00:16:46 +00:00
367a5df8cf
For each instruction itinerary class, specify the number of micro-ops each
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instruction in the class would be decoded to. Or zero if the number of
uOPs must be determined dynamically.
This will be used to determine the cost-effectiveness of predicating a
micro-coded instruction.
llvm-svn: 113513
2010-09-09 18:18:55 +00:00
8ead237758
fix bugs in push/pop segment support, rdar://8407242
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llvm-svn: 113422
2010-09-08 22:13:08 +00:00
353802114f
Add an MVT::x86mmx type. It will take the place of all current MMX vector types.
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llvm-svn: 113261
2010-09-07 20:03:56 +00:00
02b701f558
Fix whitespace, because I'm OCD.
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llvm-svn: 113250
2010-09-07 18:49:14 +00:00
605acfe533
Add patterns for MMX that use the new intrinsics.
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Enable palignr intrinsic.
These may need adjustment for a new VT in due course.
llvm-svn: 113233
2010-09-07 18:10:56 +00:00
6282336772
attempt to appease msvc
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llvm-svn: 113198
2010-09-07 06:10:48 +00:00
7f3ce25e6e
fix comment typos
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llvm-svn: 113197
2010-09-07 06:06:06 +00:00
abfe4223c2
generalize my previous operand loc info hack. If the same operand
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is busted for all variants, report it as the location. This allows
us to get the operand right for bugs like:
t.s:3:12: error: invalid operand for instruction
outb %al, %gs
^
Even though there are reg/imm and reg/reg forms of this instruction.
llvm-svn: 113183
2010-09-06 23:37:39 +00:00
339cc7bfef
in the case where an instruction only has one implementation
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of a mneumonic, report operand errors with better location
info. For example, we now report:
t.s:6:14: error: invalid operand for instruction
cwtl $1
^
but we fail for common cases like:
t.s:11:4: error: invalid operand for instruction
addl $1, $1
^
because we don't know if this is supposed to be the reg/imm or imm/reg
form.
llvm-svn: 113178
2010-09-06 22:11:18 +00:00
Bill Wendling