Commit Graph

557 Commits

Author SHA1 Message Date
Bob Wilson 06fce87c4a Add codegen support for using post-increment NEON load/store instructions.
The vld1-lane, vld1-dup and vst1-lane instructions do not yet support using
post-increment versions, but all the rest of the NEON load/store instructions
should be handled now.

llvm-svn: 125014
2011-02-07 17:43:21 +00:00
Bob Wilson a609b8954e Change VLD3/4 and VST3/4 for quad registers to not update the address register.
These operations are expanded to pairs of loads or stores, and the first one
uses the address register update to produce the address for the second one.
So far, the second load/store has also updated the address register, just
for convenience, since that output has never been used.  In anticipation of
actually supporting post-increment updates for these operations, this changes
the non-updating operations to use a non-updating load/store for the second
instruction.

llvm-svn: 125013
2011-02-07 17:43:15 +00:00
Evan Cheng b8b0ad80a8 Sorry, several patches in one.
TargetInstrInfo:
Change produceSameValue() to take MachineRegisterInfo as an optional argument.
When in SSA form, targets can use it to make more aggressive equality analysis.

Machine LICM:
1. Eliminate isLoadFromConstantMemory, use MI.isInvariantLoad instead.
2. Fix a bug which prevent CSE of instructions which are not re-materializable.
3. Use improved form of produceSameValue.

ARM:
1. Teach ARM produceSameValue to look pass some PIC labels.
2. Look for operands from different loads of different constant pool entries
   which have same values.
3. Re-implement PIC GA materialization using movw + movt. Combine the pair with
   a "add pc" or "ldr [pc]" to form pseudo instructions. This makes it possible
   to re-materialize the instruction, allow machine LICM to hoist the set of
   instructions out of the loop and make it possible to CSE them. It's a bit
   hacky, but it significantly improve code quality.
4. Some minor bug fixes as well.

With the fixes, using movw + movt to materialize GAs significantly outperform the
load from constantpool method. 186.crafty and 255.vortex improved > 20%, 254.gap
and 176.gcc ~10%.

llvm-svn: 123905
2011-01-20 08:34:58 +00:00
Daniel Dunbar e0cd9ac096 ARM/ISel: Factor out isScaledConstantInRange() helper.
llvm-svn: 123823
2011-01-19 15:12:16 +00:00
Evan Cheng dfce83c8f5 Materialize GA addresses with movw + movt pairs for Darwin in PIC mode. e.g.
movw    r0, :lower16:(L_foo$non_lazy_ptr-(LPC0_0+4))
        movt    r0, :upper16:(L_foo$non_lazy_ptr-(LPC0_0+4))
LPC0_0:
        add     r0, pc, r0

It's not yet enabled by default as some tests are failing. I suspect bugs in
down stream tools.

llvm-svn: 123619
2011-01-17 08:03:18 +00:00
Anton Korobeynikov 62acecd7e1 Model operand restrictions of mul-like instructions on ARMv5 via
earlyclobber stuff. This should fix PRs 2313 and 8157.

Unfortunately, no testcase, since it'd be dependent on register
assignments.

llvm-svn: 122663
2011-01-01 20:38:38 +00:00
Andrew Trick c416ba612b whitespace
llvm-svn: 122539
2010-12-24 04:28:06 +00:00
Chris Lattner 3e5fbd74ed rename MVT::Flag to MVT::Glue. "Flag" is a terrible name for
something that just glues two nodes together, even if it is
sometimes used for flags.

llvm-svn: 122310
2010-12-21 02:38:05 +00:00
Bob Wilson 261aad8e16 Use PairDRegs to implement ConcatVectors. No functionality change.
llvm-svn: 122017
2010-12-17 01:21:08 +00:00
Jim Grosbach bfef309d11 Thumb1 had two patterns for the same load-from-constant-pool instruction.
Canonicalize on tLDRpci and remove tLDRcp.

llvm-svn: 121920
2010-12-15 23:52:36 +00:00
Bill Wendling 832a5daab5 Reapply r121808 now that the missing patterns have been supplied.
llvm-svn: 121820
2010-12-15 01:03:19 +00:00
Bill Wendling 20480d26e9 Revert r121808 until I can fix the build.
llvm-svn: 121815
2010-12-15 00:04:00 +00:00
Bill Wendling 00adcd6ed9 Make the ISel selections for LDR/STR the same as before the LDRr/LDRi split. In
particular, we want

   ldr r2, [r3]

to be equivalent to

   ldr r2, [r3, #0]

and not

   ldr r2, [r3, r0]

llvm-svn: 121808
2010-12-14 23:40:49 +00:00
Bill Wendling 092a7bdf9f The tLDR et al instructions were emitting either a reg/reg or reg/imm
instruction based on the t_addrmode_s# mode and what it returned. There is some
obvious badness to this. In particular, it's hard to do MC-encoding when the
instruction may change out from underneath you after the t_addrmode_s# variable
is finally resolved.

The solution is to revert a long-ago change that merged the reg/reg and reg/imm
versions. There is the addition of several new addressing modes. They no longer
have extraneous operands associated with them. I.e., if it's reg/reg we don't
have to have a dummy zero immediate tacked on to the SDNode.

There are some obvious cleanups here, which will happen shortly.

llvm-svn: 121747
2010-12-14 03:36:38 +00:00
Bob Wilson d29b38c893 Fix some invalid alignments for Neon vld-dup and vld/st-lane instructions.
Alignments smaller than the total size of the memory being loaded or stored,
unless the alignment is 8 bytes, are not allowed.  Add tests for this, too.

llvm-svn: 121506
2010-12-10 19:37:42 +00:00
Evan Cheng 62c7b5bf76 Making use of VFP / NEON floating point multiply-accumulate / subtraction is
difficult on current ARM implementations for a few reasons.
1. Even though a single vmla has latency that is one cycle shorter than a pair
   of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause
   additional pipeline stall. So it's frequently better to single codegen
   vmul + vadd.
2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to
   stall for 4 cycles. We need to schedule them apart.
3. A vmla followed vmla is a special case. Obvious issuing back to back RAW
   vmla + vmla is very bad. But this isn't ideal either:
     vmul
     vadd
     vmla
   Instead, we want to expand the second vmla:
     vmla
     vmul
     vadd
   Even with the 4 cycle vmul stall, the second sequence is still 2 cycles
   faster.

Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough
but it isn't the optimial solution. This patch attempts to make it possible to
use vmla / vmls in cases where it is profitable.

A. Add missing isel predicates which cause vmla to be codegen'ed.
B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to
   compute a fmul and a fmla.
C. Add additional isel checks for vmla, avoid cases where vmla is feeding into
   fp instructions (except for the #3 exceptional case).
D. Add ARM hazard recognizer to model the vmla / vmls hazards.
E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the
   vmla / vmls will trigger one of the special hazards.

Work in progress, only A+B are enabled.

llvm-svn: 120960
2010-12-05 22:04:16 +00:00
Bob Wilson 431ac4ef50 Add support for NEON VLD3-dup instructions.
The encoding for alignment in VLD4-dup instructions is still a work in progress.

llvm-svn: 120356
2010-11-30 00:00:35 +00:00
Bob Wilson 77ab165afe Add support for NEON VLD3-dup instructions.
llvm-svn: 120312
2010-11-29 19:35:29 +00:00
Bob Wilson 2d790df105 Add support for NEON VLD2-dup instructions.
llvm-svn: 120236
2010-11-28 06:51:26 +00:00
Evan Cheng a5f048485f Fix a cut-n-paste-error.
llvm-svn: 119866
2010-11-19 23:01:16 +00:00
Evan Cheng 39c81c0a55 Avoid isel movcc of large immediates when the large immediate is available in a register. These immediates aren't free.
llvm-svn: 119558
2010-11-17 20:56:30 +00:00
Evan Cheng 2bcb8daa44 Add conditional move of large immediate.
llvm-svn: 118968
2010-11-13 02:25:14 +00:00
Evan Cheng 8ce967e393 Fix an obvious typo which inverted an immediate.
llvm-svn: 118951
2010-11-13 00:27:47 +00:00
Evan Cheng 0fc8084a64 Add conditional mvn instructions.
llvm-svn: 118935
2010-11-12 22:42:47 +00:00
Duncan Sands 1462777017 Simplify uses of MVT and EVT. An MVT can be compared directly
with a SimpleValueType, while an EVT supports equality and
inequality comparisons with SimpleValueType.

llvm-svn: 118169
2010-11-03 12:17:33 +00:00
Jim Grosbach c6af2b4066 Break ARM addrmode4 (load/store multiple base address) into its constituent
parts. Represent the operation mode as an optional operand instead.
rdar://8614429

llvm-svn: 118137
2010-11-03 01:01:43 +00:00
Bob Wilson dd9fbaa9c0 Add support for alignment operands on VLD1-lane instructions.
This is another part of the fix for Radar 8599955.

llvm-svn: 117976
2010-11-01 23:40:51 +00:00
Evan Cheng 59bbc545e0 Shifter ops are not always free. Do not fold them (especially to form
complex load / store addressing mode) when they have higher cost and
when they have more than one use.

llvm-svn: 117509
2010-10-27 23:41:30 +00:00
Jim Grosbach 1e4d9a17c2 First part of refactoring ARM addrmode2 (load/store) instructions to be more
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.

llvm-svn: 117409
2010-10-26 22:37:02 +00:00
Jim Grosbach d37f0715b1 trailing whitespace
llvm-svn: 117050
2010-10-21 19:38:40 +00:00
Bob Wilson b6d61dc291 Support alignment for NEON vld-lane and vst-lane instructions.
llvm-svn: 116776
2010-10-19 00:16:32 +00:00
Jim Grosbach 5b255c2dd6 Allow use of the 16-bit literal move instruction in CMOVs for Thumb2 mode.
llvm-svn: 115890
2010-10-07 00:53:56 +00:00
Jim Grosbach 742adc328a Allow use of the 16-bit literal move instruction in CMOVs for ARM mode.
llvm-svn: 115884
2010-10-07 00:42:42 +00:00
Jim Grosbach 0860520527 Add specializations of addrmode2 that allow differentiating those forms
which require the use of the shifter-operand. This will be used to split
the ldr/str instructions such that those versions needing the shifter operand
can get a different scheduling itenerary, as in some cases, the use of the
shifter can cause different scheduling than the simpler forms.

llvm-svn: 115066
2010-09-29 19:03:54 +00:00
Jim Grosbach c7b10f3745 Add braces for legibility.
llvm-svn: 115043
2010-09-29 17:32:29 +00:00
Bob Wilson 7fbbe9a43a Set alignment operand for NEON VST instructions.
llvm-svn: 114709
2010-09-23 23:42:37 +00:00
Bob Wilson 9eeb890172 Set alignment operand for NEON VLD instructions.
llvm-svn: 114696
2010-09-23 21:43:54 +00:00
Chris Lattner 0e023ea02a fix a long standing wart: all the ComplexPattern's were being
passed the root of the match, even though only a few patterns
actually needed this (one in X86, several in ARM [which should
be refactored anyway], and some in CellSPU that I don't feel 
like detangling).   Instead of requiring all ComplexPatterns to
take the dead root, have targets opt into getting the root by
putting SDNPWantRoot on the ComplexPattern.

llvm-svn: 114471
2010-09-21 20:31:19 +00:00
Eric Christopher 726838a3e5 Fix QOpcode assignment to Opc.
llvm-svn: 113837
2010-09-14 08:31:25 +00:00
Bob Wilson c597fd3b4a Convert some VTBL and VTBX instructions to use pseudo instructions prior to
register allocation.  Remove the NEONPreAllocPass, which is no longer needed.
Yeah!!

llvm-svn: 113818
2010-09-13 23:55:10 +00:00
Bob Wilson d5c57a5ed4 Switch all the NEON vld-lane and vst-lane instructions over to the new
pseudo-instruction approach.  Change ARMExpandPseudoInsts to use a table
to record all the NEON load/store information.

llvm-svn: 113812
2010-09-13 23:01:35 +00:00
Chris Lattner f43cb302ca remove some dead code. t2addrmode_imm8s4 is never used in a
pattern, so there is no need to define a matching function.

llvm-svn: 113122
2010-09-05 22:51:11 +00:00
Bob Wilson 35fafca587 Finish converting the rest of the NEON VLD instructions to use pseudo-
instructions prior to regalloc.  Since it's getting a little close to
the 2.8 branch deadline, I'll have to leave the rest of the instructions
handled by the NEONPreAllocPass for now, but I didn't want to leave half
of the VLD instructions converted and the other half not.

llvm-svn: 112983
2010-09-03 18:16:02 +00:00
Bob Wilson 75a6408f88 Convert VLD1 and VLD2 instructions to use pseudo-instructions until
after regalloc.

llvm-svn: 112825
2010-09-02 16:00:54 +00:00
Chris Lattner 39eccb4754 temporarily revert r112664, it is causing a decoding conflict, and
the testcases should be merged.

llvm-svn: 112711
2010-09-01 16:00:50 +00:00
Bill Wendling 6789f8b6ae We have a chance for an optimization. Consider this code:
int x(int t) {
  if (t & 256)
    return -26;
  return 0;
}

We generate this:

     tst.w   r0, #256
     mvn     r0, #25
     it      eq
     moveq   r0, #0

while gcc generates this:

     ands    r0, r0, #256
     it      ne
     mvnne   r0, #25
     bx      lr

Scandalous really!

During ISel time, we can look for this particular pattern. One where we have a
"MOVCC" that uses the flag off of a CMPZ that itself is comparing an AND
instruction to 0. Something like this (greatly simplified):

  %r0 = ISD::AND ...
  ARMISD::CMPZ %r0, 0         @ sets [CPSR]
  %r0 = ARMISD::MOVCC 0, -26  @ reads [CPSR]

All we have to do is convert the "ISD::AND" into an "ARM::ANDS" that sets [CPSR]
when it's zero. The zero value will all ready be in the %r0 register and we only
need to change it if the AND wasn't zero. Easy!

llvm-svn: 112664
2010-08-31 22:41:22 +00:00
Bob Wilson 950882be07 Use pseudo instructions for VST1 and VST2.
llvm-svn: 112357
2010-08-28 05:12:57 +00:00
Bob Wilson 8ee9394750 We don't need to custom-select VLDMQ and VSTMQ anymore.
llvm-svn: 112336
2010-08-28 00:20:11 +00:00
Bob Wilson 13ce07fa92 Change ARM VFP VLDM/VSTM instructions to use addressing mode #4, just like
all the other LDM/STM instructions.  This fixes asm printer crashes when
compiling with -O0.  I've changed one of the NEON tests (vst3.ll) to run
with -O0 to check this in the future.

Prior to this change VLDM/VSTM used addressing mode #5, but not really.
The offset field was used to hold a count of the number of registers being
loaded or stored, and the AM5 opcode field was expanded to specify the IA
or DB mode, instead of the standard ADD/SUB specifier.  Much of the backend
was not aware of these special cases.  The crashes occured when rewriting
a frameindex caused the AM5 offset field to be changed so that it did not
have a valid submode.  I don't know exactly what changed to expose this now.
Maybe we've never done much with -O0 and NEON.  Regardless, there's no longer
any reason to keep a count of the VLDM/VSTM registers, so we can use
addressing mode #4 and clean things up in a lot of places.

llvm-svn: 112322
2010-08-27 23:18:17 +00:00
Bob Wilson 97919e9c59 Use pseudo instructions for VST3.
llvm-svn: 112208
2010-08-26 18:51:29 +00:00
Bob Wilson 4cec44975e Use pseudo instructions for VST1d64Q.
llvm-svn: 112170
2010-08-26 05:33:30 +00:00
Bob Wilson 9392b0e960 Start converting NEON load/stores to use pseudo instructions, beginning here
with the VST4 instructions.  Until after register allocation, we want to
represent sets of adjacent registers by a single super-register.  These
VST4 pseudo instructions have a single QQ or QQQQ source register operand.
They get expanded to the real VST4 instructions with 4 separate D register
operands.  Once this conversion is complete, we'll be able to remove the
NEONPreAllocPass and avoid some fragile and hacky code elsewhere.

llvm-svn: 112108
2010-08-25 23:27:42 +00:00
Jakob Stoklund Olesen e2cbaf6ed7 Don't call tablegen'ed Predicate_* functions in the ARM target.
llvm-svn: 111277
2010-08-17 20:39:04 +00:00
Evan Cheng 59069ec784 Add -disable-shifter-op to disable isel of shifter ops. On Cortex-a9 the shifts cost extra instructions so it might be better to emit them separately to take advantage of dual-issues.
llvm-svn: 109934
2010-07-30 23:33:54 +00:00
Bob Wilson 5bc8a79e7f Also use REG_SEQUENCE for VTBX instructions.
llvm-svn: 107743
2010-07-07 00:08:54 +00:00
Bob Wilson 3ed511bc6b Use REG_SEQUENCE nodes to make the table registers for VTBL instructions be
allocated to consecutive registers.

llvm-svn: 107730
2010-07-06 23:36:25 +00:00
Duncan Sands 78ad27ca2b Remove an unused and a pointless variable.
llvm-svn: 107131
2010-06-29 13:00:29 +00:00
Dan Gohman f1d8304fe3 Eliminate unnecessary uses of getZExtValue().
llvm-svn: 106279
2010-06-18 14:22:04 +00:00
Bob Wilson 01ac8f9fc0 Remove the hidden "neon-reg-sequence" option. The reg sequences are working
now, so there's no need to disable them.

llvm-svn: 106155
2010-06-16 21:34:01 +00:00
Bob Wilson d8a9a04739 For NEON vectors with 32- or 64-bit elements, select BUILD_VECTORs and
VECTOR_SHUFFLEs to REG_SEQUENCE instructions.  The standard ISD::BUILD_VECTOR
node corresponds closely to REG_SEQUENCE but I couldn't use it here because
its operands do not get legalized.  That is pretty awful, but I guess it
makes sense for other targets.  Instead, I have added an ARM-specific version
of BUILD_VECTOR that will have its operands properly legalized.
This fixes the rest of Radar 7872877.

llvm-svn: 105439
2010-06-04 00:04:02 +00:00
Dale Johannesen d679ff7330 Early implementation of tail call for ARM.
A temporary flag -arm-tail-calls defaults to off,
so there is no functional change by default.
Intrepid users may try this; simple cases work
but there are bugs.

llvm-svn: 105413
2010-06-03 21:09:53 +00:00
Jim Grosbach 84511e1526 Clean up 80 column violations. No functional change.
llvm-svn: 105350
2010-06-02 21:53:11 +00:00
Bob Wilson b6112e8706 Add the cc_out operand for t2RSBrs instructions. I missed this when I changed
the instruction class for t2RSB to add that operand in svn r104582.
Radar 8033757.

llvm-svn: 104907
2010-05-28 00:27:15 +00:00
Jakob Stoklund Olesen 8d042c0269 Fix a few places that depended on the numeric value of subreg indices.
Add assertions in places that depend on consecutive indices.

llvm-svn: 104510
2010-05-24 17:13:28 +00:00
Jakob Stoklund Olesen 6c47d6423c Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enums
from ARMRegisterInfo.h

llvm-svn: 104508
2010-05-24 16:54:32 +00:00
Evan Cheng e89f5ae9d4 Target instruction selection should copy memoperands.
llvm-svn: 104110
2010-05-19 06:06:09 +00:00
Evan Cheng 3d98b996ff Turn on -neon-reg-sequence by default.
Using NEON load / store multiple instructions will no longer create gobs of vmov of D registers!

llvm-svn: 103960
2010-05-17 19:51:20 +00:00
Evan Cheng 298e6b82eb Model vst lane instructions with REG_SEQUENCE.
llvm-svn: 103898
2010-05-16 03:27:48 +00:00
Evan Cheng 9e688cbcc9 Model 128-bit vld lane with REG_SEQUENCE.
llvm-svn: 103868
2010-05-15 07:53:37 +00:00
Evan Cheng 0cbd11dfb2 Model 64-bit lane vld with REG_SEQUENCE.
llvm-svn: 103851
2010-05-15 01:36:29 +00:00
Evan Cheng cb78e5558b Model VST*_UPD and VST*oddUPD pair with REG_SEQUENCE.
llvm-svn: 103833
2010-05-14 22:54:52 +00:00
Evan Cheng cfa7d02d6e Model VLD*_UPD and VLD*odd_UPD pair with REG_SEQUENCE.
llvm-svn: 103790
2010-05-14 18:54:59 +00:00
Evan Cheng ca21cc8b13 Fix comments.
llvm-svn: 103749
2010-05-14 00:21:45 +00:00
Evan Cheng e276c18385 Model some vst3 and vst4 with reg_sequence.
llvm-svn: 103453
2010-05-11 01:19:40 +00:00
Evan Cheng 630063aa0d Model some vld3 instructions with REG_SEQUENCE.
llvm-svn: 103437
2010-05-10 21:26:24 +00:00
Evan Cheng c2ae5f546f Model vld2 / vst2 with reg_sequence.
llvm-svn: 103411
2010-05-10 17:34:18 +00:00
Bob Wilson f765e1f34a Add a missing break statement to fix unintentional fall-through
(replacing the previous patch for the same issue).

llvm-svn: 103183
2010-05-06 16:05:26 +00:00
Jim Grosbach 5e3cccb1e4 Fix unintentional fallthrough. Patch by Edmund Grimley-Evans <Edmund.Grimley-Evans@arm.com>
llvm-svn: 103181
2010-05-06 15:32:49 +00:00
Evan Cheng d85631e700 Model CONCAT_VECTORS of two 64-bit values as a REG_SEQUENCE.
llvm-svn: 103104
2010-05-05 18:28:36 +00:00
Evan Cheng 8e6b40a881 With -neon-reg-sequence, models forming a Q register from a pair of consecutive D registers as a REG_SEQUENCE.
llvm-svn: 103047
2010-05-04 20:39:49 +00:00
Jim Grosbach 825cb299cd Update ARM DAGtoDAG for matching UBFX instruction for unsigned bitfield
extraction. This fixes PR5998.

llvm-svn: 102144
2010-04-22 23:24:18 +00:00
Dan Gohman 21cea8ac2e Use const qualifiers with TargetLowering. This eliminates several
const_casts, and it reinforces the design of the Target classes being
immutable.

SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.

And PIC16's AsmPrinter no longer uses TargetLowering.

llvm-svn: 101635
2010-04-17 15:26:15 +00:00
Evan Cheng 3da64f7672 Use getAL() rather than a major constant.
llvm-svn: 101446
2010-04-16 05:46:06 +00:00
Evan Cheng f7f97b4bbd Use default lowering of DYNAMIC_STACKALLOC. As far as I can tell, ARM isle is doing the right thing and codegen looks correct for both Thumb and Thumb2.
llvm-svn: 101410
2010-04-15 22:20:34 +00:00
Evan Cheng 1ba1428577 ARM SelectDYN_ALLOC should emit a copy from SP rather than referencing SP directly. In cases where there are two dyn_alloc in the same BB it would have caused the old SP value to be reused and badness ensues. rdar://7493908
llvm is generating poor code for dynamic alloca, I'll fix that later.

llvm-svn: 101383
2010-04-15 18:42:28 +00:00
Bob Wilson 59f75bba24 Fix VLDMQ and VSTMQ instructions to use the correct encoding and address modes.
These instructions are only needed for codegen, so I've removed all the
explicit encoding bits for now; they should be set in the same way as the for
VLDMD and VSTMD whenever we add encodings for VFP.  The use of addrmode5
requires that the instructions be custom-selected so that the number of
registers can be set in the AM5Opc value.

llvm-svn: 99309
2010-03-23 18:54:46 +00:00
Bob Wilson cc0a2a75a0 Change VST1 instructions for loading Q register values to operate on pairs
of D registers.  Add a separate VST1q instruction with a Q register
source operand for use by storeRegToStackSlot.

llvm-svn: 99265
2010-03-23 06:20:33 +00:00
Bob Wilson 340861d29e Change VLD1 instructions for loading Q register values to operate on pairs
of D registers.  Add a separate VLD1q instruction with a Q register
destination operand for use by loadRegFromStackSlot.

llvm-svn: 99261
2010-03-23 05:25:43 +00:00
Bob Wilson c53a1125ff Rename some VLD1/VST1 instructions to match the implementation, i.e., the
corresponding NEON instructions, instead of operation they are currently
used for.

llvm-svn: 99189
2010-03-22 18:13:18 +00:00
Bob Wilson ae08a736d6 Re-commit r98683 ("remove redundant writeback flag from ARM address mode 6")
with changes to add a separate optional register update argument.  Change all
the NEON instructions with address register writeback to use it.

llvm-svn: 99095
2010-03-20 22:13:40 +00:00
Bob Wilson c0795f8b87 Rename some instructions for consistency and sanity: use "_UPD" suffix for
load/stores with address register writeback, and use "odd" suffix to distinguish
instructions to access odd numbered registers (instead of "a" and "b").
No functional changes.

llvm-svn: 99066
2010-03-20 18:35:24 +00:00
Bob Wilson c7ba918b84 Revert 98683. It is breaking something in the disassembler.
llvm-svn: 98692
2010-03-16 23:01:13 +00:00
Bob Wilson c953bca10b Remove redundant writeback flag from ARM address mode 6. Also remove the
optional register update argument, which is currently unused -- when we add
support for that, it can just be a separate operand.

llvm-svn: 98683
2010-03-16 21:44:40 +00:00
Chris Lattner f98f124a73 Sink InstructionSelect() out of each target into SDISel, and rename it
DoInstructionSelection.  Inline "SelectRoot" into it from DAGISelHeader.
Sink some other stuff out of DAGISelHeader into SDISel.

Eliminate the various 'Indent' stuff from various targets, which dates
to when isel was recursive.

 17 files changed, 114 insertions(+), 430 deletions(-)

llvm-svn: 97555
2010-03-02 06:34:30 +00:00
Evan Cheng 5e73ff2e3a Split SelectionDAGISel::IsLegalAndProfitableToFold to
IsLegalToFold and IsProfitableToFold. The generic version of the later simply checks whether the folding candidate has a single use.

This allows the target isel routines more flexibility in deciding whether folding makes sense. The specific case we are interested in is folding constant pool loads with multiple uses.

llvm-svn: 96255
2010-02-15 19:41:07 +00:00
Chris Lattner b06015aa69 move target-independent opcodes out of TargetInstrInfo
into TargetOpcodes.h.  #include the new TargetOpcodes.h
into MachineInstr.  Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the 
codebase.

llvm-svn: 95687
2010-02-09 19:54:29 +00:00
Evan Cheng 6c0fb92c03 Fix r93758. Use isel patterns instead of c++ selection code to select rbit and make sure we pick different instructions for ARM vs. Thumb2.
llvm-svn: 93829
2010-01-19 00:44:15 +00:00
Jim Grosbach 8546ec9c14 Patch by David Conrad:
"On ARMv6T2 this turns cttz into rbit, clz instead of the 4 instruction
 sequence it is now."

llvm-svn: 93758
2010-01-18 19:58:49 +00:00
Bob Wilson 55d2ebda31 Fix an off-by-one error that caused the chain operand to be dropped from Neon
vector load-lane and store-lane instructions.

llvm-svn: 93673
2010-01-17 05:58:23 +00:00
Dan Gohman ea6f91ff64 Change SelectCode's argument from SDValue to SDNode *, to make it more
clear what information these functions are actually using.

This is also a micro-optimization, as passing a SDNode * around is
simpler than passing a { SDNode *, int } by value or reference.

llvm-svn: 92564
2010-01-05 01:24:18 +00:00
Anton Korobeynikov 2522908653 Materialize global addresses via movt/movw pair, this is always better
than doing the same via constpool:
1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2.
2. Load from constpool might stall up to 300 cycles due to cache miss.
3. Movt/movw does not use load/store unit.
4. Less constpool entries => better compiler performance.

This is only enabled on ELF systems, since darwin does not have needed
relocations (yet).

llvm-svn: 89720
2009-11-24 00:44:37 +00:00
Evan Cheng a33fc86be3 Add predicate operand to NEON instructions. Fix lots (but not all) 80 col violations in ARMInstrNEON.td.
llvm-svn: 89542
2009-11-21 06:21:52 +00:00
Evan Cheng 81a2851bcb Fix codegen of conditional move of immediates. We were not making use of the immediate forms of cmov instructions at all.
llvm-svn: 89423
2009-11-20 00:54:03 +00:00
Evan Cheng b6c7704a8d Refactor cmov selection code out to a separate function. No functionality change.
llvm-svn: 89396
2009-11-19 21:45:22 +00:00
Evan Cheng 82adca8373 80 col violation.
llvm-svn: 89337
2009-11-19 08:16:50 +00:00
Jim Grosbach d7cf55cd0e Use Unified Assembly Syntax for the ARM backend.
llvm-svn: 86494
2009-11-09 00:11:35 +00:00
Jim Grosbach d1d002a6fe Support alignment specifier for NEON vld/vst instructions
llvm-svn: 86404
2009-11-07 21:25:39 +00:00
Dan Gohman b15f4a1cbd Remove uninteresting and confusing debug output.
llvm-svn: 86149
2009-11-05 18:47:09 +00:00
Bob Wilson e90a4aa703 Prune unnecessary include.
llvm-svn: 85805
2009-11-02 16:58:31 +00:00
Johnny Chen b678a56fef Test commit. Added '.' to the comment line.
llvm-svn: 85255
2009-10-27 17:25:15 +00:00
Evan Cheng 0f55e9ce2e Don't generate sbfx / ubfx with negative lsb field. Patch by David Conrad.
llvm-svn: 84813
2009-10-22 00:40:00 +00:00
Evan Cheng 786b15fe12 Match more patterns to movt.
llvm-svn: 84751
2009-10-21 08:15:52 +00:00
Bob Wilson ad03cf02f6 Remove unused variables to fix build warning.
llvm-svn: 84144
2009-10-14 21:40:45 +00:00
Bob Wilson c350cdf3b3 Refactor code to select NEON VST intrinsics.
llvm-svn: 84122
2009-10-14 18:32:29 +00:00
Bob Wilson 12b4799787 Refactor code to select NEON VLD intrinsics.
llvm-svn: 84117
2009-10-14 17:28:52 +00:00
Bob Wilson 93117bc499 More refactoring. NEON vst lane intrinsics can share almost all the code for
vld lane intrinsics.

llvm-svn: 84110
2009-10-14 16:46:45 +00:00
Bob Wilson 4145e3ac8d Refactor code for selecting NEON load lane intrinsics.
llvm-svn: 84109
2009-10-14 16:19:03 +00:00
Bob Wilson b62d160b3c More Neon clean-up: avoid the need for custom-lowering vld/st-lane intrinsics
by creating TargetConstants during instruction selection instead of during
legalization.

llvm-svn: 84042
2009-10-13 22:29:24 +00:00
Bob Wilson 3b51560ae4 Revise ARM inline assembly memory operands to require the memory address to
be in a register.  The previous use of ARM address mode 2 was completely
arbitrary and inappropriate for Thumb.  Radar 7137468.

llvm-svn: 84022
2009-10-13 20:50:28 +00:00
Sandeep Patel 7460e0822f Fix method name in comment, per Bob Wilson.
llvm-svn: 84017
2009-10-13 20:25:58 +00:00
Sandeep Patel 423e42b371 Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov.
llvm-svn: 84009
2009-10-13 18:59:48 +00:00
Bob Wilson 84e7967fae Add codegen support for NEON vst4lane intrinsics with 128-bit vectors.
llvm-svn: 83600
2009-10-09 00:01:36 +00:00
Bob Wilson c409030838 Add codegen support for NEON vst3lane intrinsics with 128-bit vectors.
llvm-svn: 83598
2009-10-08 23:51:31 +00:00
Bob Wilson b851eb356a Add codegen support for NEON vst2lane intrinsics with 128-bit vectors.
llvm-svn: 83596
2009-10-08 23:38:24 +00:00
Bob Wilson 38ba47225a Add codegen support for NEON vld4lane intrinsics with 128-bit vectors.
Also fix some copy-and-paste errors in previous changes.

llvm-svn: 83590
2009-10-08 22:53:57 +00:00
Bob Wilson cf54e934f8 Add codegen support for NEON vld3lane intrinsics with 128-bit vectors.
llvm-svn: 83585
2009-10-08 22:27:33 +00:00
Bob Wilson c2728f44a9 Add codegen support for NEON vld2lane intrinsics with 128-bit vectors.
llvm-svn: 83568
2009-10-08 18:56:10 +00:00
Bob Wilson fac9476589 Clean up some unnecessary initializations.
llvm-svn: 83566
2009-10-08 18:52:56 +00:00
Bob Wilson 4facd965bd Clean up a comment (indentation was wrong).
llvm-svn: 83565
2009-10-08 18:51:31 +00:00
Bob Wilson b6b0ab6117 Add codegen support for NEON vst4 intrinsics with <1 x i64> vectors.
llvm-svn: 83526
2009-10-08 05:18:18 +00:00
Bob Wilson 71387b4b2f Add codegen support for NEON vst3 intrinsics with <1 x i64> vectors.
llvm-svn: 83518
2009-10-08 00:28:28 +00:00
Bob Wilson d4f5670096 Add codegen support for NEON vst2 intrinsics with <1 x i64> vectors.
llvm-svn: 83513
2009-10-08 00:21:01 +00:00
Bob Wilson 32cc4ec304 Add codegen support for NEON vld4 intrinsics with <1 x i64> vectors.
llvm-svn: 83508
2009-10-07 23:54:04 +00:00
Bob Wilson 5ef3c6d9f4 Add codegen support for NEON vld3 intrinsics with <1 x i64> vectors.
llvm-svn: 83506
2009-10-07 23:39:57 +00:00
Bob Wilson 763be1a248 Add codegen support for NEON vld2 intrinsics with <1 x i64> vectors.
llvm-svn: 83502
2009-10-07 22:57:01 +00:00
Bob Wilson e7ef4a9a6b Add codegen support for NEON vst4 intrinsics with 128-bit vectors.
llvm-svn: 83486
2009-10-07 20:49:18 +00:00
Bob Wilson 23464866ad Add codegen support for NEON vst3 intrinsics with 128-bit vectors.
llvm-svn: 83484
2009-10-07 20:30:08 +00:00
Bob Wilson 3dcb5377ef Add codegen support for NEON vst2 intrinsics with 128-bit vectors.
llvm-svn: 83482
2009-10-07 18:47:39 +00:00
Bob Wilson ab3a9474d6 Add codegen support for NEON vld4 intrinsics with 128-bit vectors.
llvm-svn: 83479
2009-10-07 18:09:32 +00:00
Bob Wilson 6bbefc2f67 Add codegen support for NEON vld3 intrinsics with 128-bit vectors.
llvm-svn: 83471
2009-10-07 17:24:55 +00:00
Bob Wilson 99e80228a9 Rearrange code for selecting vld2 intrinsics. No functionality change.
This is just to be more consistent with the forthcoming code for vld3/4.

llvm-svn: 83470
2009-10-07 17:23:09 +00:00
Bob Wilson e6b778d5ff Add codegen support for NEON vld2 operations on quad registers.
llvm-svn: 83422
2009-10-06 22:01:59 +00:00
Bob Wilson 2dd957fff6 Pass the optimization level when constructing the ARM instruction selector.
Otherwise, it is always set to "default", which prevents debug info from
even being generated during isel.  Radar 7250345.

llvm-svn: 82988
2009-09-28 14:30:20 +00:00
Anton Korobeynikov 7c2b1e71c1 Use movt/movw pair to materialize 32 bit constants on ARMv6T2+.
This should be better than single load from constpool.

llvm-svn: 82948
2009-09-27 23:52:58 +00:00
Dan Gohman 32f71d714b Rename getTargetNode to getMachineNode, for consistency with the
naming scheme used in SelectionDAG, where there are multiple kinds
of "target" nodes, but "machine" nodes are nodes which represent
a MachineInstr.

llvm-svn: 82790
2009-09-25 18:54:59 +00:00
Bob Wilson d7797754d4 Add support for generating code for vst{234}lane intrinsics.
llvm-svn: 80707
2009-09-01 18:51:56 +00:00
Bob Wilson da9817cddd Generate code for vld{234}_lane intrinsics.
llvm-svn: 80656
2009-09-01 04:26:28 +00:00
Bob Wilson e0636a7aed Remove unneeded ARM-specific DAG nodes for VLD* and VST* Neon operations.
The instructions can be selected directly from the intrinsics.  We will need
to add some ARM-specific nodes for VLD/VST of 3 and 4 128-bit vectors, but
those are not yet implemented.

llvm-svn: 80117
2009-08-26 17:39:53 +00:00
Devang Patel 0939595711 Record variable debug info at ISel time directly.
llvm-svn: 79742
2009-08-22 17:12:53 +00:00
Anton Korobeynikov 232b19c3d5 Fix some typos and use type-based isel for VZIP/VUZP/VTRN
llvm-svn: 79625
2009-08-21 12:41:42 +00:00
Anton Korobeynikov ce3ff1be8a Add nodes & dummy matchers for some v{zip,uzp,trn} instructions
llvm-svn: 79622
2009-08-21 12:40:50 +00:00
Bob Wilson 51c7aa04ec Remove Neon intrinsics for VZIP, VUZP, and VTRN. We will represent these as
vector shuffles.  Temporarily remove the tests for these operations until the
new implementation is working.

llvm-svn: 79579
2009-08-21 00:01:42 +00:00
Evan Cheng 9a58aff837 Indentation.
llvm-svn: 79022
2009-08-14 19:01:37 +00:00
Bob Wilson cce31f6831 During legalization, change Neon vdup_lane operations from shuffles to
target-specific VDUPLANE nodes.  This allows the subreg handling for the
quad-register version to be done easily with Pats in the .td file, instead
of with custom code in ARMISelDAGToDAG.cpp.

llvm-svn: 78993
2009-08-14 05:08:32 +00:00
Owen Anderson 55f1c09e31 Push LLVMContexts through the IntegerType APIs.
llvm-svn: 78948
2009-08-13 21:58:54 +00:00
Evan Cheng bb2af3555c Shrink Thumb2 movcc instructions.
llvm-svn: 78790
2009-08-12 05:17:19 +00:00
Bob Wilson f042eadd1e Add missing chain operands for VLD* and VST* instructions.
Set "mayLoad" and "mayStore" on the load/store instructions.

llvm-svn: 78761
2009-08-12 00:49:01 +00:00
Evan Cheng f6a9d06241 Shrinkify Thumb2 r = add sp, imm.
llvm-svn: 78745
2009-08-11 23:00:31 +00:00
Owen Anderson 9f94459d24 Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
the latter is capable of representing either a primitive or an extended type.

llvm-svn: 78713
2009-08-11 20:47:22 +00:00
Jim Grosbach f24f9d9cb6 Whitespace cleanup. Remove trailing whitespace.
llvm-svn: 78666
2009-08-11 15:33:49 +00:00
Evan Cheng 3606467709 Fix Thumb2 load / store addressing mode matching code. Do not use so_reg form to
match base only address, i.e. [r] since Thumb2 requires a offset register field.
For those, use [r + imm12] where the immediate is zero.
Note the generated assembly code does not look any different after the patch.
But the bug would have broken the JIT (if there is Thumb2 support) and it can
break later passes which expect the address mode to be well-formed.

llvm-svn: 78658
2009-08-11 08:52:18 +00:00
Bob Wilson 12842f9865 Use vAny type to get rid of Neon intrinsics that differed only in whether
the overloaded vector types allowed floating-point or integer vector elements.
Most of these operations actually depend on the element type, so bitcasting
was not an option.

If you include the vpadd intrinsics that I updated earlier, this gets rid
of 20 intrinsics.

llvm-svn: 78646
2009-08-11 05:39:44 +00:00
Dan Gohman 733a64db57 Fix a bug where DAGCombine was producing an illegal ConstantFP
node after legalize, and remove the workaround code from the
ARM backend.

llvm-svn: 78615
2009-08-10 23:15:10 +00:00
Owen Anderson 53aa7a960c Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
llvm-svn: 78610
2009-08-10 22:56:29 +00:00
Evan Cheng f72c13bdf5 Handle the constantfp created during post-legalization dag combiner phase.
llvm-svn: 78594
2009-08-10 20:25:59 +00:00
Anton Korobeynikov 887d05ce9b Use VLDM / VSTM to spill/reload 128-bit Neon registers
llvm-svn: 78468
2009-08-08 13:35:48 +00:00
Bob Wilson e2231070ff Implement Neon VZIP and VUZP instructions. These are very similar to VTRN,
so I generalized the class for VTRN in the .td file to handle all 3 of them.

llvm-svn: 78460
2009-08-08 06:13:25 +00:00
Bob Wilson db46af0461 Implement Neon VTRN instructions. For now, anyway, these are selected
directly from the intrinsics produced by the frontend.  If it is more
convenient to have a custom DAG node for using these to implement shuffles,
we can add that later.

llvm-svn: 78459
2009-08-08 05:53:00 +00:00
Evan Cheng b972e5633f It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing.
This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.

This fixes PR4659 and PR4682.

llvm-svn: 78361
2009-08-07 00:34:42 +00:00
Bob Wilson 0127031c20 Implement Neon VST[234] operations.
llvm-svn: 78330
2009-08-06 18:47:44 +00:00
Bob Wilson 488db94e7b Neon does not actually have VLD{234}.64 instructions.
These operations will have to be synthesized from other instructions.

llvm-svn: 78263
2009-08-06 00:24:27 +00:00
Bob Wilson 20f79e321e Change DAG nodes for Neon VLD2/3/4 operations to return multiple results.
Get rid of yesterday's code to fix the register usage during isel.
Select the new DAG nodes to machine instructions.  The new pre-alloc pass
to choose adjacent registers for these results is not done, so the
results of this will generally not assemble yet.

llvm-svn: 78136
2009-08-05 00:49:09 +00:00
Bob Wilson f307e0bd6d Lower CONCAT_VECTOR during legalization instead of matching it during isel.
Add a testcase.

llvm-svn: 77992
2009-08-03 20:36:38 +00:00
Evan Cheng e6e8289d72 Split t2MOVCCs since some assemblers do not recognize mov shifted register alias with predicate.
llvm-svn: 77764
2009-08-01 01:43:45 +00:00
David Goodwin 5aae45fb6f Remove redundant match for frame index from imm8 addrmode, it is handled by the imm12 addrmode.
llvm-svn: 77632
2009-07-30 22:45:52 +00:00
David Goodwin 79c079b478 Cleanup and include code selection for some frame index cases.
llvm-svn: 77622
2009-07-30 18:56:48 +00:00
Evan Cheng faede73a32 Rename tMOVhi2lor to tMOVgpr2tgpr. It's not moving from a high register to a low register. It's moving from a GPR register class to a more restrictive tGPR class. Also change tMOVlor2hir, and tMOVhir2hir.
llvm-svn: 77172
2009-07-26 23:59:01 +00:00
Owen Anderson edb4a70325 Revert the ConstantInt constructors back to their 2.5 forms where possible, thanks to contexts-on-types. More to come.
llvm-svn: 77011
2009-07-24 23:12:02 +00:00
David Goodwin cdd405d804 Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index elimination more exactly for Thumb-2 to get better code gen.
llvm-svn: 76919
2009-07-24 00:16:18 +00:00
Evan Cheng e270d4a4dd Use getTargetConstant instead of getConstant since it's meant as an constant operand.
llvm-svn: 76803
2009-07-22 22:03:29 +00:00
Evan Cheng 1ec4396ee3 Eliminate a redudant check Eli pointed out.
llvm-svn: 76762
2009-07-22 18:08:05 +00:00
Evan Cheng 0d8b0cf3b8 Fix ARM isle code that optimize multiply by constants which are power-of-2 +/- 1.
llvm-svn: 76520
2009-07-21 00:31:12 +00:00
David Goodwin 802a0b576f Use t2LDRri12 for frame index loads.
llvm-svn: 76424
2009-07-20 15:55:39 +00:00
David Goodwin f39120571b Thumb-2 only support [base_reg + offset_reg] addressing, not [base_reg - offset_reg].
llvm-svn: 75789
2009-07-15 15:50:19 +00:00
Owen Anderson b6b2530000 Move EVER MORE stuff over to LLVMContext.
llvm-svn: 75703
2009-07-14 23:09:55 +00:00
David Goodwin 95bad85498 Check for PRE_INC and POST_INC.
llvm-svn: 75683
2009-07-14 21:29:29 +00:00
David Goodwin 4ad7797e1c hasThumb2() does not mean we are compiling for thumb, must also check isThumb().
llvm-svn: 75660
2009-07-14 18:48:51 +00:00
Evan Cheng 0794c6a083 Smarter isel of ldrsb / ldrsh. Only make use of these when [r,r] address is feasible.
llvm-svn: 75360
2009-07-11 07:08:13 +00:00
Evan Cheng cd4cdd1157 Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically.
A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well.

llvm-svn: 75359
2009-07-11 06:43:01 +00:00
Evan Cheng 7591d02c84 Fix ldrd / strd address mode matching code. It allows for +/- 8 bit offset. Also change the printer to make the scale 4 explicit.
Note, we are not yet generating these instructions.

llvm-svn: 75181
2009-07-09 22:21:59 +00:00
David Goodwin 22c2fba978 Use common code for both ARM and Thumb-2 instruction and register info.
llvm-svn: 75067
2009-07-08 23:10:31 +00:00
Evan Cheng e3a53c448b Change how so_imm and t2_so_imm are handled. At instruction selection time, the immediates are no longer encoded in the imm8 + rot format, that are left as it is. The encoding is now done in ams printing and code emission time instead.
llvm-svn: 75048
2009-07-08 21:03:57 +00:00
Torok Edwin fb8d6d5b58 Implement changes from Chris's feedback.
Finish converting lib/Target.

llvm-svn: 75043
2009-07-08 20:53:28 +00:00
Evan Cheng d0611f9a37 Add Thumb2 movcc instructions.
llvm-svn: 74946
2009-07-07 20:39:03 +00:00
Evan Cheng b24e51e2d9 Add some more Thumb2 multiplication instructions.
llvm-svn: 74889
2009-07-07 01:17:28 +00:00
Evan Cheng 8ecd7eb3f7 Sign extending pre/post indexed loads.
llvm-svn: 74736
2009-07-02 23:16:11 +00:00
Evan Cheng 84c6cda2ef Thumb2 pre/post indexed loads.
llvm-svn: 74696
2009-07-02 07:28:31 +00:00
Evan Cheng d9c55368e7 Factor out ARM indexed load matching code.
llvm-svn: 74681
2009-07-02 01:23:32 +00:00
Bob Wilson deb35afd23 Add a new addressing mode for NEON load/store instructions.
llvm-svn: 74658
2009-07-01 23:16:05 +00:00
David Goodwin a83100f687 Thumb-2 load and store double description. But nothing yet creates them.
llvm-svn: 74566
2009-06-30 22:50:01 +00:00
David Goodwin 27303cde82 Add conditional and unconditional thumb-2 branch. Add thumb-2 jump table.
llvm-svn: 74543
2009-06-30 18:04:13 +00:00
Evan Cheng b23b50d54d Implement Thumb2 ldr.
After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.

llvm-svn: 74420
2009-06-29 07:51:04 +00:00
Evan Cheng eab9ca7ea6 Renaming for consistency.
llvm-svn: 74368
2009-06-27 02:26:13 +00:00
Anton Korobeynikov 99152f3a2c Split thumb-related stuff into separate classes.
Step 1: ARMInstructionInfo => {ARM,Thumb}InstructionInfo

llvm-svn: 74329
2009-06-26 21:28:53 +00:00
Evan Cheng 8d21e9c4e6 Code clean up.
llvm-svn: 73986
2009-06-23 19:38:34 +00:00
Evan Cheng e379107cdc Rename SelectShifterOperand to SelectThumb2ShifterOperandReg.
llvm-svn: 73975
2009-06-23 18:14:38 +00:00
Bob Wilson 2e076c4e02 Add support for ARM's Advanced SIMD (NEON) instruction set.
This is still a work in progress but most of the NEON instruction set
is supported.

llvm-svn: 73919
2009-06-22 23:27:02 +00:00
Bob Wilson 360eef0782 Fix llvm-gcc build for armv6t2 and later architectures. The hasV6T2Ops
predicate does not check if Thumb mode is enabled, and when in ARM mode
there are still some checks for constant-pool use that need to run.

llvm-svn: 73887
2009-06-22 17:29:13 +00:00
Anton Korobeynikov 02bb33c58d Initial support for some Thumb2 instructions.
Patch by Viktor Kutuzov and Anton Korzh from Access Softek, Inc.

llvm-svn: 73622
2009-06-17 18:13:58 +00:00
Anton Korobeynikov 3708883bfe Revert hunk commited by accident
llvm-svn: 73097
2009-06-08 22:57:18 +00:00
Anton Korobeynikov 77d1943637 The attached patches implement most of the ARM AAPCS-VFP hard float
ABI. The missing piece is support for putting "homogeneous aggregates"
into registers.

Patch by Sandeep Patel!

llvm-svn: 73095
2009-06-08 22:53:56 +00:00
Bob Wilson a2c462bbe9 Fix pr4091: Add support for "m" constraint in ARM inline assembly.
llvm-svn: 72105
2009-05-19 05:53:42 +00:00
Jim Grosbach fde2110aa9 PR2985 / <rdar://problem/6584986>
When compiling in Thumb mode, only the low (R0-R7) registers are available
for most instructions. Breaking the low registers into a new register class
handles this. Uses of R12, SP, etc, are handled explicitly where needed
with copies inserted to move results into low registers where the rest of
the code generator can deal with them.

llvm-svn: 68545
2009-04-07 20:34:09 +00:00
Evan Cheng 904f14663d tADDhirr is a thumb instruction. Do not allow this code to be reached in non-thumb mode.
llvm-svn: 67765
2009-03-26 19:09:01 +00:00
Chris Lattner 844deb73f4 fix PR3538 for ARM.
llvm-svn: 64384
2009-02-12 17:38:23 +00:00
Dale Johannesen ab8e4425a3 Eliminate remaining non-DebugLoc version of getTargetNode.
llvm-svn: 63951
2009-02-06 19:16:40 +00:00
Dale Johannesen 2c4cf2752d get rid of some non-DebugLoc getTargetNode variants.
llvm-svn: 63909
2009-02-06 02:08:06 +00:00
Dale Johannesen 9f3f72f144 Get rid of one more non-DebugLoc getNode and
its corresponding getTargetNode.  Lots of
caller changes.

llvm-svn: 63904
2009-02-06 01:31:28 +00:00
Dan Gohman 619ef48a52 Move a few containers out of ScheduleDAGInstrs::BuildSchedGraph
and into the ScheduleDAGInstrs class, so that they don't get
destructed and re-constructed for each block. This fixes a
compile-time hot spot in the post-pass scheduler.

To help facilitate this, tidy and do some minor reorganization
in the scheduler constructor functions.

llvm-svn: 62275
2009-01-15 19:20:50 +00:00
Evan Cheng d5021730c8 Preliminary ARM debug support based on patch by Mikael of FlexyCore.
llvm-svn: 60851
2008-12-10 21:54:21 +00:00
Dan Gohman 810daf7e93 Update a comment.
llvm-svn: 60484
2008-12-03 17:10:41 +00:00
Dan Gohman f14b77ebf1 Eliminate the ISel priority queue, which used the topological order for a
priority function. Instead, just iterate over the AllNodes list, which is
already in topological order. This eliminates a fair amount of bookkeeping,
and speeds up the isel phase by about 15% on many testcases.

The impact on most targets is that AddToISelQueue calls can be simply removed.

In the x86 target, there are two additional notable changes.

The rule-bending AND+SHIFT optimization in MatchAddress that creates new
pre-isel nodes during isel is now a little more verbose, but more robust.
Instead of either creating an invalid DAG or creating an invalid topological
sort, as it has historically done, it can now just insert the new nodes into
the node list at a position where they will be consistent with the topological
ordering.

Also, the address-matching code has logic that checked to see if a node was
"already selected". However, when a node is selected, it has all its uses
taken away via ReplaceAllUsesWith or equivalent, so it won't recieve any
further visits from MatchAddress. This code is now removed.

llvm-svn: 58748
2008-11-05 04:14:16 +00:00
David Greene ce2a938186 Have TableGen emit setSubgraphColor calls under control of a -gen-debug
flag.  Then in a debugger developers can set breakpoints at these calls
to see waht is about to be selected and what the resulting subgraph
looks like.  This really helps when debugging instruction selection.

llvm-svn: 58278
2008-10-27 21:56:29 +00:00
Dan Gohman 2c836cf187 Avoid creating two TargetLowering objects for each target.
Instead, just create one, and make sure everything that needs
it can access it. Previously most of the SelectionDAGISel
subclasses all had their own TargetLowering object, which was
redundant with the TargetLowering object in the TargetMachine
subclasses, except on Sparc, where SparcTargetMachine
didn't have a TargetLowering object. Change Sparc to work
more like the other targets here.

llvm-svn: 57016
2008-10-03 16:55:19 +00:00
Evan Cheng bc0d0eccf3 Cosmetic.
llvm-svn: 56299
2008-09-18 07:24:33 +00:00
Dan Gohman effb894453 Rename ConstantSDNode::getValue to getZExtValue, for consistency
with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.

llvm-svn: 56159
2008-09-12 16:56:44 +00:00
Gabor Greif f304a7aa4d erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics
llvm-svn: 55504
2008-08-28 21:40:38 +00:00
Gabor Greif abfdf928d8 disallow direct access to SDValue::ResNo, provide a getter instead
llvm-svn: 55394
2008-08-26 22:36:50 +00:00
Dan Gohman eb0cee91f6 Move the point at which FastISel taps into the SelectionDAGISel
process up to a higher level. This allows FastISel to leverage
more of SelectionDAGISel's infastructure, such as updating Machine
PHI nodes.

Also, implement transitioning from SDISel back to FastISel in
the middle of a block, so it's now possible to go back and
forth. This allows FastISel to hand individual CallInsts and other
complicated things off to SDISel to handle, while handling the rest
of the block itself.

To help support this, reorganize the SelectionDAG class so that it
is allocated once and reused throughout a function, instead of
being completely reallocated for each block.

llvm-svn: 55219
2008-08-23 02:25:05 +00:00
Dan Gohman d3582c9bda Simplify SelectRoot's interface, and factor out some common code
from all targets.

llvm-svn: 55124
2008-08-21 16:36:34 +00:00
Dan Gohman 2ce6f2ad5e Rename SDOperand to SDValue.
llvm-svn: 54128
2008-07-27 21:46:04 +00:00
Dan Gohman 1705968102 Add a new function, ReplaceAllUsesOfValuesWith, which handles bulk
replacement of multiple values. This is slightly more efficient
than doing multiple ReplaceAllUsesOfValueWith calls, and theoretically
could be optimized even further. However, an important property of this
new function is that it handles the case where the source value set and
destination value set overlap. This makes it feasible for isel to use
SelectNodeTo in many very common cases, which is advantageous because
SelectNodeTo avoids a temporary node and it doesn't require CSEMap
updates for users of values that don't change position.

Revamp MorphNodeTo, which is what does all the work of SelectNodeTo, to
handle operand lists more efficiently, and to correctly handle a number
of corner cases to which its new wider use exposes it.

This commit also includes a change to the encoding of post-isel opcodes
in SDNodes; now instead of being sandwiched between the target-independent
pre-isel opcodes and the target-dependent pre-isel opcodes, post-isel
opcodes are now represented as negative values. This makes it possible
to test if an opcode is pre-isel or post-isel without having to know
the size of the current target's post-isel instruction set.

These changes speed up llc overall by 3% and reduce memory usage by 10%
on the InstructionCombining.cpp testcase with -fast and -regalloc=local.

llvm-svn: 53728
2008-07-17 19:10:17 +00:00
Dan Gohman 56e3f63ec5 Add explicit keywords.
llvm-svn: 53179
2008-07-07 18:00:37 +00:00
Evan Cheng 0711d68fa7 Split scheduling from instruction selection.
llvm-svn: 52923
2008-06-30 20:45:06 +00:00
Duncan Sands 13237ac3b9 Wrap MVT::ValueType in a struct to get type safety
and better control the abstraction.  Rename the type
to MVT.  To update out-of-tree patches, the main
thing to do is to rename MVT::ValueType to MVT, and
rewrite expressions like MVT::getSizeInBits(VT) in
the form VT.getSizeInBits().  Use VT.getSimpleVT()
to extract a MVT::SimpleValueType for use in switch
statements (you will get an assert failure if VT is
an extended value type - these shouldn't exist after
type legalization).
This results in a small speedup of codegen and no
new testsuite failures (x86-64 linux).

llvm-svn: 52044
2008-06-06 12:08:01 +00:00
Evan Cheng 2cb9068c78 Dwarf requires variable entries to be in the source order. Right now, since we are recording variable information at isel time this means parameters would appear in the reverse order. The short term fix is to issue recordVariable() at asm printing time instead.
llvm-svn: 46724
2008-02-04 23:06:48 +00:00
Chris Lattner 1770fb883b explicitly include Compiler.h instead of getting it from tblgen in the middle of a class.
llvm-svn: 46676
2008-02-03 05:43:57 +00:00
Chris Lattner e99faac423 don't do ReplaceUses on a result that doesn't exist.
llvm-svn: 46673
2008-02-03 03:20:59 +00:00
Evan Cheng efd142a920 SDIsel processes llvm.dbg.declare by recording the variable debug information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc.
Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes.
For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time.

llvm-svn: 46659
2008-02-02 04:07:54 +00:00
Dan Gohman 47a7d6fafe Factor the addressing mode and the load/store VT out of LoadSDNode
and StoreSDNode into their common base class LSBaseSDNode. Member
functions getLoadedVT and getStoredVT are replaced with the common
getMemoryVT to simplify code that will handle both loads and stores.

llvm-svn: 46538
2008-01-30 00:15:11 +00:00
Chris Lattner a10fff51d9 Rename SSARegMap -> MachineRegisterInfo in keeping with the idea
that "machine" classes are used to represent the current state of
the code being compiled.  Given this expanded name, we can start 
moving other stuff into it.  For now, move the UsedPhysRegs and
LiveIn/LoveOuts vectors from MachineFunction into it.

Update all the clients to match.

This also reduces some needless #includes, such as MachineModuleInfo
from MachineFunction.

llvm-svn: 45467
2007-12-31 04:13:23 +00:00
Chris Lattner f3ebc3f3d2 Remove attribution from file headers, per discussion on llvmdev.
llvm-svn: 45418
2007-12-29 20:36:04 +00:00
Dan Gohman a160361c85 Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} to
use ISD::{S,U}DIVREM and ISD::{S,U}MUL_HIO. Move the lowering code
associated with these operators into target-independent in LegalizeDAG.cpp
and TargetLowering.cpp.

llvm-svn: 42762
2007-10-08 18:33:35 +00:00
Evan Cheng 9d41b311fb Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit.
llvm-svn: 38501
2007-07-10 18:08:01 +00:00
Evan Cheng 7e90b11550 Unfortunately we now require C++ code to isel Bcc, conditional moves, etc.
llvm-svn: 37896
2007-07-05 07:15:27 +00:00
Evan Cheng 0f7cbe8370 Add PredicateOperand to all ARM instructions that have the condition field.
llvm-svn: 37066
2007-05-15 01:29:07 +00:00
Chris Lattner 1c1082133c match a reassociated form of fnmul. This implements CodeGen/ARM/fnmul.ll
llvm-svn: 36660
2007-05-03 00:32:00 +00:00
Evan Cheng 9bb01c9f4f Fix naming inconsistencies.
llvm-svn: 35163
2007-03-19 07:48:02 +00:00
Evan Cheng ee2763f76f Special LDR instructions to load from non-pc-relative constantpools. These are
rematerializable. Only used for constant generation for now.

llvm-svn: 35162
2007-03-19 07:20:03 +00:00
Evan Cheng 72a8bcf238 AM2 can match 2^n +/- 1. e.g. ldr r3, [r2, r2, lsl #2]
llvm-svn: 35088
2007-03-13 21:05:54 +00:00