forked from OSchip/llvm-project
176 lines
5.5 KiB
LLVM
176 lines
5.5 KiB
LLVM
; RUN: llc < %s -x86-early-ifcvt -stress-early-ifcvt | FileCheck %s
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target triple = "x86_64-apple-macosx10.8.0"
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; CHECK: mm2
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define i32 @mm2(i32* nocapture %p, i32 %n) nounwind uwtable readonly ssp {
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entry:
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br label %do.body
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; CHECK: do.body
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; Loop body has no branches before the backedge.
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; CHECK-NOT: LBB
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do.body:
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%max.0 = phi i32 [ 0, %entry ], [ %max.1, %do.cond ]
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%min.0 = phi i32 [ 0, %entry ], [ %min.1, %do.cond ]
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%n.addr.0 = phi i32 [ %n, %entry ], [ %dec, %do.cond ]
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%p.addr.0 = phi i32* [ %p, %entry ], [ %incdec.ptr, %do.cond ]
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%incdec.ptr = getelementptr inbounds i32, i32* %p.addr.0, i64 1
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%0 = load i32, i32* %p.addr.0, align 4
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%cmp = icmp sgt i32 %0, %max.0
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br i1 %cmp, label %do.cond, label %if.else
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if.else:
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%cmp1 = icmp slt i32 %0, %min.0
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%.min.0 = select i1 %cmp1, i32 %0, i32 %min.0
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br label %do.cond
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do.cond:
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%max.1 = phi i32 [ %0, %do.body ], [ %max.0, %if.else ]
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%min.1 = phi i32 [ %min.0, %do.body ], [ %.min.0, %if.else ]
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; CHECK: decl %esi
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; CHECK: jne LBB
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%dec = add i32 %n.addr.0, -1
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%tobool = icmp eq i32 %dec, 0
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br i1 %tobool, label %do.end, label %do.body
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do.end:
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%sub = sub nsw i32 %max.1, %min.1
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ret i32 %sub
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}
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; CHECK: multipreds
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; Deal with alternative tail predecessors
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; CHECK-NOT: LBB
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; CHECK: cmov
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; CHECK-NOT: LBB
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; CHECK: cmov
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; CHECK-NOT: LBB
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; CHECK: fprintf
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define void @multipreds(i32 %sw) nounwind uwtable ssp {
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entry:
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switch i32 %sw, label %if.then29 [
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i32 0, label %if.then37
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i32 127, label %if.end41
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]
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if.then29:
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br label %if.end41
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if.then37:
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br label %if.end41
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if.end41:
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%exit_status.0 = phi i32 [ 2, %if.then29 ], [ 0, %if.then37 ], [ 66, %entry ]
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call void (...) @fprintf(i32 %exit_status.0) nounwind
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unreachable
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}
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declare void @fprintf(...) nounwind
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; CHECK: BZ2_decompress
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; This test case contains irreducible control flow, so MachineLoopInfo doesn't
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; recognize the cycle in the CFG. This would confuse MachineTraceMetrics.
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define void @BZ2_decompress(i8* %s) nounwind ssp {
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entry:
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switch i32 undef, label %sw.default [
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i32 39, label %if.end.sw.bb2050_crit_edge
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i32 36, label %sw.bb1788
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i32 37, label %if.end.sw.bb1855_crit_edge
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i32 40, label %sw.bb2409
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i32 38, label %sw.bb1983
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i32 44, label %if.end.sw.bb3058_crit_edge
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]
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if.end.sw.bb3058_crit_edge: ; preds = %entry
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br label %save_state_and_return
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if.end.sw.bb1855_crit_edge: ; preds = %entry
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br label %save_state_and_return
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if.end.sw.bb2050_crit_edge: ; preds = %entry
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br label %sw.bb2050
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sw.bb1788: ; preds = %entry
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br label %save_state_and_return
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sw.bb1983: ; preds = %entry
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br i1 undef, label %save_state_and_return, label %if.then1990
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if.then1990: ; preds = %sw.bb1983
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br label %while.body2038
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while.body2038: ; preds = %sw.bb2050, %if.then1990
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%groupPos.8 = phi i32 [ 0, %if.then1990 ], [ %groupPos.9, %sw.bb2050 ]
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br i1 undef, label %save_state_and_return, label %if.end2042
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if.end2042: ; preds = %while.body2038
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br i1 undef, label %if.end2048, label %while.end2104
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if.end2048: ; preds = %if.end2042
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%bsLive2054.pre = getelementptr inbounds i8, i8* %s, i32 8
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br label %sw.bb2050
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sw.bb2050: ; preds = %if.end2048, %if.end.sw.bb2050_crit_edge
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%groupPos.9 = phi i32 [ 0, %if.end.sw.bb2050_crit_edge ], [ %groupPos.8, %if.end2048 ]
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%and2064 = and i32 undef, 1
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br label %while.body2038
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while.end2104: ; preds = %if.end2042
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br i1 undef, label %save_state_and_return, label %if.end2117
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if.end2117: ; preds = %while.end2104
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br i1 undef, label %while.body2161.lr.ph, label %while.body2145.lr.ph
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while.body2145.lr.ph: ; preds = %if.end2117
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br label %save_state_and_return
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while.body2161.lr.ph: ; preds = %if.end2117
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br label %save_state_and_return
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sw.bb2409: ; preds = %entry
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br label %save_state_and_return
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sw.default: ; preds = %entry
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call void @BZ2_bz__AssertH__fail() nounwind
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br label %save_state_and_return
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save_state_and_return:
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%groupPos.14 = phi i32 [ 0, %sw.default ], [ %groupPos.8, %while.body2038 ], [ %groupPos.8, %while.end2104 ], [ 0, %if.end.sw.bb3058_crit_edge ], [ 0, %if.end.sw.bb1855_crit_edge ], [ %groupPos.8, %while.body2161.lr.ph ], [ %groupPos.8, %while.body2145.lr.ph ], [ 0, %sw.bb2409 ], [ 0, %sw.bb1788 ], [ 0, %sw.bb1983 ]
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store i32 %groupPos.14, i32* undef, align 4
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ret void
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}
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declare void @BZ2_bz__AssertH__fail()
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; Make sure we don't speculate on div/idiv instructions
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; CHECK: test_idiv
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; CHECK-NOT: cmov
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define i32 @test_idiv(i32 %a, i32 %b) nounwind uwtable readnone ssp {
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%1 = icmp eq i32 %b, 0
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br i1 %1, label %4, label %2
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; <label>:2 ; preds = %0
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%3 = sdiv i32 %a, %b
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br label %4
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; <label>:4 ; preds = %0, %2
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%5 = phi i32 [ %3, %2 ], [ %a, %0 ]
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ret i32 %5
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}
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; CHECK: test_div
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; CHECK-NOT: cmov
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define i32 @test_div(i32 %a, i32 %b) nounwind uwtable readnone ssp {
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%1 = icmp eq i32 %b, 0
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br i1 %1, label %4, label %2
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; <label>:2 ; preds = %0
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%3 = udiv i32 %a, %b
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br label %4
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; <label>:4 ; preds = %0, %2
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%5 = phi i32 [ %3, %2 ], [ %a, %0 ]
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ret i32 %5
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}
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