forked from OSchip/llvm-project
97 lines
3.0 KiB
C
97 lines
3.0 KiB
C
/* ===-- clear_cache.c - Implement __clear_cache ---------------------------===
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*
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* The LLVM Compiler Infrastructure
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*
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* This file is dual licensed under the MIT and the University of Illinois Open
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* Source Licenses. See LICENSE.TXT for details.
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*
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* ===----------------------------------------------------------------------===
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*/
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#include "int_lib.h"
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#if __APPLE__
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#include <libkern/OSCacheControl.h>
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#endif
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#if defined(__NetBSD__) && defined(__arm__)
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#include <machine/sysarch.h>
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#endif
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#if defined(__ANDROID__) && defined(__mips__)
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#include <sys/cachectl.h>
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#endif
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#if defined(__ANDROID__) && defined(__arm__)
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#include <asm/unistd.h>
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#endif
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/*
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* The compiler generates calls to __clear_cache() when creating
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* trampoline functions on the stack for use with nested functions.
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* It is expected to invalidate the instruction cache for the
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* specified range.
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*/
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void __clear_cache(void *start, void *end) {
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#if __i386__ || __x86_64__
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/*
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* Intel processors have a unified instruction and data cache
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* so there is nothing to do
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*/
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#elif defined(__arm__) && !defined(__APPLE__)
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#if defined(__NetBSD__)
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struct arm_sync_icache_args arg;
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arg.addr = (uintptr_t)start;
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arg.len = (uintptr_t)end - (uintptr_t)start;
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sysarch(ARM_SYNC_ICACHE, &arg);
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#elif defined(__ANDROID__)
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const register int start_reg __asm("r0") = (int) (intptr_t) start;
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const register int end_reg __asm("r1") = (int) (intptr_t) end;
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const register int flags __asm("r2") = 0;
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const register int syscall_nr __asm("r7") = __ARM_NR_cacheflush;
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__asm __volatile("svc 0x0" : "=r"(start_reg)
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: "r"(syscall_nr), "r"(start_reg), "r"(end_reg), "r"(flags) : "r0");
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if (start_reg != 0) {
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compilerrt_abort();
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}
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#else
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compilerrt_abort();
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#endif
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#elif defined(__ANDROID__) && defined(__mips__)
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const uintptr_t start_int = (uintptr_t) start;
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const uintptr_t end_int = (uintptr_t) end;
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_flush_cache(start, (end_int - start_int), BCACHE);
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#elif defined(__aarch64__) && !defined(__APPLE__)
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uint64_t xstart = (uint64_t)(uintptr_t) start;
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uint64_t xend = (uint64_t)(uintptr_t) end;
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// Get Cache Type Info
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uint64_t ctr_el0;
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__asm __volatile("mrs %0, ctr_el0" : "=r"(ctr_el0));
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/*
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* dc & ic instructions must use 64bit registers so we don't use
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* uintptr_t in case this runs in an IPL32 environment.
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*/
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const size_t dcache_line_size = 4 << ((ctr_el0 >> 16) & 15);
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for (uint64_t addr = xstart; addr < xend; addr += dcache_line_size)
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__asm __volatile("dc cvau, %0" :: "r"(addr));
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__asm __volatile("dsb ish");
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const size_t icache_line_size = 4 << ((ctr_el0 >> 0) & 15);
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for (uint64_t addr = xstart; addr < xend; addr += icache_line_size)
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__asm __volatile("ic ivau, %0" :: "r"(addr));
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__asm __volatile("isb sy");
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#else
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#if __APPLE__
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/* On Darwin, sys_icache_invalidate() provides this functionality */
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sys_icache_invalidate(start, end-start);
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#else
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compilerrt_abort();
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#endif
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#endif
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}
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