forked from OSchip/llvm-project
89 lines
3.6 KiB
LLVM
89 lines
3.6 KiB
LLVM
; RUN: opt -loop-reduce -S < %s | FileCheck %s
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;
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; <rdar://10619599> "SelectionDAGBuilder shouldn't visit PHI nodes!" assert.
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; <rdar://10655343> SCEVExpander segfault on simple test case
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-f128:128:128-n8:16:32"
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target triple = "i386-apple-darwin"
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; LSR should convert the inner loop (bb7.us) IV (j.01.us) into float*.
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; This involves a nested AddRec, the outer AddRec's loop invariant components
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; cannot find a preheader, so they should be expanded in the loop header
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; (bb7.lr.ph.us) below the existing phi i.12.us.
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; Currently, LSR won't kick in on such loops.
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; CHECK-LABEL: @nopreheader(
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; CHECK: bb7.us:
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; CHECK-NOT: phi float*
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; CHECK: %j.01.us = phi i32
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; CHECK-NOT: phi float*
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define void @nopreheader(float* nocapture %a, i32 %n) nounwind {
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entry:
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%0 = sdiv i32 %n, undef
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indirectbr i8* undef, [label %bb10.preheader]
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bb10.preheader: ; preds = %bb4
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indirectbr i8* undef, [label %bb8.preheader.lr.ph, label %return]
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bb8.preheader.lr.ph: ; preds = %bb10.preheader
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indirectbr i8* null, [label %bb7.lr.ph.us, label %bb9]
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bb7.lr.ph.us: ; preds = %bb9.us, %bb8.preheader.lr.ph
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%i.12.us = phi i32 [ %2, %bb9.us ], [ 0, %bb8.preheader.lr.ph ]
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%tmp30 = mul i32 %0, %i.12.us
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indirectbr i8* undef, [label %bb7.us]
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bb7.us: ; preds = %bb7.lr.ph.us, %bb7.us
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%j.01.us = phi i32 [ 0, %bb7.lr.ph.us ], [ %1, %bb7.us ]
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%tmp31 = add i32 %tmp30, %j.01.us
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%scevgep9 = getelementptr float* %a, i32 %tmp31
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store float undef, float* %scevgep9, align 1
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%1 = add nsw i32 %j.01.us, 1
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indirectbr i8* undef, [label %bb9.us, label %bb7.us]
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bb9.us: ; preds = %bb7.us
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%2 = add nsw i32 %i.12.us, 1
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indirectbr i8* undef, [label %bb7.lr.ph.us, label %return]
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bb9: ; preds = %bb9, %bb8.preheader.lr.ph
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indirectbr i8* undef, [label %bb9, label %return]
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return: ; preds = %bb9, %bb9.us, %bb10.preheader
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ret void
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}
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; In this case, SCEVExpander simply cannot materialize the AddRecExpr
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; that LSR picks. We must detect that %bb8.preheader does not have a
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; preheader and avoid performing LSR on %bb7.
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; CHECK-LABEL: @nopreheader2(
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; CHECK: bb7:
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; CHECK: %indvar = phi i32
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define fastcc void @nopreheader2([200 x i32]* nocapture %Array2) nounwind {
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entry:
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indirectbr i8* undef, [label %bb]
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bb: ; preds = %bb, %entry
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indirectbr i8* undef, [label %bb3, label %bb]
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bb3: ; preds = %bb3, %bb
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indirectbr i8* undef, [label %bb8.preheader, label %bb3]
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bb8.preheader: ; preds = %bb9, %bb3
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%indvar5 = phi i32 [ %indvar.next6, %bb9 ], [ 0, %bb3 ]
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%tmp26 = add i32 %indvar5, 13
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indirectbr i8* null, [label %bb7]
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bb7: ; preds = %bb8.preheader, %bb7
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%indvar = phi i32 [ 0, %bb8.preheader ], [ %indvar.next, %bb7 ]
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%scevgep = getelementptr [200 x i32]* %Array2, i32 %tmp26, i32 %indvar
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store i32 undef, i32* %scevgep, align 4
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%indvar.next = add i32 %indvar, 1
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indirectbr i8* undef, [label %bb9, label %bb7]
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bb9: ; preds = %bb7
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%indvar.next6 = add i32 %indvar5, 1
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indirectbr i8* undef, [label %return, label %bb8.preheader]
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return: ; preds = %bb9
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ret void
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}
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