Suyog Sarda 43fae93da8 Revert 224119 "This patch recognizes (+ (+ v0, v1) (+ v2, v3)), reorders them for bundling into vector of loads, ... and vectorizes it." This was re-ordering floating point data types resulting in mismatch in output. llvm-svn: 224424		2014-12-17 10:34:27 +00:00
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AArch64	Revert 224119 "This patch recognizes (+ (+ v0, v1) (+ v2, v3)), reorders them for bundling into vector of loads,	2014-12-17 10:34:27 +00:00
ARM	Preserve IR flags (nsw, nuw, exact, fast-math) in SLP vectorizer (PR20802).	2014-09-03 17:40:30 +00:00
R600	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
X86	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00
XCore	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00