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Craig Topper 826f44b550 [TargetLowering][AMDGPU] Remove the SimplifyDemandedBits function that takes a User and OpIdx. Stop using it in AMDGPU target for simplifyI24. 
As we saw in D56057 when we tried to use this function on X86, it's unsafe. It allows the operand node to have multiple users, but doesn't prevent recursing past the first node when it does have multiple users. This can cause other simplifications earlier in the graph without regard to what bits are needed by the other users of the first node. Ideally all we should do to the first node if it has multiple uses is bypass it when its not needed by the user we started from. Doing any other transformation that SimplifyDemandedBits can do like turning ZEXT/SEXT into AEXT would result in an increase in instructions.

Fortunately, we already have a function that can do just that, GetDemandedBits. It will only make transformations that involve bypassing a node.

This patch changes AMDGPU's simplifyI24, to use a combination of GetDemandedBits to handle the multiple use simplifications. And then uses the regular SimplifyDemandedBits on each operand to handle simplifications allowed when the operand only has a single use. Unfortunately, GetDemandedBits simplifies constants more aggressively than SimplifyDemandedBits. This caused the -7 constant in the changed test to be simplified to remove the upper bits. I had to modify computeKnownBits to account for this by ignoring the upper 8 bits of the input.

Differential Revision: https://reviews.llvm.org/D56087

llvm-svn: 350560
 		2019-01-07 19:30:43 +00:00
..
AsmParser [AMDGPU] Emit MessagePack HSA Metadata for v3 code object 2018-12-12 19:39:27 +00:00
Disassembler AMDGPU: Separate R600 and GCN TableGen files 2018-06-28 23:47:12 +00:00
InstPrinter AMDGPU: Re-apply r341982 after fixing the layering issue 2018-09-12 18:50:47 +00:00
MCTargetDesc AMDGPU: Use an ABS32_LO relocation for SCRATCH_RSRC_DWORD1 2018-12-19 11:55:03 +00:00
TargetInfo Remove \brief commands from doxygen comments. 2018-05-01 15:54:18 +00:00
Utils [AMDGPU] Extend the SI Load/Store optimizer to combine more things. 2018-12-12 16:15:21 +00:00
AMDGPU.h [AMDGPU] Add new Mode Register pass 2018-12-10 12:06:10 +00:00
AMDGPU.td AMDGPU: Remove llvm.AMDGPU.kill 2018-12-07 17:46:16 +00:00
AMDGPUAliasAnalysis.cpp Allow subclassing ExternalAA 2018-11-07 20:26:42 +00:00
AMDGPUAliasAnalysis.h Allow subclassing ExternalAA 2018-11-07 20:26:42 +00:00
AMDGPUAlwaysInlinePass.cpp AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
AMDGPUAnnotateKernelFeatures.cpp Revert r348971: [AMDGPU] Support for "uniform-work-group-size" attribute 2018-12-13 21:23:12 +00:00
AMDGPUAnnotateUniformValues.cpp AMDGPU: test for uniformity of branch instruction, not its condition 2019-01-07 15:52:28 +00:00
AMDGPUArgumentUsageInfo.cpp AMDGPU/AMDHSA: Remove GridWorkGroupCountX/Y/Z 2018-06-21 18:36:04 +00:00
AMDGPUArgumentUsageInfo.h AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
AMDGPUAsmPrinter.cpp [AMDGPU] Emit MessagePack HSA Metadata for v3 code object 2018-12-12 19:39:27 +00:00
AMDGPUAsmPrinter.h [AMDGPU] Emit MessagePack HSA Metadata for v3 code object 2018-12-12 19:39:27 +00:00
AMDGPUAtomicOptimizer.cpp [AMDGPU] Fix the new atomic optimizer in pixel shaders. 2018-11-05 12:04:48 +00:00
AMDGPUCallLowering.cpp AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
AMDGPUCallLowering.h AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
AMDGPUCallingConv.td AMDGPU: Partially fix handling of packed amdgpu_ps arguments 2018-08-01 19:57:34 +00:00
AMDGPUCodeGenPrepare.cpp [IRBuilder] Fixup CreateIntrinsic to allow specifying Types to Mangle. 2018-10-08 10:32:33 +00:00
AMDGPUFeatures.td AMDGPU: Allow fp32-denormals feature for r600 targets 2018-08-01 15:04:36 +00:00
AMDGPUFixFunctionBitcasts.cpp [AMDGPU] Add a pass to promote bitcast calls 2018-10-26 13:18:36 +00:00
AMDGPUFrameLowering.cpp
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AMDGPUFrameLowering.h Remove \brief commands from doxygen comments. 2018-05-01 15:54:18 +00:00
AMDGPUGISel.td AMDGPU/GlobalISel: Select amdgcn.cvt.pkrtz to 64-bit instructions 2018-10-08 17:49:29 +00:00
AMDGPUGenRegisterBankInfo.def AMDGPU/GlobalISel: Fix ValueMapping tables for i1 2018-12-20 01:33:43 +00:00
AMDGPUHSAMetadataStreamer.cpp [AMDGPU] Emit MessagePack HSA Metadata for v3 code object 2018-12-12 19:39:27 +00:00
AMDGPUHSAMetadataStreamer.h [AMDGPU] Emit MessagePack HSA Metadata for v3 code object 2018-12-12 19:39:27 +00:00
AMDGPUISelDAGToDAG.cpp AMDGPU: Don't peel of the offset if the resulting base could possibly be negative in Indirect addressing. 2018-12-21 20:57:34 +00:00
AMDGPUISelLowering.cpp [TargetLowering][AMDGPU] Remove the SimplifyDemandedBits function that takes a User and OpIdx. Stop using it in AMDGPU target for simplifyI24. 2019-01-07 19:30:43 +00:00
AMDGPUISelLowering.h DAG: Change behavior of fminnum/fmaxnum nodes 2018-10-22 16:27:27 +00:00
AMDGPUInline.cpp fix typos aggressively; NFC 2018-11-07 14:35:36 +00:00
AMDGPUInstrInfo.cpp AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
AMDGPUInstrInfo.h AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
AMDGPUInstrInfo.td AMDGPU: Remove PHI loop condition optimization 2018-10-31 13:26:48 +00:00
AMDGPUInstructionSelector.cpp Revert "AMDGPU/GlobalISel: Implement select for G_INSERT" 2018-10-11 23:36:46 +00:00
AMDGPUInstructionSelector.h Revert "AMDGPU/GlobalISel: Implement select for G_INSERT" 2018-10-11 23:36:46 +00:00
AMDGPUInstructions.td [AMDGPU] Add and update scalar instructions 2018-11-29 16:05:38 +00:00
AMDGPUIntrinsicInfo.cpp AMDGPU: Remove llvm.AMDGPU.kill 2018-12-07 17:46:16 +00:00
AMDGPUIntrinsicInfo.h AMDGPU: Remove llvm.AMDGPU.kill 2018-12-07 17:46:16 +00:00
AMDGPULegalizerInfo.cpp AMDGPU/GlobalISel: RegBankSelect for some fp ops 2018-12-21 03:14:45 +00:00
AMDGPULegalizerInfo.h AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
AMDGPULibCalls.cpp AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
AMDGPULibFunc.cpp [AMDGPU] Fix discarded result of addAttribute 2018-12-09 21:56:50 +00:00
AMDGPULibFunc.h AMDGPU: Fix missing C++ mode comment 2018-06-20 19:45:40 +00:00
AMDGPULowerIntrinsics.cpp AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
AMDGPULowerKernelArguments.cpp AMDGPU: Fix offsets for < 4-byte aggregate kernel arguments 2018-12-07 22:12:17 +00:00
AMDGPULowerKernelAttributes.cpp AMDGPU: Add pass to optimize reqd_work_group_size 2018-05-18 21:35:00 +00:00
AMDGPUMCInstLower.cpp AMDGPU: Fix getInstSizeInBytes 2018-08-29 07:46:09 +00:00
AMDGPUMachineCFGStructurizer.cpp AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
AMDGPUMachineFunction.cpp Reapply "AMDGPU: Fix handling of alignment padding in DAG argument lowering" 2018-07-20 09:05:08 +00:00
AMDGPUMachineFunction.h Reapply "AMDGPU: Fix handling of alignment padding in DAG argument lowering" 2018-07-20 09:05:08 +00:00
AMDGPUMachineModuleInfo.cpp Remove \brief commands from doxygen comments. 2018-05-01 15:54:18 +00:00
AMDGPUMachineModuleInfo.h Remove \brief commands from doxygen comments. 2018-05-01 15:54:18 +00:00
AMDGPUMacroFusion.cpp [AMDGPU] Always pass TRI into findRegister[Use/Def]OperandIdx 2018-11-09 17:58:59 +00:00
AMDGPUMacroFusion.h
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AMDGPUOpenCLEnqueuedBlockLowering.cpp [AMDGPU] Change enqueue kernel handle type 2018-06-13 17:31:51 +00:00
AMDGPUPTNote.h [AMDGPU] Emit MessagePack HSA Metadata for v3 code object 2018-12-12 19:39:27 +00:00
AMDGPUPerfHintAnalysis.cpp AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
AMDGPUPerfHintAnalysis.h Fix -Winconsistent-missing-overrides in AMDGPU code 2018-05-25 17:46:24 +00:00
AMDGPUPromoteAlloca.cpp [AMDGPU] Extend promote alloca vectorization 2018-11-08 00:16:23 +00:00
AMDGPURegAsmNames.inc.cpp
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AMDGPURegisterBankInfo.cpp AMDGPU: Remove VS/SV mappings from select 2019-01-07 13:21:36 +00:00
AMDGPURegisterBankInfo.h AMDGPU/GlobalISel: Legality/regbankselect for atomicrmw/atomic_cmpxchg 2018-12-20 00:33:49 +00:00
AMDGPURegisterBanks.td AMDGPU/GlobalISel: Define InstrMappings for G_ICMP 2018-03-01 19:27:10 +00:00
AMDGPURegisterInfo.cpp AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headers 2018-05-22 02:03:23 +00:00
AMDGPURegisterInfo.h [TargetRegisterInfo] Remove temporary hook enableMultipleCopyHints() 2018-10-05 14:23:11 +00:00
AMDGPURegisterInfo.td AMDGPU: Separate R600 and GCN TableGen files 2018-06-28 23:47:12 +00:00
AMDGPURewriteOutArguments.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AMDGPUSearchableTables.td AMDGPU: Remove old-style image intrinsics 2018-06-21 13:37:45 +00:00
AMDGPUSubtarget.cpp Revert r347871 "Fix: Add support for TFE/LWE in image intrinsic" 2018-11-29 20:14:17 +00:00
AMDGPUSubtarget.h Revert r347871 "Fix: Add support for TFE/LWE in image intrinsic" 2018-11-29 20:14:17 +00:00
AMDGPUTargetMachine.cpp Revert r348971: [AMDGPU] Support for "uniform-work-group-size" attribute 2018-12-13 21:23:12 +00:00
AMDGPUTargetMachine.h AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
AMDGPUTargetObjectFile.cpp [AMDGPU] Change section name with metadata access 2019-01-03 11:22:58 +00:00
AMDGPUTargetObjectFile.h [AMDGPU] Set metadata access for explicit section 2018-12-12 11:20:04 +00:00
AMDGPUTargetTransformInfo.cpp AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
AMDGPUTargetTransformInfo.h AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
AMDGPUUnifyDivergentExitNodes.cpp [NFC] Rename the DivergenceAnalysis to LegacyDivergenceAnalysis 2018-08-30 14:21:36 +00:00
AMDGPUUnifyMetadata.cpp Remove \brief commands from doxygen comments. 2018-05-01 15:54:18 +00:00
AMDILCFGStructurizer.cpp AMDGPU: Separate R600 and GCN TableGen files 2018-06-28 23:47:12 +00:00
AMDKernelCodeT.h Remove @brief commands from doxygen comments, too. 2018-05-01 16:10:38 +00:00
BUFInstructions.td [AMDGPU] Extend the SI Load/Store optimizer to combine more things. 2018-12-12 16:15:21 +00:00
CMakeLists.txt [AMDGPU] Add new Mode Register pass 2018-12-10 12:06:10 +00:00
CaymanInstructions.td [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register. 2017-12-07 10:40:31 +00:00
DSInstructions.td AMDGPU: Avoid selecting ds_{read,write}2_b32 on SI 2018-10-17 15:37:48 +00:00
EvergreenInstructions.td AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
FLATInstructions.td [AMDGPU] Add FixupVectorISel pass, currently Supports SREGs in GLOBAL LD/ST 2018-11-16 01:13:34 +00:00
GCNDPPCombine.cpp [AMDGPU] Combine DPP mov with use instructions (VOP1/2/3) 2018-11-30 14:21:56 +00:00
GCNHazardRecognizer.cpp [AMDGPU] Prevent sequences of non-instructions disrupting GCNHazardRecognizer wait state counting 2018-09-10 10:14:48 +00:00
GCNHazardRecognizer.h AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
GCNILPSched.cpp ScheduleDAG: Cleanup dumping code; NFC 2018-09-19 00:23:35 +00:00
GCNIterativeScheduler.cpp llvm::sort(C.begin(), C.end(), ...) -> llvm::sort(C, ...) 2018-09-27 02:13:45 +00:00
GCNIterativeScheduler.h AMDGPU: Partial ILP scheduler port from SelectionDAG to SchedulingDAG (experimental) 2017-11-20 14:35:53 +00:00
GCNMinRegStrategy.cpp ScheduleDAG: Cleanup dumping code; NFC 2018-09-19 00:23:35 +00:00
GCNProcessors.td [AMDGPU] Defined gfx909 Raven Ridge 2 2018-10-24 08:14:07 +00:00
GCNRegPressure.cpp AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
GCNRegPressure.h AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
GCNSchedStrategy.cpp AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
GCNSchedStrategy.h AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
LLVMBuild.txt [AMDGPU] Emit MessagePack HSA Metadata for v3 code object 2018-12-12 19:39:27 +00:00
MIMGInstructions.td Revert r347871 "Fix: Add support for TFE/LWE in image intrinsic" 2018-11-29 20:14:17 +00:00
R600.td Reapply "AMDGPU: Fix handling of alignment padding in DAG argument lowering" 2018-07-20 09:05:08 +00:00
R600AsmPrinter.cpp AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
R600AsmPrinter.h AMDGPU: Split R600 AsmPrinter code into its own class 2018-05-24 20:02:01 +00:00
R600ClauseMergePass.cpp AMDGPU: Separate R600 and GCN TableGen files 2018-06-28 23:47:12 +00:00
R600ControlFlowFinalizer.cpp AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
R600Defines.h Remove \brief commands from doxygen comments. 2018-05-01 15:54:18 +00:00
R600EmitClauseMarkers.cpp [AMDGPU] Always pass TRI into findRegister[Use/Def]OperandIdx 2018-11-09 17:58:59 +00:00
R600ExpandSpecialInstrs.cpp AMDGPU: Separate R600 and GCN TableGen files 2018-06-28 23:47:12 +00:00
R600FrameLowering.cpp
…
R600FrameLowering.h
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R600ISelLowering.cpp [SelectionDAG] Add FoldBUILD_VECTOR to simplify new BUILD_VECTOR nodes 2018-10-30 10:32:11 +00:00
R600ISelLowering.h AMDGPU/R600: Convert kernel param loads to use PARAM_I_ADDRESS 2018-08-01 18:36:07 +00:00
R600InstrFormats.td AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
R600InstrInfo.cpp [AMDGPU] Always pass TRI into findRegister[Use/Def]OperandIdx 2018-11-09 17:58:59 +00:00
R600InstrInfo.h [PSV] Update API to be able to use TargetCustom without UB. 2018-08-20 19:23:45 +00:00
R600Instructions.td AMDGPU: Remove remnants of old address space mapping 2018-08-31 05:49:54 +00:00
R600MachineFunctionInfo.cpp
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R600MachineFunctionInfo.h
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R600MachineScheduler.cpp Fix clang -Wimplicit-fallthrough warnings across llvm, NFC 2018-11-01 19:54:45 +00:00
R600MachineScheduler.h Remove \brief commands from doxygen comments. 2018-05-01 15:54:18 +00:00
R600OpenCLImageTypeLoweringPass.cpp AMDGPU: Rename OpenCL lowering pass to be R600 specific. 2018-05-13 10:04:48 +00:00
R600OptimizeVectorRegisters.cpp AMDGPU: Separate R600 and GCN TableGen files 2018-06-28 23:47:12 +00:00
R600Packetizer.cpp AMDGPU: Separate R600 and GCN TableGen files 2018-06-28 23:47:12 +00:00
R600Processors.td AMDGPU: Separate R600 and GCN TableGen files 2018-06-28 23:47:12 +00:00
R600RegisterInfo.cpp AMDGPU: Separate R600 and GCN TableGen files 2018-06-28 23:47:12 +00:00
R600RegisterInfo.h AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
R600RegisterInfo.td AMDGPU: Separate R600 and GCN TableGen files 2018-06-28 23:47:12 +00:00
R600Schedule.td
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R700Instructions.td AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
SIAnnotateControlFlow.cpp AMDGPU: test for uniformity of branch instruction, not its condition 2019-01-07 15:52:28 +00:00
SIDebuggerInsertNops.cpp AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
SIDefines.h [AMDGPU] Add new Mode Register pass 2018-12-10 12:06:10 +00:00
SIFixSGPRCopies.cpp AMDGPU: Rewrite SILowerI1Copies to always stay on SALU 2018-10-31 13:27:08 +00:00
SIFixVGPRCopies.cpp AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
SIFixWWMLiveness.cpp [AMDGPU] Reworked SIFixWWMLiveness 2018-08-02 23:31:32 +00:00
SIFixupVectorISel.cpp [AMDGPU] Disable SReg Global LD/ST, perf regression 2018-11-30 18:29:17 +00:00
SIFoldOperands.cpp [AMDGPU] Fix scalar operand folding bug that causes SHOC performance regression. 2019-01-03 19:55:32 +00:00
SIFormMemoryClauses.cpp llvm::sort(C.begin(), C.end(), ...) -> llvm::sort(C, ...) 2018-09-27 02:13:45 +00:00
SIFrameLowering.cpp AMDGPU: Rename isAmdCodeObjectV2 -> isAmdHsaOrMesa 2018-10-04 21:02:16 +00:00
SIFrameLowering.h AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
SIISelLowering.cpp [AMDGPU] Handle OR as operand of raw load/store 2019-01-02 09:47:41 +00:00
SIISelLowering.h [AMDGPU] Promote constant offset to the immediate by finding a new base with 13bit constant offset from the nearby instructions. 2018-12-14 21:13:14 +00:00
SIInsertSkips.cpp AMDGPU: Fix analyzeBranch failing with pseudoterminators 2018-11-16 05:03:02 +00:00
SIInsertWaitcnts.cpp AMDGPU/InsertWaitcnts: Update VGPR/SGPR bounds when brackets are merged 2018-12-19 10:17:49 +00:00
SIInstrFormats.td [AMDGPU] Add new Mode Register pass 2018-12-10 12:06:10 +00:00
SIInstrInfo.cpp [AMDGPU] Add sdwa support for ADD|SUB U64 decomposed Pseudos 2018-12-03 13:04:54 +00:00
SIInstrInfo.h [AMDGPU] Add new Mode Register pass 2018-12-10 12:06:10 +00:00
SIInstrInfo.td [AMDGPU] Combine DPP mov with use instructions (VOP1/2/3) 2018-11-30 14:21:56 +00:00
SIInstructions.td AMDGPU: Add patterns for v4i16/v4f16 -> v4i16/v4f16 bitcasts 2018-12-19 22:53:33 +00:00
SIIntrinsics.td AMDGPU: Remove llvm.SI.tbuffer.store 2018-12-07 18:03:47 +00:00
SILoadStoreOptimizer.cpp [AMDGPU] Removed the unnecessary operand size-check-assert from processBaseWithConstOffset(). 2018-12-18 19:58:39 +00:00
SILowerControlFlow.cpp AMDGPU: Remove PHI loop condition optimization 2018-10-31 13:26:48 +00:00
SILowerI1Copies.cpp AMDGPU: Rewrite SILowerI1Copies to always stay on SALU 2018-10-31 13:27:08 +00:00
SIMachineFunctionInfo.cpp [AMDGPU] Remove FeatureVGPRSpilling 2018-10-31 18:54:06 +00:00
SIMachineFunctionInfo.h AMDGPU/AMDHSA: Remove GridWorkGroupCountX/Y/Z 2018-06-21 18:36:04 +00:00
SIMachineScheduler.cpp [CodeGen][NFC] Make `TII::getMemOpBaseImmOfs` return a base operand 2018-11-28 12:00:20 +00:00
SIMachineScheduler.h Remove \brief commands from doxygen comments. 2018-05-01 15:54:18 +00:00
SIMemoryLegalizer.cpp [AMDGPU] Change the l1 flush instruction for AMDPAL/MESA3D. 2018-12-10 16:35:53 +00:00
SIModeRegister.cpp [AMDGPU] Add new Mode Register pass - minor fix 2018-12-10 16:23:30 +00:00
SIOptimizeExecMasking.cpp AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
SIOptimizeExecMaskingPreRA.cpp [AMDGPU] Fix build failure, second attempt 2018-12-13 05:52:11 +00:00
SIPeepholeSDWA.cpp [AMDGPU] Add sdwa support for ADD|SUB U64 decomposed Pseudos 2018-12-03 13:04:54 +00:00
SIProgramInfo.h [AMDGPU] Refactor HSAMetadataStream::emitKernel (NFC) 2018-07-10 17:31:32 +00:00
SIRegisterInfo.cpp [AMDGPU] Simplify negated condition 2018-12-13 03:17:40 +00:00
SIRegisterInfo.h [AMDGPU] Simplify negated condition 2018-12-13 03:17:40 +00:00
SIRegisterInfo.td AMDGPU: Remove v16i8 from register classes 2019-01-07 13:31:55 +00:00
SISchedule.td [SchedModel] Complete models shouldn't match against itineraries when they don't use them (PR35639) 2018-04-05 13:11:36 +00:00
SIShrinkInstructions.cpp [AMDGPU] Shrink scalar AND, OR, XOR instructions 2018-12-07 15:33:21 +00:00
SIWholeQuadMode.cpp AMDGPU: Refactor Subtarget classes 2018-07-11 20:59:01 +00:00
SMInstructions.td AMDGPU: Allow f32 types for llvm.amdgcn.s.buffer.load 2018-12-07 18:41:39 +00:00
SOPInstructions.td [AMDGPU] Add and update scalar instructions 2018-11-29 16:05:38 +00:00
VIInstrFormats.td
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VIInstructions.td
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VOP1Instructions.td [AMDGPU] Add new Mode Register pass 2018-12-10 12:06:10 +00:00
VOP2Instructions.td [AMDGPU] Add new Mode Register pass 2018-12-10 12:06:10 +00:00
VOP3Instructions.td [AMDGPU] Add new Mode Register pass 2018-12-10 12:06:10 +00:00
VOP3PInstructions.td [AMDGPU] Add new Mode Register pass 2018-12-10 12:06:10 +00:00
VOPCInstructions.td AMDGPU: Implement llvm.amdgcn.icmp/fcmp for i16/f16 2018-08-15 21:25:20 +00:00
VOPInstructions.td [AMDGPU] Combine DPP mov with use instructions (VOP1/2/3) 2018-11-30 14:21:56 +00:00