Nigel
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
llvm-project/llvm/test/CodeGen/RISCV/addimm-mulimm.ll

369 lines
11 KiB
LLVM
Raw Blame History

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
;; Test that (mul (add x, c1), c2) can be transformed to
;; (add (mul x, c2), c1*c2) if profitable.
; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-zba -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IMB %s
; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-zba -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IMB %s
define i32 @add_mul_combine_accept_a1(i32 %x) {
; RV32IMB-LABEL: add_mul_combine_accept_a1:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: addi a1, zero, 29
; RV32IMB-NEXT: mul a0, a0, a1
; RV32IMB-NEXT: addi a0, a0, 1073
; RV32IMB-NEXT: ret
;
; RV64IMB-LABEL: add_mul_combine_accept_a1:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addi a1, zero, 29
; RV64IMB-NEXT: mulw a0, a0, a1
; RV64IMB-NEXT: addiw a0, a0, 1073
; RV64IMB-NEXT: ret
%tmp0 = add i32 %x, 37
%tmp1 = mul i32 %tmp0, 29
ret i32 %tmp1
}
define signext i32 @add_mul_combine_accept_a2(i32 signext %x) {
; RV32IMB-LABEL: add_mul_combine_accept_a2:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: addi a1, zero, 29
; RV32IMB-NEXT: mul a0, a0, a1
; RV32IMB-NEXT: addi a0, a0, 1073
; RV32IMB-NEXT: ret
;
; RV64IMB-LABEL: add_mul_combine_accept_a2:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addi a1, zero, 29
; RV64IMB-NEXT: mulw a0, a0, a1
; RV64IMB-NEXT: addiw a0, a0, 1073
; RV64IMB-NEXT: ret
%tmp0 = add i32 %x, 37
%tmp1 = mul i32 %tmp0, 29
ret i32 %tmp1
}
define i64 @add_mul_combine_accept_a3(i64 %x) {
; RV32IMB-LABEL: add_mul_combine_accept_a3:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: addi a2, zero, 29
; RV32IMB-NEXT: mul a1, a1, a2
; RV32IMB-NEXT: mulhu a3, a0, a2
; RV32IMB-NEXT: add a1, a3, a1
; RV32IMB-NEXT: mul a2, a0, a2
; RV32IMB-NEXT: addi a0, a2, 1073
; RV32IMB-NEXT: sltu a2, a0, a2
; RV32IMB-NEXT: add a1, a1, a2
; RV32IMB-NEXT: ret
;
; RV64IMB-LABEL: add_mul_combine_accept_a3:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addi a1, zero, 29
; RV64IMB-NEXT: mul a0, a0, a1
; RV64IMB-NEXT: addi a0, a0, 1073
; RV64IMB-NEXT: ret
%tmp0 = add i64 %x, 37
%tmp1 = mul i64 %tmp0, 29
ret i64 %tmp1
}
define i32 @add_mul_combine_accept_b1(i32 %x) {
; RV32IMB-LABEL: add_mul_combine_accept_b1:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: addi a1, zero, 23
; RV32IMB-NEXT: mul a0, a0, a1
; RV32IMB-NEXT: lui a1, 50
; RV32IMB-NEXT: addi a1, a1, 1119
; RV32IMB-NEXT: add a0, a0, a1
; RV32IMB-NEXT: ret
;
; RV64IMB-LABEL: add_mul_combine_accept_b1:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addi a1, zero, 23
; RV64IMB-NEXT: mulw a0, a0, a1
; RV64IMB-NEXT: lui a1, 50
; RV64IMB-NEXT: addiw a1, a1, 1119
; RV64IMB-NEXT: addw a0, a0, a1
; RV64IMB-NEXT: ret
%tmp0 = add i32 %x, 8953
%tmp1 = mul i32 %tmp0, 23
ret i32 %tmp1
}
define signext i32 @add_mul_combine_accept_b2(i32 signext %x) {
; RV32IMB-LABEL: add_mul_combine_accept_b2:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: addi a1, zero, 23
; RV32IMB-NEXT: mul a0, a0, a1
; RV32IMB-NEXT: lui a1, 50
; RV32IMB-NEXT: addi a1, a1, 1119
; RV32IMB-NEXT: add a0, a0, a1
; RV32IMB-NEXT: ret
;
; RV64IMB-LABEL: add_mul_combine_accept_b2:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addi a1, zero, 23
; RV64IMB-NEXT: mulw a0, a0, a1
; RV64IMB-NEXT: lui a1, 50
; RV64IMB-NEXT: addiw a1, a1, 1119
; RV64IMB-NEXT: addw a0, a0, a1
; RV64IMB-NEXT: ret
%tmp0 = add i32 %x, 8953
%tmp1 = mul i32 %tmp0, 23
ret i32 %tmp1
}
define i64 @add_mul_combine_accept_b3(i64 %x) {
; RV32IMB-LABEL: add_mul_combine_accept_b3:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: addi a2, zero, 23
; RV32IMB-NEXT: mul a1, a1, a2
; RV32IMB-NEXT: mulhu a3, a0, a2
; RV32IMB-NEXT: add a1, a3, a1
; RV32IMB-NEXT: mul a2, a0, a2
; RV32IMB-NEXT: lui a0, 50
; RV32IMB-NEXT: addi a0, a0, 1119
; RV32IMB-NEXT: add a0, a2, a0
; RV32IMB-NEXT: sltu a2, a0, a2
; RV32IMB-NEXT: add a1, a1, a2
; RV32IMB-NEXT: ret
;
; RV64IMB-LABEL: add_mul_combine_accept_b3:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addi a1, zero, 23
; RV64IMB-NEXT: mul a0, a0, a1
; RV64IMB-NEXT: lui a1, 50
; RV64IMB-NEXT: addiw a1, a1, 1119
; RV64IMB-NEXT: add a0, a0, a1
; RV64IMB-NEXT: ret
%tmp0 = add i64 %x, 8953
%tmp1 = mul i64 %tmp0, 23
ret i64 %tmp1
}
define i32 @add_mul_combine_reject_a1(i32 %x) {
; RV32IMB-LABEL: add_mul_combine_reject_a1:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: addi a1, zero, 29
; RV32IMB-NEXT: mul a0, a0, a1
; RV32IMB-NEXT: lui a1, 14
; RV32IMB-NEXT: addi a1, a1, -185
; RV32IMB-NEXT: add a0, a0, a1
; RV32IMB-NEXT: ret
;
; RV64IMB-LABEL: add_mul_combine_reject_a1:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addi a1, zero, 29
; RV64IMB-NEXT: mulw a0, a0, a1
; RV64IMB-NEXT: lui a1, 14
; RV64IMB-NEXT: addiw a1, a1, -185
; RV64IMB-NEXT: addw a0, a0, a1
; RV64IMB-NEXT: ret
%tmp0 = add i32 %x, 1971
%tmp1 = mul i32 %tmp0, 29
ret i32 %tmp1
}
define signext i32 @add_mul_combine_reject_a2(i32 signext %x) {
; RV32IMB-LABEL: add_mul_combine_reject_a2:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: addi a1, zero, 29
; RV32IMB-NEXT: mul a0, a0, a1
; RV32IMB-NEXT: lui a1, 14
; RV32IMB-NEXT: addi a1, a1, -185
; RV32IMB-NEXT: add a0, a0, a1
; RV32IMB-NEXT: ret
;
; RV64IMB-LABEL: add_mul_combine_reject_a2:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addi a1, zero, 29
; RV64IMB-NEXT: mulw a0, a0, a1
; RV64IMB-NEXT: lui a1, 14
; RV64IMB-NEXT: addiw a1, a1, -185
; RV64IMB-NEXT: addw a0, a0, a1
; RV64IMB-NEXT: ret
%tmp0 = add i32 %x, 1971
%tmp1 = mul i32 %tmp0, 29
ret i32 %tmp1
}
define i64 @add_mul_combine_reject_a3(i64 %x) {
; RV32IMB-LABEL: add_mul_combine_reject_a3:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: addi a2, zero, 29
; RV32IMB-NEXT: mul a1, a1, a2
; RV32IMB-NEXT: mulhu a3, a0, a2
; RV32IMB-NEXT: add a1, a3, a1
; RV32IMB-NEXT: mul a2, a0, a2
; RV32IMB-NEXT: lui a0, 14
; RV32IMB-NEXT: addi a0, a0, -185
; RV32IMB-NEXT: add a0, a2, a0
; RV32IMB-NEXT: sltu a2, a0, a2
; RV32IMB-NEXT: add a1, a1, a2
; RV32IMB-NEXT: ret
;
; RV64IMB-LABEL: add_mul_combine_reject_a3:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addi a1, zero, 29
; RV64IMB-NEXT: mul a0, a0, a1
; RV64IMB-NEXT: lui a1, 14
; RV64IMB-NEXT: addiw a1, a1, -185
; RV64IMB-NEXT: add a0, a0, a1
; RV64IMB-NEXT: ret
%tmp0 = add i64 %x, 1971
%tmp1 = mul i64 %tmp0, 29
ret i64 %tmp1
}
define i32 @add_mul_combine_reject_c1(i32 %x) {
; RV32IMB-LABEL: add_mul_combine_reject_c1:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: sh3add a1, a0, a0
; RV32IMB-NEXT: sh3add a0, a1, a0
; RV32IMB-NEXT: lui a1, 18
; RV32IMB-NEXT: addi a1, a1, -728
; RV32IMB-NEXT: add a0, a0, a1
; RV32IMB-NEXT: ret
;
; RV64IMB-LABEL: add_mul_combine_reject_c1:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: sh3add a1, a0, a0
; RV64IMB-NEXT: sh3add a0, a1, a0
; RV64IMB-NEXT: lui a1, 18
; RV64IMB-NEXT: addiw a1, a1, -728
; RV64IMB-NEXT: addw a0, a0, a1
; RV64IMB-NEXT: ret
%tmp0 = add i32 %x, 1000
%tmp1 = mul i32 %tmp0, 73
ret i32 %tmp1
}
define signext i32 @add_mul_combine_reject_c2(i32 signext %x) {
; RV32IMB-LABEL: add_mul_combine_reject_c2:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: sh3add a1, a0, a0
; RV32IMB-NEXT: sh3add a0, a1, a0
; RV32IMB-NEXT: lui a1, 18
; RV32IMB-NEXT: addi a1, a1, -728
; RV32IMB-NEXT: add a0, a0, a1
; RV32IMB-NEXT: ret
;
; RV64IMB-LABEL: add_mul_combine_reject_c2:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: sh3add a1, a0, a0
; RV64IMB-NEXT: sh3add a0, a1, a0
; RV64IMB-NEXT: lui a1, 18
; RV64IMB-NEXT: addiw a1, a1, -728
; RV64IMB-NEXT: addw a0, a0, a1
; RV64IMB-NEXT: ret
%tmp0 = add i32 %x, 1000
%tmp1 = mul i32 %tmp0, 73
ret i32 %tmp1
}
define i64 @add_mul_combine_reject_c3(i64 %x) {
; RV32IMB-LABEL: add_mul_combine_reject_c3:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: addi a2, zero, 73
; RV32IMB-NEXT: mul a1, a1, a2
; RV32IMB-NEXT: mulhu a3, a0, a2
; RV32IMB-NEXT: add a1, a3, a1
; RV32IMB-NEXT: mul a2, a0, a2
; RV32IMB-NEXT: lui a0, 18
; RV32IMB-NEXT: addi a0, a0, -728
; RV32IMB-NEXT: add a0, a2, a0
; RV32IMB-NEXT: sltu a2, a0, a2
; RV32IMB-NEXT: add a1, a1, a2
; RV32IMB-NEXT: ret
;
; RV64IMB-LABEL: add_mul_combine_reject_c3:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: sh3add a1, a0, a0
; RV64IMB-NEXT: sh3add a0, a1, a0
; RV64IMB-NEXT: lui a1, 18
; RV64IMB-NEXT: addiw a1, a1, -728
; RV64IMB-NEXT: add a0, a0, a1
; RV64IMB-NEXT: ret
%tmp0 = add i64 %x, 1000
%tmp1 = mul i64 %tmp0, 73
ret i64 %tmp1
}
define i32 @add_mul_combine_reject_d1(i32 %x) {
; RV32IMB-LABEL: add_mul_combine_reject_d1:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: sh1add a0, a0, a0
; RV32IMB-NEXT: slli a0, a0, 6
; RV32IMB-NEXT: lui a1, 47
; RV32IMB-NEXT: addi a1, a1, -512
; RV32IMB-NEXT: add a0, a0, a1
; RV32IMB-NEXT: ret
;
; RV64IMB-LABEL: add_mul_combine_reject_d1:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: sh1add a0, a0, a0
; RV64IMB-NEXT: slli a0, a0, 6
; RV64IMB-NEXT: lui a1, 47
; RV64IMB-NEXT: addiw a1, a1, -512
; RV64IMB-NEXT: addw a0, a0, a1
; RV64IMB-NEXT: ret
%tmp0 = add i32 %x, 1000
%tmp1 = mul i32 %tmp0, 192
ret i32 %tmp1
}
define signext i32 @add_mul_combine_reject_d2(i32 signext %x) {
; RV32IMB-LABEL: add_mul_combine_reject_d2:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: sh1add a0, a0, a0
; RV32IMB-NEXT: slli a0, a0, 6
; RV32IMB-NEXT: lui a1, 47
; RV32IMB-NEXT: addi a1, a1, -512
; RV32IMB-NEXT: add a0, a0, a1
; RV32IMB-NEXT: ret
;
; RV64IMB-LABEL: add_mul_combine_reject_d2:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: sh1add a0, a0, a0
; RV64IMB-NEXT: slli a0, a0, 6
; RV64IMB-NEXT: lui a1, 47
; RV64IMB-NEXT: addiw a1, a1, -512
; RV64IMB-NEXT: addw a0, a0, a1
; RV64IMB-NEXT: ret
%tmp0 = add i32 %x, 1000
%tmp1 = mul i32 %tmp0, 192
ret i32 %tmp1
}
define i64 @add_mul_combine_reject_d3(i64 %x) {
; RV32IMB-LABEL: add_mul_combine_reject_d3:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: addi a2, zero, 192
; RV32IMB-NEXT: mulhu a2, a0, a2
; RV32IMB-NEXT: sh1add a1, a1, a1
; RV32IMB-NEXT: slli a1, a1, 6
; RV32IMB-NEXT: add a1, a2, a1
; RV32IMB-NEXT: sh1add a0, a0, a0
; RV32IMB-NEXT: slli a2, a0, 6
; RV32IMB-NEXT: lui a0, 47
; RV32IMB-NEXT: addi a0, a0, -512
; RV32IMB-NEXT: add a0, a2, a0
; RV32IMB-NEXT: sltu a2, a0, a2
; RV32IMB-NEXT: add a1, a1, a2
; RV32IMB-NEXT: ret
;
; RV64IMB-LABEL: add_mul_combine_reject_d3:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: sh1add a0, a0, a0
; RV64IMB-NEXT: slli a0, a0, 6
; RV64IMB-NEXT: lui a1, 47
; RV64IMB-NEXT: addiw a1, a1, -512
; RV64IMB-NEXT: add a0, a0, a1
; RV64IMB-NEXT: ret
%tmp0 = add i64 %x, 1000
%tmp1 = mul i64 %tmp0, 192
ret i64 %tmp1
}
Reference in New Issue View Git Blame Copy Permalink