Amara Emerson 95ac3d15e9 [AArch64][GlobalISel] Add G_VECREDUCE fewerElements support for full scalarization. ... For some reductions like G_VECREDUCE_OR on AArch64, we need to scalarize completely if the source is <= 64b. This change adds support for that in the legalizer. If the source has a pow-2 num elements, then we can do a tree reduction using the scalar operation in the individual elements. Otherwise, we just create a sequential chain of operations. For AArch64, we only need to scalarize if the input is <64b. If it's great than 64b then we can first do a fewElements step to 64b, taking advantage of vector instructions until we reach the point of scalarization. I also had to relax the verifier checks for reductions because the intrinsics support <1 x EltTy> types, which we lower to scalars for GlobalISel. Differential Revision: https://reviews.llvm.org/D108276		2021-08-19 16:38:52 -07:00
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generic-vreg-undef-use.mir	CodeGen: Print/parse LLTs in MachineMemOperands	2021-06-30 16:54:13 -04:00
live-ins-01.mir	…
live-ins-02.mir	…
live-ins-03.mir	…
test_copy.mir	…
test_copy_mismatch_types.mir	…
test_copy_physregs_x86.mir	[X86] AVX512FP16 instructions enabling 1/6	2021-08-10 12:46:01 +08:00
test_g_add.mir	…
test_g_addrspacecast.mir	…
test_g_assert_sext.mir	[GlobalISel] Add G_ASSERT_SEXT	2021-02-17 13:10:34 -08:00
test_g_assert_sext_register_bank_class.mir	[GlobalISel] Add G_ASSERT_SEXT	2021-02-17 13:10:34 -08:00
test_g_assert_zext.mir	…
test_g_assert_zext_register_bank_class.mir	…
test_g_bitcast.mir	…
test_g_brindirect_is_indirect_branch.mir	…
test_g_brjt.mir	…
test_g_brjt_is_indirect_branch.mir	…
test_g_build_vector.mir	…
test_g_build_vector_trunc.mir	…
test_g_bzero.mir	CodeGen: Print/parse LLTs in MachineMemOperands	2021-06-30 16:54:13 -04:00
test_g_concat_vectors.mir	GlobalISel: Verify G_CONCAT_VECTORS has at least 2 sources	2021-03-01 09:10:36 -05:00
test_g_constant.mir	…
test_g_dyn_stackalloc.mir	…
test_g_extract.mir	…
test_g_fcmp.mir	…
test_g_fconstant.mir	…
test_g_icmp.mir	…
test_g_insert.mir	…
test_g_intrinsic.mir	…
test_g_intrinsic_w_side_effects.mir	…
test_g_inttoptr.mir	…
test_g_isnan.mir	[GlobalISel] Add G_ISNAN	2021-08-18 10:42:05 -07:00
test_g_jump_table.mir	…
test_g_load.mir	CodeGen: Print/parse LLTs in MachineMemOperands	2021-06-30 16:54:13 -04:00
test_g_memcpy.mir	CodeGen: Print/parse LLTs in MachineMemOperands	2021-06-30 16:54:13 -04:00
test_g_memcpy_inline.mir	[GISel] Support llvm.memcpy.inline	2021-06-30 12:39:05 -07:00
test_g_memmove.mir	[GISel] Support llvm.memcpy.inline	2021-06-30 12:39:05 -07:00
test_g_memset.mir	CodeGen: Print/parse LLTs in MachineMemOperands	2021-06-30 16:54:13 -04:00
test_g_merge_values.mir	…
test_g_phi.mir	…
test_g_ptr_add.mir	…
test_g_ptrmask.mir	…
test_g_ptrtoint.mir	…
test_g_rotr_rotl.mir	[GlobalISel] Add G_ROTR and G_ROTL opcodes for rotates.	2021-03-25 17:23:30 -07:00
test_g_select.mir	…
test_g_sext_inreg.mir	…
test_g_sextload.mir	CodeGen: Print/parse LLTs in MachineMemOperands	2021-06-30 16:54:13 -04:00
test_g_shuffle_vector.mir	…
test_g_store.mir	CodeGen: Print/parse LLTs in MachineMemOperands	2021-06-30 16:54:13 -04:00
test_g_trunc.mir	…
test_g_ubfx_sbfx.mir	Add missing -march to runline in llvm/test/MachineVerifier/test_g_ubfx_sbfx.mir	2021-03-24 11:23:08 -07:00
test_g_zextload.mir	CodeGen: Print/parse LLTs in MachineMemOperands	2021-06-30 16:54:13 -04:00
test_insert_subreg.mir	[MachineVerifier] Make INSERT_SUBREG diagnostic respect operand 2 subregs	2021-07-21 08:47:17 -07:00
test_phis_precede_nonphis.mir	…
test_vector_reductions.mir	[AArch64][GlobalISel] Add G_VECREDUCE fewerElements support for full scalarization.	2021-08-19 16:38:52 -07:00
verifier-generic-extend-truncate.mir	…
verifier-generic-types-1.mir	…
verifier-generic-types-2.mir	…
verifier-implicit-virtreg-invalid-physreg-liveness.mir	…
verifier-phi-fail0.mir	…
verifier-phi.mir	…
verifier-pseudo-terminators.mir	…
verifier-statepoint.mir	…
verify-regbankselected.mir	…
verify-regops.mir	CodeGen: Print/parse LLTs in MachineMemOperands	2021-06-30 16:54:13 -04:00
verify-selected.mir	…