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llvm-project/llvm/lib/Target/AArch64
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Andrew Wei c2deacd929 [AArch64] Fix ldst optimization of non-immediate store offset 
When matching store instruction for ldst opt, we should make sure store instr is in 'reg+imm' form as load instr,
otherwise, it will have assertion in isLdOffsetInRangeOfSt since it will use getImm() directly.

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D87905
 		2020-09-23 23:00:13 +08:00
..
AsmParser [MC] [Win64EH] Canonicalize ARM64 unwind opcodes 2020-09-11 10:31:04 +03:00
Disassembler [AArch64] Emit warning when disassembling unpredictable LDRAA and LDRAB 2020-06-25 15:56:36 +01:00
GISel [AArch64][GlobalISel] Merge selection of vector-vector G_ASHR/G_LSHR and support more cases. 2020-09-21 16:04:52 -07:00
MCTargetDesc [AArch64] Add -mmark-bti-property flag. 2020-09-17 01:18:36 +02:00
TargetInfo
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Utils [ARM, AArch64] Fix a comment typo. NFC. 2020-08-06 09:23:45 +03:00
AArch64.h [AArch64] Extend AArch64SLSHardeningPass to harden BLR instructions. 2020-06-12 07:34:33 +01:00
AArch64.td [AArch64] Cortex-A55 scheduler model 2020-09-21 10:54:32 +01:00
AArch64A53Fix835769.cpp
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AArch64A57FPLoadBalancing.cpp
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AArch64AdvSIMDScalarPass.cpp [AArch64] Update a code comment incorrectly referring to zero_reg. NFC 2020-08-20 14:36:59 +02:00
AArch64AsmPrinter.cpp AArch64: make sure jump table entries can reach entire image 2020-09-18 09:50:40 +01:00
AArch64BranchTargets.cpp [AArch64] Fix BTI instruction emission. 2020-06-15 15:04:36 +02:00
AArch64CallingConvention.cpp [Alignment][NFC] Use Align for TargetCallingConv::OrigAlign 2020-06-25 13:21:22 +00:00
AArch64CallingConvention.h
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AArch64CallingConvention.td [Alignment][NFC] Use Align for TargetCallingConv::OrigAlign 2020-06-25 13:21:22 +00:00
AArch64CleanupLocalDynamicTLSPass.cpp
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AArch64CollectLOH.cpp [AArch64] Fix CollectLOH creating an AdrpAdd LOH when there's a live used reg 2020-06-01 16:00:55 -07:00
AArch64Combine.td [AArch64][GlobalISel] Add a post-legalize combine for lowering vector-immediate G_ASHR/G_LSHR. 2020-09-21 16:04:52 -07:00
AArch64CompressJumpTables.cpp
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AArch64CondBrTuning.cpp [AArch64CondBrTuning] Ignore debug insts when scanning for NZCV clobbers [10/14] 2020-04-22 17:03:40 -07:00
AArch64ConditionOptimizer.cpp MachineBasicBlock::updateTerminator now requires an explicit layout successor. 2020-06-06 22:30:51 -04:00
AArch64ConditionalCompares.cpp DomTree: Remove getChildren() accessor 2020-07-06 21:58:11 +02:00
AArch64DeadRegisterDefinitionsPass.cpp
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AArch64ExpandImm.cpp
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AArch64ExpandImm.h
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AArch64ExpandPseudoInsts.cpp [SVE] Fix invalid assert in expand_DestructiveOp. 2020-07-04 09:21:40 +00:00
AArch64FalkorHWPFFix.cpp Small fixes for "[LoopInfo] empty() -> isInnermost(), add isOutermost()" 2020-09-22 23:59:34 +03:00
AArch64FastISel.cpp [FastISel] update to use intrinsic's isCommutative(); NFC 2020-08-30 11:36:41 -04:00
AArch64FrameLowering.cpp Revert "Revert "Reapply D70800: Fix AArch64 AAPCS frame record chain"" 2020-09-01 19:29:03 +00:00
AArch64FrameLowering.h [AArch64][SVE] Add missing unwind info for SVE registers. 2020-08-04 11:47:06 +01:00
AArch64GenRegisterBankInfo.def
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AArch64ISelDAGToDAG.cpp [SVE] Make ElementCount members private 2020-08-28 14:43:53 +01:00
AArch64ISelLowering.cpp [SVE] Lower fixed length ISD::VECREDUCE_ADD to Scalable 2020-09-23 09:08:07 -05:00
AArch64ISelLowering.h [SVE] Lower fixed length ISD::VECREDUCE_ADD to Scalable 2020-09-23 09:08:07 -05:00
AArch64InstrAtomics.td
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AArch64InstrFormats.td [MachineScheduler] Fix operand scheduling for pre/post-increment loads 2020-09-12 16:53:12 +03:00
AArch64InstrGISel.td [AArch64][GlobalISel] Add a post-legalize combine for lowering vector-immediate G_ASHR/G_LSHR. 2020-09-21 16:04:52 -07:00
AArch64InstrInfo.cpp [AArch64] Teach analyzeBranch to remove branch equivelent to fallthrough 2020-09-22 14:38:27 -07:00
AArch64InstrInfo.h [AArch64] Enable implicit null check transformation 2020-09-17 16:00:19 -07:00
AArch64InstrInfo.td AArch64: make sure jump table entries can reach entire image 2020-09-18 09:50:40 +01:00
AArch64LoadStoreOptimizer.cpp [AArch64] Fix ldst optimization of non-immediate store offset 2020-09-23 23:00:13 +08:00
AArch64MCInstLower.cpp
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AArch64MCInstLower.h
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AArch64MachineFunctionInfo.cpp MachineFunctionInfo for AArch64 in MIR 2020-04-17 15:16:59 -07:00
AArch64MachineFunctionInfo.h AArch64: make sure jump table entries can reach entire image 2020-09-18 09:50:40 +01:00
AArch64MacroFusion.cpp
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AArch64MacroFusion.h
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AArch64PBQPRegAlloc.cpp
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AArch64PBQPRegAlloc.h
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AArch64PerfectShuffle.h
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AArch64PfmCounters.td
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AArch64PromoteConstant.cpp [AArch64] Don't promote constants with float ConstantExpr. 2020-05-13 23:31:47 +01:00
AArch64RedundantCopyElimination.cpp
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AArch64RegisterBanks.td
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AArch64RegisterInfo.cpp [AArch64] Statepoint support for AArch64. 2020-09-14 16:43:08 -07:00
AArch64RegisterInfo.h [AARCH64][RegisterCoalescer] clang miscompiles zero-extension to long long 2020-09-08 08:04:52 +01:00
AArch64RegisterInfo.td [AArch64][SVE] Fix CFA calculation in presence of SVE objects. 2020-08-04 11:47:06 +01:00
AArch64SIMDInstrOpt.cpp
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AArch64SLSHardening.cpp [NFC] Clean up uses of MachineModuleInfoWrapperPass 2020-07-01 09:45:05 -07:00
AArch64SVEInstrInfo.td [SVE][CodeGen] Lower legal integer -> floating point conversions 2020-09-23 11:53:53 +01:00
AArch64SchedA53.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedA55.td [AArch64] Cortex-A55 scheduler model 2020-09-21 10:54:32 +01:00
AArch64SchedA57.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedA57WriteRes.td
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AArch64SchedCyclone.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedExynosM3.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedExynosM4.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedExynosM5.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedFalkor.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedFalkorDetails.td
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AArch64SchedKryo.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedKryoDetails.td
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AArch64SchedPredExynos.td
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AArch64SchedPredicates.td
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AArch64SchedThunderX.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedThunderX2T99.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedThunderX3T110.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64Schedule.td
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AArch64SelectionDAGInfo.cpp [CodeGen] Refactor getMemBasePlusOffset & getObjectPtrOffset to accept a TypeSize 2020-08-11 12:17:10 +01:00
AArch64SelectionDAGInfo.h [Alignment][NFC] Migrate SelectionDAGTargetInfo::EmitTargetCodeForMemset to Align 2020-06-30 12:46:26 +00:00
AArch64SpeculationHardening.cpp
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AArch64StackOffset.h [AArch64][SVE] Fix CFA calculation in presence of SVE objects. 2020-08-04 11:47:06 +01:00
AArch64StackTagging.cpp [ValueTracking] Remove AllocaForValue parameter 2020-07-30 18:48:34 -07:00
AArch64StackTaggingPreRA.cpp
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AArch64StorePairSuppress.cpp
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AArch64Subtarget.cpp [X86][MC][Target] Initial backend support a tune CPU to support -mtune 2020-08-14 15:31:50 -07:00
AArch64Subtarget.h [X86][MC][Target] Initial backend support a tune CPU to support -mtune 2020-08-14 15:31:50 -07:00
AArch64SystemOperands.td [AArch64] Remove inexistent system register ERXTS_EL1 2020-04-29 16:43:48 +01:00
AArch64TargetMachine.cpp [GlobalISel] Enable usage of BranchProbabilityInfo in IRTranslator. 2020-09-09 14:31:12 -07:00
AArch64TargetMachine.h Support addrspacecast initializers with isNoopAddrSpaceCast 2020-07-31 10:42:43 -04:00
AArch64TargetObjectFile.cpp [X86] Reland D71360 Clean up UseInitArray initialization for X86ELFTargetObjectFile 2020-03-20 21:57:34 -07:00
AArch64TargetObjectFile.h [llvm][ELF][AArch64] Handle R_AARCH64_PLT32 relocation 2020-06-10 11:34:16 -07:00
AArch64TargetTransformInfo.cpp [ARM][TTI] Prevents constants in a min(max) or max(min) pattern from being hoisted when in a loop 2020-09-22 11:54:10 +00:00
AArch64TargetTransformInfo.h [ARM][TTI] Prevents constants in a min(max) or max(min) pattern from being hoisted when in a loop 2020-09-22 11:54:10 +00:00
CMakeLists.txt [AArch64] Introduce AArch64SLSHardeningPass, implementing hardening of RET and BR instructions. 2020-06-11 07:51:17 +01:00
LLVMBuild.txt
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SVEInstrFormats.td [SVE][CodeGen] Lower legal integer -> floating point conversions 2020-09-23 11:53:53 +01:00
SVEIntrinsicOpts.cpp [SVE] Fix bug in SVEIntrinsicOpts::optimizePTest 2020-08-14 07:57:21 +01:00