forked from OSchip/llvm-project
7fff1fbd3c
This hashing scheme has been useful out of tree, and I want to start experimenting with it. Specifically I want to experiment on the MIRVRegNamer, MIRCanononicalizer, and eventually the MachineOutliner. This diff is a first step, that optionally brings stable hashing to the MIRVRegNamer (and as a result, the MIRCanonicalizer). We've tested this hashing scheme on a lot of MachineOperand types that llvm::hash_value can not handle in a stable manner. This stable hashing was also the basis for "Global Machine Outliner for ThinLTO" in EuroLLVM 2020 http://llvm.org/devmtg/2020-04/talks.html#TechTalk_58 Credits: Kyungwoo Lee, Nikolai Tillmann Differential Revision: https://reviews.llvm.org/D86952 |
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| .. | ||
| expected-target-index-name.mir | ||
| intrinsics.mir | ||
| invalid-target-index-operand.mir | ||
| lit.local.cfg | ||
| llc-target-cpu-attr-from-cmdline-ir.mir | ||
| llc-target-cpu-attr-from-cmdline.mir | ||
| load-store-opt-dlc.mir | ||
| machine-function-info-dynlds-align-invalid-case.mir | ||
| machine-function-info-no-ir.mir | ||
| machine-function-info-register-parse-error1.mir | ||
| machine-function-info-register-parse-error2.mir | ||
| machine-function-info.ll | ||
| mfi-frame-offset-reg-class.mir | ||
| mfi-parse-error-frame-offset-reg.mir | ||
| mfi-parse-error-scratch-rsrc-reg.mir | ||
| mfi-parse-error-stack-ptr-offset-reg.mir | ||
| mfi-scratch-rsrc-reg-reg-class.mir | ||
| mfi-stack-ptr-offset-reg-class.mir | ||
| mir-canon-multi.mir | ||
| mircanon-memoperands.mir | ||
| parse-order-reserved-regs.mir | ||
| stack-id.mir | ||
| subreg-def-is-not-ssa.mir | ||
| syncscopes.mir | ||
| target-flags.mir | ||
| target-index-operands.mir | ||