forked from OSchip/llvm-project
				
			
		
			
				
	
	
		
			301 lines
		
	
	
		
			9.8 KiB
		
	
	
	
		
			LLVM
		
	
	
	
			
		
		
	
	
			301 lines
		
	
	
		
			9.8 KiB
		
	
	
	
		
			LLVM
		
	
	
	
; RUN: llc < %s -O3 -march=x86-64 -mcpu=core2 | FileCheck %s -check-prefix=X64
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; RUN: llc < %s -O3 -march=x86 -mcpu=core2 | FileCheck %s -check-prefix=X32
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; @simple is the most basic chain of address induction variables. Chaining
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; saves at least one register and avoids complex addressing and setup
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; code.
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;
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; X64: @simple
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; %x * 4
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; X64: shlq $2
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; no other address computation in the preheader
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; X64-NEXT: xorl
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; X64-NEXT: .align
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; X64: %loop
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; no complex address modes
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; X64-NOT: (%{{[^)]+}},%{{[^)]+}},
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;
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; X32: @simple
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; no expensive address computation in the preheader
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; X32-NOT: imul
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; X32: %loop
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; no complex address modes
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; X32-NOT: (%{{[^)]+}},%{{[^)]+}},
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define i32 @simple(i32* %a, i32* %b, i32 %x) nounwind {
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entry:
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  br label %loop
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loop:
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  %iv = phi i32* [ %a, %entry ], [ %iv4, %loop ]
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  %s = phi i32 [ 0, %entry ], [ %s4, %loop ]
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  %v = load i32* %iv
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  %iv1 = getelementptr inbounds i32* %iv, i32 %x
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  %v1 = load i32* %iv1
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  %iv2 = getelementptr inbounds i32* %iv1, i32 %x
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  %v2 = load i32* %iv2
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  %iv3 = getelementptr inbounds i32* %iv2, i32 %x
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  %v3 = load i32* %iv3
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  %s1 = add i32 %s, %v
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  %s2 = add i32 %s1, %v1
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  %s3 = add i32 %s2, %v2
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  %s4 = add i32 %s3, %v3
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  %iv4 = getelementptr inbounds i32* %iv3, i32 %x
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  %cmp = icmp eq i32* %iv4, %b
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  br i1 %cmp, label %exit, label %loop
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exit:
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  ret i32 %s4
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}
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; @user is not currently chained because the IV is live across memory ops.
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;
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; X64: @user
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; X64: shlq $4
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; X64: lea
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; X64: lea
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; X64: %loop
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; complex address modes
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; X64: (%{{[^)]+}},%{{[^)]+}},
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;
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; X32: @user
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; expensive address computation in the preheader
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; X32: imul
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; X32: %loop
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; complex address modes
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; X32: (%{{[^)]+}},%{{[^)]+}},
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define i32 @user(i32* %a, i32* %b, i32 %x) nounwind {
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entry:
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  br label %loop
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loop:
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  %iv = phi i32* [ %a, %entry ], [ %iv4, %loop ]
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  %s = phi i32 [ 0, %entry ], [ %s4, %loop ]
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  %v = load i32* %iv
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  %iv1 = getelementptr inbounds i32* %iv, i32 %x
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  %v1 = load i32* %iv1
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  %iv2 = getelementptr inbounds i32* %iv1, i32 %x
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  %v2 = load i32* %iv2
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  %iv3 = getelementptr inbounds i32* %iv2, i32 %x
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  %v3 = load i32* %iv3
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  %s1 = add i32 %s, %v
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  %s2 = add i32 %s1, %v1
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  %s3 = add i32 %s2, %v2
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  %s4 = add i32 %s3, %v3
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  %iv4 = getelementptr inbounds i32* %iv3, i32 %x
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  store i32 %s4, i32* %iv
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  %cmp = icmp eq i32* %iv4, %b
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  br i1 %cmp, label %exit, label %loop
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exit:
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  ret i32 %s4
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}
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; @extrastride is a slightly more interesting case of a single
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; complete chain with multiple strides. The test case IR is what LSR
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; used to do, and exactly what we don't want to do. LSR's new IV
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; chaining feature should now undo the damage.
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;
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; X64: extrastride:
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; We currently don't handle this on X64 because the sexts cause
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; strange increment expressions like this:
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; IV + ((sext i32 (2 * %s) to i64) + (-1 * (sext i32 %s to i64)))
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;
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; X32: extrastride:
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; no spills in the preheader
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; X32-NOT: mov{{.*}}(%esp){{$}}
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; X32: %for.body{{$}}
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; no complex address modes
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; X32-NOT: (%{{[^)]+}},%{{[^)]+}},
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; no reloads
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; X32-NOT: (%esp)
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define void @extrastride(i8* nocapture %main, i32 %main_stride, i32* nocapture %res, i32 %x, i32 %y, i32 %z) nounwind {
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entry:
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  %cmp8 = icmp eq i32 %z, 0
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  br i1 %cmp8, label %for.end, label %for.body.lr.ph
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for.body.lr.ph:                                   ; preds = %entry
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  %add.ptr.sum = shl i32 %main_stride, 1 ; s*2
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  %add.ptr1.sum = add i32 %add.ptr.sum, %main_stride ; s*3
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  %add.ptr2.sum = add i32 %x, %main_stride ; s + x
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  %add.ptr4.sum = shl i32 %main_stride, 2 ; s*4
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  %add.ptr3.sum = add i32 %add.ptr2.sum, %add.ptr4.sum ; total IV stride = s*5+x
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  br label %for.body
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for.body:                                         ; preds = %for.body.lr.ph, %for.body
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  %main.addr.011 = phi i8* [ %main, %for.body.lr.ph ], [ %add.ptr6, %for.body ]
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  %i.010 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.body ]
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  %res.addr.09 = phi i32* [ %res, %for.body.lr.ph ], [ %add.ptr7, %for.body ]
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  %0 = bitcast i8* %main.addr.011 to i32*
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  %1 = load i32* %0, align 4
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  %add.ptr = getelementptr inbounds i8* %main.addr.011, i32 %main_stride
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  %2 = bitcast i8* %add.ptr to i32*
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  %3 = load i32* %2, align 4
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  %add.ptr1 = getelementptr inbounds i8* %main.addr.011, i32 %add.ptr.sum
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  %4 = bitcast i8* %add.ptr1 to i32*
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  %5 = load i32* %4, align 4
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  %add.ptr2 = getelementptr inbounds i8* %main.addr.011, i32 %add.ptr1.sum
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  %6 = bitcast i8* %add.ptr2 to i32*
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  %7 = load i32* %6, align 4
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  %add.ptr3 = getelementptr inbounds i8* %main.addr.011, i32 %add.ptr4.sum
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  %8 = bitcast i8* %add.ptr3 to i32*
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  %9 = load i32* %8, align 4
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  %add = add i32 %3, %1
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  %add4 = add i32 %add, %5
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  %add5 = add i32 %add4, %7
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  %add6 = add i32 %add5, %9
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  store i32 %add6, i32* %res.addr.09, align 4
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  %add.ptr6 = getelementptr inbounds i8* %main.addr.011, i32 %add.ptr3.sum
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  %add.ptr7 = getelementptr inbounds i32* %res.addr.09, i32 %y
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  %inc = add i32 %i.010, 1
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  %cmp = icmp eq i32 %inc, %z
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  br i1 %cmp, label %for.end, label %for.body
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for.end:                                          ; preds = %for.body, %entry
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  ret void
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}
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; @foldedidx is an unrolled variant of this loop:
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;  for (unsigned long i = 0; i < len; i += s) {
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;    c[i] = a[i] + b[i];
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;  }
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; where 's' can be folded into the addressing mode.
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; Consequently, we should *not* form any chains.
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;
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; X64: foldedidx:
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; X64: movzbl -3(
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;
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; X32: foldedidx:
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; X32: movzbl -3(
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define void @foldedidx(i8* nocapture %a, i8* nocapture %b, i8* nocapture %c) nounwind ssp {
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entry:
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  br label %for.body
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for.body:                                         ; preds = %for.body, %entry
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  %i.07 = phi i32 [ 0, %entry ], [ %inc.3, %for.body ]
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  %arrayidx = getelementptr inbounds i8* %a, i32 %i.07
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  %0 = load i8* %arrayidx, align 1
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  %conv5 = zext i8 %0 to i32
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  %arrayidx1 = getelementptr inbounds i8* %b, i32 %i.07
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  %1 = load i8* %arrayidx1, align 1
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  %conv26 = zext i8 %1 to i32
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  %add = add nsw i32 %conv26, %conv5
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  %conv3 = trunc i32 %add to i8
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  %arrayidx4 = getelementptr inbounds i8* %c, i32 %i.07
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  store i8 %conv3, i8* %arrayidx4, align 1
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  %inc1 = or i32 %i.07, 1
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  %arrayidx.1 = getelementptr inbounds i8* %a, i32 %inc1
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  %2 = load i8* %arrayidx.1, align 1
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  %conv5.1 = zext i8 %2 to i32
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  %arrayidx1.1 = getelementptr inbounds i8* %b, i32 %inc1
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  %3 = load i8* %arrayidx1.1, align 1
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  %conv26.1 = zext i8 %3 to i32
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  %add.1 = add nsw i32 %conv26.1, %conv5.1
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  %conv3.1 = trunc i32 %add.1 to i8
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  %arrayidx4.1 = getelementptr inbounds i8* %c, i32 %inc1
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  store i8 %conv3.1, i8* %arrayidx4.1, align 1
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  %inc.12 = or i32 %i.07, 2
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  %arrayidx.2 = getelementptr inbounds i8* %a, i32 %inc.12
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  %4 = load i8* %arrayidx.2, align 1
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  %conv5.2 = zext i8 %4 to i32
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  %arrayidx1.2 = getelementptr inbounds i8* %b, i32 %inc.12
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  %5 = load i8* %arrayidx1.2, align 1
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  %conv26.2 = zext i8 %5 to i32
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  %add.2 = add nsw i32 %conv26.2, %conv5.2
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  %conv3.2 = trunc i32 %add.2 to i8
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  %arrayidx4.2 = getelementptr inbounds i8* %c, i32 %inc.12
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  store i8 %conv3.2, i8* %arrayidx4.2, align 1
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  %inc.23 = or i32 %i.07, 3
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  %arrayidx.3 = getelementptr inbounds i8* %a, i32 %inc.23
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  %6 = load i8* %arrayidx.3, align 1
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  %conv5.3 = zext i8 %6 to i32
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  %arrayidx1.3 = getelementptr inbounds i8* %b, i32 %inc.23
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  %7 = load i8* %arrayidx1.3, align 1
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  %conv26.3 = zext i8 %7 to i32
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  %add.3 = add nsw i32 %conv26.3, %conv5.3
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  %conv3.3 = trunc i32 %add.3 to i8
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  %arrayidx4.3 = getelementptr inbounds i8* %c, i32 %inc.23
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  store i8 %conv3.3, i8* %arrayidx4.3, align 1
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  %inc.3 = add nsw i32 %i.07, 4
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  %exitcond.3 = icmp eq i32 %inc.3, 400
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  br i1 %exitcond.3, label %for.end, label %for.body
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for.end:                                          ; preds = %for.body
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  ret void
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}
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; @multioper tests instructions with multiple IV user operands. We
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; should be able to chain them independent of each other.
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;
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; X64: @multioper
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; X64: %for.body
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; X64: movl %{{.*}},4)
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; X64-NEXT: leal 1(
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; X64-NEXT: movl %{{.*}},4)
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; X64-NEXT: leal 2(
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; X64-NEXT: movl %{{.*}},4)
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; X64-NEXT: leal 3(
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; X64-NEXT: movl %{{.*}},4)
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;
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; X32: @multioper
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; X32: %for.body
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; X32: movl %{{.*}},4)
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; X32-NEXT: leal 1(
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; X32-NEXT: movl %{{.*}},4)
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; X32-NEXT: leal 2(
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; X32-NEXT: movl %{{.*}},4)
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; X32-NEXT: leal 3(
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; X32-NEXT: movl %{{.*}},4)
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define void @multioper(i32* %a, i32 %n) nounwind {
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entry:
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  br label %for.body
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for.body:
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  %p = phi i32* [ %p.next, %for.body ], [ %a, %entry ]
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  %i = phi i32 [ %inc4, %for.body ], [ 0, %entry ]
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  store i32 %i, i32* %p, align 4
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  %inc1 = or i32 %i, 1
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  %add.ptr.i1 = getelementptr inbounds i32* %p, i32 1
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  store i32 %inc1, i32* %add.ptr.i1, align 4
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  %inc2 = add nsw i32 %i, 2
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  %add.ptr.i2 = getelementptr inbounds i32* %p, i32 2
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  store i32 %inc2, i32* %add.ptr.i2, align 4
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  %inc3 = add nsw i32 %i, 3
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  %add.ptr.i3 = getelementptr inbounds i32* %p, i32 3
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  store i32 %inc3, i32* %add.ptr.i3, align 4
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  %p.next = getelementptr inbounds i32* %p, i32 4
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  %inc4 = add nsw i32 %i, 4
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  %cmp = icmp slt i32 %inc4, %n
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  br i1 %cmp, label %for.body, label %exit
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exit:
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  ret void
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}
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; @testCmpZero has a ICmpZero LSR use that should not be hidden from
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; LSR. Profitable chains should have more than one nonzero increment
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; anyway.
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;
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; X32: @testCmpZero
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; X32: %for.body82.us
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; X32: dec
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; X32: jne
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define void @testCmpZero(i8* %src, i8* %dst, i32 %srcidx, i32 %dstidx, i32 %len) nounwind ssp {
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entry:
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  %dest0 = getelementptr inbounds i8* %src, i32 %srcidx
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  %source0 = getelementptr inbounds i8* %dst, i32 %dstidx
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  %add.ptr79.us.sum = add i32 %srcidx, %len
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  %lftr.limit = getelementptr i8* %src, i32 %add.ptr79.us.sum
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  br label %for.body82.us
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for.body82.us:
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  %dest = phi i8* [ %dest0, %entry ], [ %incdec.ptr91.us, %for.body82.us ]
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  %source = phi i8* [ %source0, %entry ], [ %add.ptr83.us, %for.body82.us ]
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  %0 = bitcast i8* %source to i32*
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  %1 = load i32* %0, align 4
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  %trunc = trunc i32 %1 to i8
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  %add.ptr83.us = getelementptr inbounds i8* %source, i32 4
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  %incdec.ptr91.us = getelementptr inbounds i8* %dest, i32 1
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  store i8 %trunc, i8* %dest, align 1
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  %exitcond = icmp eq i8* %incdec.ptr91.us, %lftr.limit
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  br i1 %exitcond, label %return, label %for.body82.us
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return:
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  ret void
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}
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