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llvm-project/llvm/test/DebugInfo/MIR/ARM
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Sam Parker a3e41d4581 [ARM] Make MachineVerifier more strict about terminators 
Fix the ARM backend's analyzeBranch so it doesn't ignore predicated
return instructions, and make the MachineVerifier rule more strict.

Differential Revision: https://reviews.llvm.org/D40061
 		2020-08-27 07:10:20 +01:00
..
call-site-info-vmovd.mir Reland D73534: [DebugInfo] Enable the debug entry values feature by default 2020-03-19 13:57:30 +01:00
call-site-info-vmovs.mir Reland D73534: [DebugInfo] Enable the debug entry values feature by default 2020-03-19 13:57:30 +01:00
dbgcall-site-interpretation.mir [CallSiteInfo] Enable the call site info only for -g + optimizations 2020-03-09 12:12:44 +01:00
dbgcall-site-propagated-value.mir Reland D73534: [DebugInfo] Enable the debug entry values feature by default 2020-03-19 13:57:30 +01:00
dbgcallsite-noreg-is-imm-check.mir [CallSiteInfo] Enable the call site info only for -g + optimizations 2020-03-09 12:12:44 +01:00
if-coverter-call-site-info.mir [CallSiteInfo] Enable the call site info only for -g + optimizations 2020-03-09 12:12:44 +01:00
larger-subregister.mir [ARM] Move ConstantIsland and LowOverheadLoops Passes. 2020-03-25 16:49:21 +01:00
lit.local.cfg [lit] Delete empty lines at the end of lit.local.cfg NFC 2019-06-17 09:51:07 +00:00
live-debug-values-reg-copy.mir [MIR][ARM] MachineOperand comments 2020-02-24 14:19:21 +00:00
param-reg-const-mix.mir [ARM] Move ConstantIsland and LowOverheadLoops Passes. 2020-03-25 16:49:21 +01:00
split-superreg-complex.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
split-superreg-piece.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
split-superreg.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
subregister-full-piece.mir [ARM] Make MachineVerifier more strict about terminators 2020-08-27 07:10:20 +01:00