forked from OSchip/llvm-project
52 lines
1.7 KiB
C++
52 lines
1.7 KiB
C++
//===- MipsSubtarget.cpp - Mips Subtarget Information -----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the Mips specific subclass of TargetSubtarget.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsSubtarget.h"
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#include "Mips.h"
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#include "MipsGenSubtarget.inc"
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using namespace llvm;
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MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &FS,
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bool little) :
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MipsArchVersion(Mips1), MipsABI(O32), IsLittle(little), IsSingleFloat(false),
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IsFP64bit(false), IsGP64bit(false), HasVFPU(false), IsLinux(true),
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HasSEInReg(false), HasCondMov(false), HasMulDivAdd(false), HasMinMax(false),
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HasSwap(false), HasBitCount(false)
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{
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std::string CPU = "mips1";
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MipsArchVersion = Mips1;
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// Parse features string.
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ParseSubtargetFeatures(FS, CPU);
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// Is the target system Linux ?
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if (TT.find("linux") == std::string::npos)
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IsLinux = false;
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// When only the target triple is specified and is
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// a allegrex target, set the features. We also match
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// big and little endian allegrex cores (dont really
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// know if a big one exists)
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if (TT.find("mipsallegrex") != std::string::npos ||
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TT.find("psp") != std::string::npos) {
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MipsABI = EABI;
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IsSingleFloat = true;
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MipsArchVersion = Mips2;
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HasVFPU = true; // Enables Allegrex Vector FPU (not supported yet)
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HasSEInReg = true;
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HasBitCount = true;
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HasSwap = true;
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HasCondMov = true;
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}
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}
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