Andrea Di Biagio dd0dc19b1c Set an explicit x86 triple for test bottleneck-analysis.s added by my r364045. NFC ... This should unbreak the ppc64 buildbots. llvm-svn: 364048		2019-06-21 14:05:58 +00:00
..
bottleneck-analysis.s	Set an explicit x86 triple for test bottleneck-analysis.s added by my r364045. NFC	2019-06-21 14:05:58 +00:00
resources-adx.s	…
resources-aes.s	[llvm-mca][x86] Add missing AES instruction resource tests	2018-12-07 18:35:54 +00:00
resources-avx1.s	[X86] Add missing properties on llvm.x86.sse.{st,ld}mxcsr	2019-06-19 08:44:31 +00:00
resources-avx2.s	[MCA] Fix typo in AVX2 gather tests. NFC	2019-04-28 10:54:45 +00:00
resources-bmi1.s	[llvm-mca][X86] Add missing tzcntw tests	2019-01-22 14:53:52 +00:00
resources-bmi2.s	…
resources-clflushopt.s	…
resources-cmov.s	…
resources-cmpxchg.s	…
resources-f16c.s	…
resources-fma.s	…
resources-fsgsbase.s	[llvm-mca][X86] Add missing CLWB/CLZERO/FSGSBASE/LWP/MWAITX/RDPID/SHA tests	2019-01-22 16:39:28 +00:00
resources-lea.s	…
resources-lzcnt.s	…
resources-mmx.s	…
resources-movbe.s	…
resources-pclmul.s	…
resources-popcnt.s	…
resources-prefetchw.s	…
resources-rdrand.s	[llvm-mca][x86] Add RDRAND/RDSEED instruction resource tests	2018-12-07 18:29:47 +00:00
resources-rdseed.s	[llvm-mca][x86] Add RDRAND/RDSEED instruction resource tests	2018-12-07 18:29:47 +00:00
resources-sse1.s	[X86] Add missing properties on llvm.x86.sse.{st,ld}mxcsr	2019-06-19 08:44:31 +00:00
resources-sse2.s	[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.	2019-05-06 21:39:51 +00:00
resources-sse3.s	[llvm-mca][X86] Add missing monitor/mwait tests	2019-01-22 15:48:16 +00:00
resources-sse41.s	…
resources-sse42.s	…
resources-ssse3.s	…
resources-x86_32.s	…
resources-x86_64.s	[X86] Correct scheduler information for rotate by constant for Haswell, Broadwell, and Skylake.	2019-03-07 21:22:56 +00:00
resources-x87.s	[X86] Print all register forms of x87 fadd/fsub/fdiv/fmul as having two arguments where on is %st.	2019-02-04 17:28:18 +00:00
zero-idioms.s	[X86] Add zero idioms to the haswell, broadwell, and skylake schedule models. Add 256-bit fp xor to sandybridge zero idioms	2019-05-25 04:47:49 +00:00