forked from OSchip/llvm-project
80 lines
2.8 KiB
C++
80 lines
2.8 KiB
C++
//===-- llvm/CodeGen/AllocationOrder.cpp - Allocation Order ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements an allocation order for virtual registers.
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//
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// The preferred allocation order for a virtual register depends on allocation
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// hints and target hooks. The AllocationOrder class encapsulates all of that.
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//
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//===----------------------------------------------------------------------===//
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#include "AllocationOrder.h"
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#include "RegisterClassInfo.h"
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#include "VirtRegMap.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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using namespace llvm;
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// Compare VirtRegMap::getRegAllocPref().
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AllocationOrder::AllocationOrder(unsigned VirtReg,
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const VirtRegMap &VRM,
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const RegisterClassInfo &RegClassInfo)
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: Begin(0), End(0), Pos(0), RCI(RegClassInfo), OwnedBegin(false) {
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const TargetRegisterClass *RC = VRM.getRegInfo().getRegClass(VirtReg);
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std::pair<unsigned, unsigned> HintPair =
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VRM.getRegInfo().getRegAllocationHint(VirtReg);
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// HintPair.second is a register, phys or virt.
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Hint = HintPair.second;
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// Translate to physreg, or 0 if not assigned yet.
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if (TargetRegisterInfo::isVirtualRegister(Hint))
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Hint = VRM.getPhys(Hint);
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// The first hint pair component indicates a target-specific hint.
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if (HintPair.first) {
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const TargetRegisterInfo &TRI = VRM.getTargetRegInfo();
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// The remaining allocation order may depend on the hint.
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ArrayRef<uint16_t> Order =
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TRI.getRawAllocationOrder(RC, HintPair.first, Hint,
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VRM.getMachineFunction());
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if (Order.empty())
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return;
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// Copy the allocation order with reserved registers removed.
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OwnedBegin = true;
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unsigned *P = new unsigned[Order.size()];
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Begin = P;
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for (unsigned i = 0; i != Order.size(); ++i)
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if (!RCI.isReserved(Order[i]))
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*P++ = Order[i];
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End = P;
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// Target-dependent hints require resolution.
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Hint = TRI.ResolveRegAllocHint(HintPair.first, Hint,
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VRM.getMachineFunction());
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} else {
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// If there is no hint or just a normal hint, use the cached allocation
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// order from RegisterClassInfo.
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ArrayRef<unsigned> O = RCI.getOrder(RC);
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Begin = O.begin();
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End = O.end();
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}
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// The hint must be a valid physreg for allocation.
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if (Hint && (!TargetRegisterInfo::isPhysicalRegister(Hint) ||
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!RC->contains(Hint) || RCI.isReserved(Hint)))
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Hint = 0;
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}
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AllocationOrder::~AllocationOrder() {
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if (OwnedBegin)
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delete [] Begin;
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}
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