forked from OSchip/llvm-project
39ae86ab72
This patch adds a custom implementation of isLegalNTStore to AArch64TTI that supports vector types that can be directly stored by STNP. Note that the implementation may not catch all valid cases (e.g. because the vector is a multiple of 256 and could be broken down to multiple valid 256 bit stores), but it is good enough for LV to vectorize loops with NT stores, as LV only passes in a vector with 2 elements to check. LV seems to also be the only user of isLegalNTStore. We should also do the same for NT loads, but before that we need to ensure that we properly lower LDNP of vectors, similar to D72919. Reviewers: dmgreen, samparker, t.p.northover, ab Reviewed By: dmgreen Differential Revision: https://reviews.llvm.org/D73158 |
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| .. | ||
| aarch64-predication.ll | ||
| aarch64-unroll.ll | ||
| arbitrary-induction-step.ll | ||
| arm64-unroll.ll | ||
| backedge-overflow.ll | ||
| deterministic-type-shrinkage.ll | ||
| extractvalue-no-scalarization-required.ll | ||
| gather-cost.ll | ||
| induction-trunc.ll | ||
| interleaved-vs-scalar.ll | ||
| interleaved_cost.ll | ||
| lit.local.cfg | ||
| loop-vectorization-factors.ll | ||
| max-vf-for-interleaved.ll | ||
| no_vector_instructions.ll | ||
| nontemporal-load-store.ll | ||
| outer_loop_test1_no_explicit_vect_width.ll | ||
| pr31900.ll | ||
| pr33053.ll | ||
| pr36032.ll | ||
| predication_costs.ll | ||
| reduction-small-size.ll | ||
| sdiv-pow2.ll | ||
| smallest-and-widest-types.ll | ||
| type-shrinkage-insertelt.ll | ||