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.github/image/ov-pipline.drawio vendored
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<mxfile host="app.diagrams.net" modified="2024-04-11T06:42:17.627Z" agent="Mozilla/5.0 (Windows NT 10.0; Win64; x64) AppleWebKit/537.36 (KHTML, like Gecko) Chrome/123.0.0.0 Safari/537.36 Edg/123.0.0.0" etag="6yX-ULCYsPwj42ocDWqh" version="24.0.7" type="device">
<diagram name="Page-1" id="FTH7PsahlGnXAK5tEtyi">
<mxGraphModel dx="843" dy="512" grid="1" gridSize="10" guides="1" tooltips="1" connect="1" arrows="1" fold="1" page="1" pageScale="1" pageWidth="827" pageHeight="1169" math="0" shadow="0">
<root>
<mxCell id="0" />
<mxCell id="1" parent="0" />
<mxCell id="NuuIC_HhkidKEVra6tKi-31" value="" style="group" vertex="1" connectable="0" parent="1">
<mxGeometry x="60" y="230" width="630" height="150" as="geometry" />
</mxCell>
<mxCell id="NuuIC_HhkidKEVra6tKi-1" value="在线报名" style="rounded=0;whiteSpace=wrap;html=1;" vertex="1" parent="NuuIC_HhkidKEVra6tKi-31">
<mxGeometry x="80" y="30" width="20" height="100" as="geometry" />
</mxCell>
<mxCell id="NuuIC_HhkidKEVra6tKi-2" value="资格认证" style="rounded=0;whiteSpace=wrap;html=1;" vertex="1" parent="NuuIC_HhkidKEVra6tKi-31">
<mxGeometry x="140" y="30" width="20" height="100" as="geometry" />
</mxCell>
<mxCell id="NuuIC_HhkidKEVra6tKi-3" value="F&lt;div&gt;o&lt;/div&gt;&lt;div&gt;r&lt;/div&gt;&lt;div&gt;k&lt;/div&gt;&lt;div&gt;仓库&lt;/div&gt;" style="rounded=0;whiteSpace=wrap;html=1;" vertex="1" parent="NuuIC_HhkidKEVra6tKi-31">
<mxGeometry x="200" y="30" width="20" height="100" as="geometry" />
</mxCell>
<mxCell id="NuuIC_HhkidKEVra6tKi-20" value="" style="edgeStyle=orthogonalEdgeStyle;rounded=0;orthogonalLoop=1;jettySize=auto;html=1;" edge="1" parent="NuuIC_HhkidKEVra6tKi-31" source="NuuIC_HhkidKEVra6tKi-4" target="NuuIC_HhkidKEVra6tKi-7">
<mxGeometry relative="1" as="geometry" />
</mxCell>
<mxCell id="NuuIC_HhkidKEVra6tKi-4" value="领取任务" style="rounded=0;whiteSpace=wrap;html=1;" vertex="1" parent="NuuIC_HhkidKEVra6tKi-31">
<mxGeometry x="250" y="30" width="20" height="100" as="geometry" />
</mxCell>
<mxCell id="NuuIC_HhkidKEVra6tKi-21" value="" style="edgeStyle=orthogonalEdgeStyle;rounded=0;orthogonalLoop=1;jettySize=auto;html=1;" edge="1" parent="NuuIC_HhkidKEVra6tKi-31" source="NuuIC_HhkidKEVra6tKi-6" target="NuuIC_HhkidKEVra6tKi-8">
<mxGeometry relative="1" as="geometry" />
</mxCell>
<mxCell id="NuuIC_HhkidKEVra6tKi-6" value="测试点分解&amp;amp;验证方案" style="rounded=0;whiteSpace=wrap;html=1;" vertex="1" parent="NuuIC_HhkidKEVra6tKi-31">
<mxGeometry x="310" y="30" width="30" height="100" as="geometry" />
</mxCell>
<mxCell id="NuuIC_HhkidKEVra6tKi-7" value="编写&lt;div&gt;&amp;amp;测试测用例&lt;/div&gt;" style="rounded=0;whiteSpace=wrap;html=1;" vertex="1" parent="NuuIC_HhkidKEVra6tKi-31">
<mxGeometry x="370" y="30" width="30" height="100" as="geometry" />
</mxCell>
<mxCell id="NuuIC_HhkidKEVra6tKi-22" value="" style="edgeStyle=orthogonalEdgeStyle;rounded=0;orthogonalLoop=1;jettySize=auto;html=1;entryX=0;entryY=0.5;entryDx=0;entryDy=0;" edge="1" parent="NuuIC_HhkidKEVra6tKi-31" source="NuuIC_HhkidKEVra6tKi-8" target="NuuIC_HhkidKEVra6tKi-9">
<mxGeometry relative="1" as="geometry" />
</mxCell>
<mxCell id="NuuIC_HhkidKEVra6tKi-28" style="edgeStyle=orthogonalEdgeStyle;rounded=0;orthogonalLoop=1;jettySize=auto;html=1;exitX=0.5;exitY=1;exitDx=0;exitDy=0;entryX=0.25;entryY=1;entryDx=0;entryDy=0;" edge="1" parent="NuuIC_HhkidKEVra6tKi-31" source="NuuIC_HhkidKEVra6tKi-8" target="NuuIC_HhkidKEVra6tKi-4">
<mxGeometry relative="1" as="geometry" />
</mxCell>
<mxCell id="NuuIC_HhkidKEVra6tKi-30" style="edgeStyle=orthogonalEdgeStyle;rounded=0;orthogonalLoop=1;jettySize=auto;html=1;entryX=0.5;entryY=1;entryDx=0;entryDy=0;" edge="1" parent="NuuIC_HhkidKEVra6tKi-31" source="NuuIC_HhkidKEVra6tKi-8" target="NuuIC_HhkidKEVra6tKi-7">
<mxGeometry relative="1" as="geometry">
<Array as="points">
<mxPoint x="440" y="150" />
<mxPoint x="385" y="150" />
</Array>
</mxGeometry>
</mxCell>
<mxCell id="NuuIC_HhkidKEVra6tKi-8" value="b&lt;div&gt;u&lt;/div&gt;&lt;div&gt;g汇报&lt;/div&gt;" style="rounded=0;whiteSpace=wrap;html=1;" vertex="1" parent="NuuIC_HhkidKEVra6tKi-31">
<mxGeometry x="430" y="30" width="20" height="100" as="geometry" />
</mxCell>
<mxCell id="NuuIC_HhkidKEVra6tKi-23" value="" style="edgeStyle=orthogonalEdgeStyle;rounded=0;orthogonalLoop=1;jettySize=auto;html=1;" edge="1" parent="NuuIC_HhkidKEVra6tKi-31" source="NuuIC_HhkidKEVra6tKi-9" target="NuuIC_HhkidKEVra6tKi-10">
<mxGeometry relative="1" as="geometry" />
</mxCell>
<mxCell id="NuuIC_HhkidKEVra6tKi-9" value="测试文档撰写" style="rounded=0;whiteSpace=wrap;html=1;" vertex="1" parent="NuuIC_HhkidKEVra6tKi-31">
<mxGeometry x="480" y="30" width="20" height="100" as="geometry" />
</mxCell>
<mxCell id="NuuIC_HhkidKEVra6tKi-26" value="" style="edgeStyle=orthogonalEdgeStyle;rounded=0;orthogonalLoop=1;jettySize=auto;html=1;" edge="1" parent="NuuIC_HhkidKEVra6tKi-31" source="NuuIC_HhkidKEVra6tKi-10" target="NuuIC_HhkidKEVra6tKi-25">
<mxGeometry relative="1" as="geometry" />
</mxCell>
<mxCell id="NuuIC_HhkidKEVra6tKi-10" value="P&lt;div&gt;P&lt;/div&gt;&lt;div&gt;T在线答辩&lt;/div&gt;" style="rounded=0;whiteSpace=wrap;html=1;" vertex="1" parent="NuuIC_HhkidKEVra6tKi-31">
<mxGeometry x="530" y="30" width="20" height="100" as="geometry" />
</mxCell>
<mxCell id="NuuIC_HhkidKEVra6tKi-12" value="每个队伍、每个阶段的基本数据（阶段、任务、积分）相互公开" style="rounded=0;whiteSpace=wrap;html=1;" vertex="1" parent="NuuIC_HhkidKEVra6tKi-31">
<mxGeometry x="80" width="470" height="20" as="geometry" />
</mxCell>
<mxCell id="NuuIC_HhkidKEVra6tKi-13" value="" style="endArrow=classic;html=1;rounded=0;" edge="1" parent="NuuIC_HhkidKEVra6tKi-31">
<mxGeometry width="50" height="50" relative="1" as="geometry">
<mxPoint x="30" y="79.70999999999998" as="sourcePoint" />
<mxPoint x="70" y="79.70999999999998" as="targetPoint" />
</mxGeometry>
</mxCell>
<mxCell id="NuuIC_HhkidKEVra6tKi-14" value="队伍" style="shape=umlActor;verticalLabelPosition=bottom;verticalAlign=top;html=1;outlineConnect=0;" vertex="1" parent="NuuIC_HhkidKEVra6tKi-31">
<mxGeometry y="50" width="20" height="50" as="geometry" />
</mxCell>
<mxCell id="NuuIC_HhkidKEVra6tKi-15" value="" style="endArrow=classic;html=1;rounded=0;" edge="1" parent="NuuIC_HhkidKEVra6tKi-31">
<mxGeometry width="50" height="50" relative="1" as="geometry">
<mxPoint x="100" y="79.70999999999998" as="sourcePoint" />
<mxPoint x="140" y="79.70999999999998" as="targetPoint" />
</mxGeometry>
</mxCell>
<mxCell id="NuuIC_HhkidKEVra6tKi-16" value="" style="endArrow=classic;html=1;rounded=0;exitX=1;exitY=0.5;exitDx=0;exitDy=0;entryX=0;entryY=0.5;entryDx=0;entryDy=0;" edge="1" parent="NuuIC_HhkidKEVra6tKi-31" source="NuuIC_HhkidKEVra6tKi-2" target="NuuIC_HhkidKEVra6tKi-3">
<mxGeometry width="50" height="50" relative="1" as="geometry">
<mxPoint x="110" y="89.70999999999998" as="sourcePoint" />
<mxPoint x="150" y="89.70999999999998" as="targetPoint" />
</mxGeometry>
</mxCell>
<mxCell id="NuuIC_HhkidKEVra6tKi-17" value="" style="endArrow=classic;html=1;rounded=0;exitX=1;exitY=0.5;exitDx=0;exitDy=0;entryX=0;entryY=0.5;entryDx=0;entryDy=0;" edge="1" parent="NuuIC_HhkidKEVra6tKi-31" target="NuuIC_HhkidKEVra6tKi-4">
<mxGeometry width="50" height="50" relative="1" as="geometry">
<mxPoint x="220" y="79.70999999999998" as="sourcePoint" />
<mxPoint x="250" y="80" as="targetPoint" />
</mxGeometry>
</mxCell>
<mxCell id="NuuIC_HhkidKEVra6tKi-18" value="" style="endArrow=classic;html=1;rounded=0;entryX=0;entryY=0.5;entryDx=0;entryDy=0;" edge="1" parent="NuuIC_HhkidKEVra6tKi-31" source="NuuIC_HhkidKEVra6tKi-4" target="NuuIC_HhkidKEVra6tKi-6">
<mxGeometry width="50" height="50" relative="1" as="geometry">
<mxPoint x="270" y="79.70999999999998" as="sourcePoint" />
<mxPoint x="300" y="80" as="targetPoint" />
</mxGeometry>
</mxCell>
<mxCell id="NuuIC_HhkidKEVra6tKi-25" value="结束&lt;div&gt;结算&lt;/div&gt;" style="ellipse;whiteSpace=wrap;html=1;aspect=fixed;" vertex="1" parent="NuuIC_HhkidKEVra6tKi-31">
<mxGeometry x="590" y="60" width="40" height="40" as="geometry" />
</mxCell>
</root>
</mxGraphModel>
</diagram>
</mxfile>

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.vscode
**/__pycache__/
**.pytest_cache/
*.fst
*.fst.hier
*.log
*.dat
**/UT_*
NemuBR/
report/
reports/

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木兰宽松许可证, 第2版
木兰宽松许可证， 第2版
2020年1月 http://license.coscl.org.cn/MulanPSL2
您对“软件”的复制、使用、修改及分发受木兰宽松许可证，第2版（“本许可证”）的如下条款的约束：
0. 定义
“软件”是指由“贡献”构成的许可在“本许可证”下的程序和相关文档的集合。
“贡献”是指由任一“贡献者”许可在“本许可证”下的受版权法保护的作品。
“贡献者”是指将受版权法保护的作品许可在“本许可证”下的自然人或“法人实体”。
“法人实体”是指提交贡献的机构及其“关联实体”。
“关联实体”是指，对“本许可证”下的行为方而言，控制、受控制或与其共同受控制的机构，此处的控制是指有受控方或共同受控方至少50%直接或间接的投票权、资金或其他有价证券。
1. 授予版权许可
每个“贡献者”根据“本许可证”授予您永久性的、全球性的、免费的、非独占的、不可撤销的版权许可，您可以复制、使用、修改、分发其“贡献”，不论修改与否。
2. 授予专利许可
每个“贡献者”根据“本许可证”授予您永久性的、全球性的、免费的、非独占的、不可撤销的（根据本条规定撤销除外）专利许可，供您制造、委托制造、使用、许诺销售、销售、进口其“贡献”或以其他方式转移其“贡献”。前述专利许可仅限于“贡献者”现在或将来拥有或控制的其“贡献”本身或其“贡献”与许可“贡献”时的“软件”结合而将必然会侵犯的专利权利要求，不包括对“贡献”的修改或包含“贡献”的其他结合。如果您或您的“关联实体”直接或间接地，就“软件”或其中的“贡献”对任何人发起专利侵权诉讼（包括反诉或交叉诉讼）或其他专利维权行动，指控其侵犯专利权，则“本许可证”授予您对“软件”的专利许可自您提起诉讼或发起维权行动之日终止。
3. 无商标许可
“本许可证”不提供对“贡献者”的商品名称、商标、服务标志或产品名称的商标许可，但您为满足第4条规定的声明义务而必须使用除外。
4. 分发限制
您可以在任何媒介中将“软件”以源程序形式或可执行形式重新分发，不论修改与否，但您必须向接收者提供“本许可证”的副本，并保留“软件”中的版权、商标、专利及免责声明。
5. 免责声明与责任限制
“软件”及其中的“贡献”在提供时不带任何明示或默示的担保。在任何情况下，“贡献者”或版权所有者不对任何人因使用“软件”或其中的“贡献”而引发的任何直接或间接损失承担责任，不论因何种原因导致或者基于何种法律理论，即使其曾被建议有此种损失的可能性。
6. 语言
“本许可证”以中英文双语表述，中英文版本具有同等法律效力。如果中英文版本存在任何冲突不一致，以中文版为准。
条款结束
如何将木兰宽松许可证，第2版，应用到您的软件
如果您希望将木兰宽松许可证，第2版，应用到您的新软件，为了方便接收者查阅，建议您完成如下三步：
1， 请您补充如下声明中的空白，包括软件名、软件的首次发表年份以及您作为版权人的名字；
2， 请您在软件包的一级目录下创建以“LICENSE”为名的文件，将整个许可证文本放入该文件中；
3， 请将如下声明文本放入每个源文件的头部注释中。
Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
XiangShan is licensed under Mulan PSL v2.
You can use this software according to the terms and conditions of the Mulan PSL v2.
You may obtain a copy of Mulan PSL v2 at:
http://license.coscl.org.cn/MulanPSL2
THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
See the Mulan PSL v2 for more details.
Mulan Permissive Software License，Version 2
Mulan Permissive Software License，Version 2 (Mulan PSL v2)
January 2020 http://license.coscl.org.cn/MulanPSL2
Your reproduction, use, modification and distribution of the Software shall be subject to Mulan PSL v2 (this License) with the following terms and conditions:
0. Definition
Software means the program and related documents which are licensed under this License and comprise all Contribution(s).
Contribution means the copyrightable work licensed by a particular Contributor under this License.
Contributor means the Individual or Legal Entity who licenses its copyrightable work under this License.
Legal Entity means the entity making a Contribution and all its Affiliates.
Affiliates means entities that control, are controlled by, or are under common control with the acting entity under this License, ‘control’ means direct or indirect ownership of at least fifty percent (50%) of the voting power, capital or other securities of controlled or commonly controlled entity.
1. Grant of Copyright License
Subject to the terms and conditions of this License, each Contributor hereby grants to you a perpetual, worldwide, royalty-free, non-exclusive, irrevocable copyright license to reproduce, use, modify, or distribute its Contribution, with modification or not.
2. Grant of Patent License
Subject to the terms and conditions of this License, each Contributor hereby grants to you a perpetual, worldwide, royalty-free, non-exclusive, irrevocable (except for revocation under this Section) patent license to make, have made, use, offer for sale, sell, import or otherwise transfer its Contribution, where such patent license is only limited to the patent claims owned or controlled by such Contributor now or in future which will be necessarily infringed by its Contribution alone, or by combination of the Contribution with the Software to which the Contribution was contributed. The patent license shall not apply to any modification of the Contribution, and any other combination which includes the Contribution. If you or your Affiliates directly or indirectly institute patent litigation (including a cross claim or counterclaim in a litigation) or other patent enforcement activities against any individual or entity by alleging that the Software or any Contribution in it infringes patents, then any patent license granted to you under this License for the Software shall terminate as of the date such litigation or activity is filed or taken.
3. No Trademark License
No trademark license is granted to use the trade names, trademarks, service marks, or product names of Contributor, except as required to fulfill notice requirements in Section 4.
4. Distribution Restriction
You may distribute the Software in any medium with or without modification, whether in source or executable forms, provided that you provide recipients with a copy of this License and retain copyright, patent, trademark and disclaimer statements in the Software.
5. Disclaimer of Warranty and Limitation of Liability
THE SOFTWARE AND CONTRIBUTION IN IT ARE PROVIDED WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR IMPLIED. IN NO EVENT SHALL ANY CONTRIBUTOR OR COPYRIGHT HOLDER BE LIABLE TO YOU FOR ANY DAMAGES, INCLUDING, BUT NOT LIMITED TO ANY DIRECT, OR INDIRECT, SPECIAL OR CONSEQUENTIAL DAMAGES ARISING FROM YOUR USE OR INABILITY TO USE THE SOFTWARE OR THE CONTRIBUTION IN IT, NO MATTER HOW IT’S CAUSED OR BASED ON WHICH LEGAL THEORY, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
6. Language
THIS LICENSE IS WRITTEN IN BOTH CHINESE AND ENGLISH, AND THE CHINESE VERSION AND ENGLISH VERSION SHALL HAVE THE SAME LEGAL EFFECT. IN THE CASE OF DIVERGENCE BETWEEN THE CHINESE AND ENGLISH VERSIONS, THE CHINESE VERSION SHALL PREVAIL.
END OF THE TERMS AND CONDITIONS
How to Apply the Mulan Permissive Software License，Version 2 (Mulan PSL v2) to Your Software
To apply the Mulan PSL v2 to your work, for easy identification by recipients, you are suggested to complete following three steps:
i Fill in the blanks in following statement, including insert your software name, the year of the first publication of your software, and your name identified as the copyright owner;
ii Create a file named “LICENSE” which contains the whole context of this License in the first directory of your software package;
iii Attach the statement to the appropriate annotated syntax at the beginning of each source file.
Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
XiangShan is licensed under Mulan PSL v2.
You can use this software according to the terms and conditions of the Mulan PSL v2.
You may obtain a copy of Mulan PSL v2 at:
http://license.coscl.org.cn/MulanPSL2
THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
See the Mulan PSL v2 for more details.

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export TL ?= python
export WAVE ?= true
export VERBOSE ?= false
export EXAMPLE ?= false
export TARGET
default:
@echo "Usage"
@echo " test: run tests, use TEST=test_name specify test folder in tests, default test all tests"
@echo " uftb: build uFTB DUT module"
@echo " tage_sc: build TAGE_SC DUT module"
@echo " ftb: build FTB DUT module"
@echo " ras: build RAS DUT module"
@echo " ittage: build ITTAGE DUT module"
@echo " all: build all DUTs"
@echo "Make examples:"
@echo " make test TEST=uFTB-raw"
@echo " make uftb"
test:
make -f tests/Makefile
uftb:
make -f ./mk/uFTB.mk uftb
tage_sc:
make -f ./mk/Tage.mk tage_sc
ftb:
make -f ./mk/FTB.mk ftb
ras:
make -f ./mk/RAS.mk ras
ittage:
make -f ./mk/ITTAGE.mk ittage
bputop:
make -f ./mk/BPUTop.mk BPUTop
filter:
cat log|grep Cannot |awk '{print $8}'| sort| uniq|tr -d "'"
all: uftb tage_sc ftb ras ittage

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# UnityChipVerification
开源高性能处理器核香山之开放验证挑战赛旨在通过基于Python的分支预测器验证任务，降低芯片验证门槛，培养芯片验证人才。赛事依托开源芯片社区平台，提供学习文档、技术培训及丰富的奖项和实习机会，推动开源芯片技术的发展。
## 报名步骤
CCF开源创新大赛报名：
## 相关资源链接
开放验证主页：https://www.gitlink.org.cn/XS-MLVP
开源开放验证官网：https://open-verify.cc
香山微架构开放验证第一期：昆明湖BPU模块UT验证实战：
https://www.gitlink.org.cn/XS-MLVP/env-xs-ov-00-bpu
## 项目意义
开源芯片验证项目将软件测试的众包模式引入芯片验证，利用开源社区的力量，共同参与芯片验证工作。通过降低验证复杂度和成本，促进芯片技术的发展和创新。同时，使用基于Python的高级语言验证工具，使更多软件开发人员能够参与芯片开发。
## 发展背景
芯片设计源代码是企业的核心机密，传统验证方法需要在严格保密环境下由内部验证工程师完成，成本高昂。开源芯片，如香山处理器核，公开所有源代码，任何人都可以访问。基于此，启动了开源芯片验证项目，目标是建立一个类似Hugging Face的开源社区，让更多人参与芯片验证。尽管面临开发者基数小、验证环境复杂等挑战，但通过开源模式的“三步走”规划，逐步实现社区参与芯片验证的目标。这将彻底改变芯片验证模式，促进敏捷硬件设计和开源硬件的发展。

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# The first phase of Open Verification for the Kunminghu microarchitecture of Xiangshan: Kunminghu's BPU Module UT Verification in Action.
[中文文档](./Readme_cn.md)
This project aims to explore open-sourced subdivision verification of the high-performance open-source RISC-V OpenXiangshan processor's microarchitecture. It introduces new tools and methods based on Python, enabling all students interested in chip design and verification to quickly grasp and study the XiangShan microarchitecture. This phase provides a detailed introduction to the principles and implementation of the branch prediction module of the XiangShan Kunminghu architecture, along with the corresponding open-source verification environment. Participants in this phase can earn points and rewards by submitting bugs, writing verification reports, and more.
**The Open Verification Porject website：[open-verify.cc](https://open-verify.cc/en/)**
## Introduction
This project utilizes open-source tools for the open verification of open-source chips. The focus of the current phase is the BPU module within the XiangShan Kunminghu microarchitecture.
## Kunminghu microarchitecture
The Kunminghu architecture is the third-generation high-performance microarchitecture of the XiangShan open-source processor. For the architecture diagram, please refer to the [Kunminghu architecture diagram](https://github.com/OpenXiangShan/XiangShan/raw/kunminghu/images/xs-arch-nanhu.svg).
## Chip verification
Chip validation is a crucial aspect of chip design work. Skipping or insufficient validation can result in chip fabrication failures or products not meeting standards, leading to significant losses. Chip design companies treat chip design as proprietary business secrets, and chip validation typically requires access to the chip design source code. Therefore, chip validation work can only be conducted internally within the company. However, with the open-source nature of the Shanhai high-performance RISC-V chip, concerns about "leaking proprietary secrets" do not arise. Consequently, chip validation work can be distributed in a manner similar to software subcontracting or crowdsourcing, allowing interested individuals to participate remotely.
## Learning resources
1. [Basic Learning Materials](https://open-verify.cc/mlvp/en/docs/): Learn about chip validation and how to use Python for validation.
1. [Introduction to Shanhai BPU](https://open-verify.cc/xs-bpu/en/docs/): Learn about branch prediction and the basic predictors used in the Shanhai processor.
1. [How to Participate in This Activity](/doc/join_en.md): Learn how to participate in this activity and the rules.
1. [Building Verification Environment](/doc/env_en.md): Learn how to set up the basic verification environment, how to validate, and submit validation results.
**<font color="blue">To accelerate the verification process, the verification environment has provided the following reusable features:</font>**
<font color="blue">
- Python DUT: Python module corresponding to each module to be verified
- FakeFTQ: A general interface for driving BPU, providing operations such as redirect and update
- BPU Trace: Branch jump data of real applications
- Pytest environment: Drive tests through pytest, generate test reports, provide code line coverage, and function coverage support
For details, please refer to the test Demo: [uFTB-raw](/tests/uFTB-raw/README.md), [uFTB-with-ftq](/tests/uFTB-with-ftq/README.md)
</font>
## Repository Directory
The structure of this repository directory and corresponding explanations are as follows:
```bash
.
├── doc
├── image
├── LICENSE
├── Makefile
├── mk # Sub Makefiles
├── Readme_cn.md
├── Readme.md
├── tests # Tests dir <- put your test code here !
│   ├── Makefile # Test Makefile
│   ├── conftest.py # Pytest config
│   ├── README.md # Test readme
│   ├── uFTB_raw # Example 1
│   └── uftb-with-ftq # Example 2
└── utils # Tools you may need
├── BRTParser # Branc trace parser
└── ready-to-run # Binary files to run (trace source)
```
**Note: Since this project requires submitting results via PR, please make sure to organize the data according to the directory requirements mentioned above.**
## Join Us
Please visit the following link to sign up for this event.
[Sign up](https://iz9a87wn37.feishu.cn/share/base/form/shrcnwpiyWaVUzyo47QdPBGy5Yd)
## The QQ discussion group: 600480230
<image src="/.github/image/600480230.jpg" alter="600480230" width=500px />

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# 香山微架构开放验证第一期：昆明湖BPU模块UT验证实战
**[English Readme](/Readme.md)**
本项目的目标是对高性能开源RISC-V香山处理器的微架构进行开放式分包验证的探索。它提供了基于Python的新工具、新方法，让所有对芯片设计与验证感兴趣的同学能够快速了解香山微架构，学习香山微架构。本期活动对香山昆明湖架构的分支预测模块的原理以及实现进行了详细介绍，并提供了对应的开源验证环境。参本次活动的同学，通过提交Bug、编写验证报告等获取积分与奖励。
**开源开放验证官网：[open-verify.cc](https://open-verify.cc)**
## 简介
本项目是基于开源工具对开源芯片进行的开源开放验证。本期验证的对象是香山昆明湖微架构中的BPU模块。
### 昆明湖微架构
昆明湖架构是香山开源处理器的第三代高性能微架构，架构图请参考：[昆明湖架构图](https://github.com/OpenXiangShan/XiangShan/raw/kunminghu/images/xs-arch-nanhu.svg)。
### 芯片验证
芯片验证是芯片设计工作中的重点，跳过验证或者验证的不够，会导致流片失败或者芯片产品不达标，带来巨大损失。芯片设计公司把芯片设计当成核心商业机密，而芯片验证通常需要基于芯片设计源代码，因此芯片验证工作只能在公司内部进行。开源香山高性能risc-v芯片不存在“商业机密泄露”等问题，因此可以把芯片验证工作以类似软件分包、众包的方式进行分发，让感兴趣的人远程参与。
## 学习材料
1. **[基础学习材料](https://open-verify.cc/mlvp/docs/)**，学习什么是芯片验证，如何使用Python进行验证
1. **[香山BPU介绍](https://open-verify.cc/xs-bpu/docs/)**，学习什么是分支预测，香山处理器中采用了哪些基础预测器
1. **[如何参与本活动](/doc/join_cn.md)**，介绍如何参与本活动，有哪些活动规则
1. **[构建验证环境](/doc/env_cn.md)**，介绍基本验证环境搭建，如何进行验证和提交验证结果
**<font color="blue">为了加速验证过程，验证环境已经提供了如下可复用功能：</font>**
<font color="blue">
- Python DUT：各待验证模块对应的python module
- FakeFTQ：用于驱动BPU的通用接口，提供redirect、update等操作
- BPU Trace：真实应用的分支跳转数据
- Pytest环境：通过pytest驱动测试，生成测试报告，提供代码行覆盖率，功能覆盖率支持
具体请参考测试 Demo: [uFTB-raw](/tests/uFTB-raw/README.md)、[uFTB-with-ftq](/tests/uFTB-with-ftq/README.md)
</font>
## 本仓库目录
本仓库目录结构和对应说明如下：
```bash
.
├── doc # 仓库文档
├── image # 文档图片
├── LICENSE # 开源协议
├── Makefile # Makefile
├── mk # 子 Makefile
├── Readme_cn.md # 中文 Readme
├── Readme.md # 英文 Readme
├── tests # 测试用例 <- 在此目录添加测试用例
│   ├── Makefile # 测试用例 Makefile
│   ├── conftest.py # 测试用例配置
│   ├── README.md # 测试用例说明
│   ├── uFTB_raw # 测试用例1：uFTB_raw
│   └── uftb-with-ftq # 测试用例2：uftb-with-ftq
└── utils # 实用工具
├── BRTParser # 分支预测结果解析工具
└── ready-to-run # 可供在模拟器中执行的程序
```
**注：由于本项目是以PR的方式提交结果，所以请务必按照上述目录要求进行数据组织**
## 报名链接
请访问以下链接报名参与本活动：
[报名问卷](https://iz9a87wn37.feishu.cn/share/base/form/shrcnwpiyWaVUzyo47QdPBGy5Yd)
## 加入讨QQ论群: 600480230
<image src="/.github/image/600480230.jpg" alter="600480230" width=500px />

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# BPU验证环境
本环境提供BPU验证所需的所有依赖，以及工具包。本验证环境需要在linux系统下运行，包含以下组件
1. 生成待验证的 Python DUT 模块
2. 对DUT进行验证的示例项目
3. 生成验证报告的组件
待验证项目：
- 待验证模块：[XiangShan 545d7b](https://github.com/OpenXiangShan/XiangShan/tree/545d7be08861a078dc54ccc114bf1792e894ab54)
## 安装依赖
除去基本的gcc/python3开发环境外，本验仓库还依赖如下两个项目，请先行安装，**并安装对应项目的依赖**。
1. [picker](https://github.com/XS-MLVP/picker)
2. [mlvp](https://github.com/XS-MLVP/mlvp)
再通过以下命令安装其他依赖：
```bash
apt install lcov # genhtml
pip install pytest-sugar pytest-rerunfailures pytest-xdist pytest-assume pytest-html # pytest
```
## 生成待验证模块
下载仓库
```bash
git clone https://github.com/XS-MLVP/env-xs-ov-00-bpu.git
cd env-xs-ov-00-bpu
```
### 生成 uFTB
```bash
make uftb TL=python
```
上述命令会在当前目录中生成out目录，其中 picker_out_uFTB 目录下的 UT_FauFTB 即为待验证的Python Module。可以在python环境中直接导入。因为待验证的python DUT与python版本相关，所以无法提供通用版本的python-dut，需要自行编译。
```bash
out
`-- picker_out_uFTB
`-- UT_FauFTB
|-- _UT_FauFTB.so
|-- __init__.py
|-- libDPIFauFTB.a
|-- libUTFauFTB.so
|-- libUT_FauFTB.py
|-- uFTB.fst.hier
`-- xspcomm
|-- __init__.py
|-- __pycache__
| |-- __init__.cpython-38.pyc
| `-- pyxspcomm.cpython-38.pyc
|-- _pyxspcomm.so -> _pyxspcomm.so.0.0.1
|-- _pyxspcomm.so.0.0.1
|-- info.py
`-- pyxspcomm.py
4 directories, 13 files
```
当导入模块UT_FauFTB后，可以在Python环境中进行简单测试。
```python
from UT_FauFTB import *
if __name__ == "__main__":
# Create DUT
uftb = DUTFauFTB()
# Init DUT with clock pin name
uftb.InitClock("clock")
# Your testcases here
# ...
# Destroy DUT
utb.Finish()
```
其他待验证模块，例如 TAGE-SC，FTB也可以通过类似命令生成。
**支持的模块名称有：uftb、tage_sc、ftb、ras、ittage。也可以通过如下命令，一次性生成所有DUT模块。**
```bash
make all TL=python
```
## BPU外围环境
BPU是CPU中的一个模块，本环境提供了其所需的外围环境来驱动BPU执行trace数据（**具体验证时，可根据实际情况选择是否使用**）。
### 分支 Trace 工具：BRTParser
BRTParser 使我们专门为 BPU 验证所设计的能够自动抓取、解析程序指令流中的分支信息的工具，它基于香山前端的开发工具 `OracleBP`。 BRTParser 内部集成了 NEMU 模拟器，可以直接运行程序，并在其中抓取分支信息。BRTParser 会将抓取到的分支信息解析成一种通用的格式，方便后续的验证工作。
具体请参见 `utils` 目录下的 `BRTParser`。
### FTQ 运行环境
由于单独的子预测器模块并无法运行真实的程序，更无法验证其在实际程序中的预测准确率与功能正确性。因此，我们提供了一个简易的 FTQ 环境，该环境使用了 BRTParser 生成的分支信息来生成程序指令执行流。FTQ 将会解析预测器的预测结果，并与实际的分支信息进行比对，从而验证预测器的准确性。另外，FTQ 还会向 BPU 发出重定向信息与更新信息，使得预测器可以在 FTQ 的环境中不间断运行。
为了使一个子预测器能够正常工作，我们还模拟了 BPU 顶层模块，为子预测器提供时序控制等功能。对于非 FTB 类型的子预测器，我们还提供了一个简易的 FTB 实现，用于向子预测器结果中添加 FTB 基础预测结果信息。
目前，我们使用 FTQ 环境驱动了 uFTB 子预测器，并编写了时序精确的 uFTB 参考模型。FTQ 环境的具体实现和使用方法都可以在这个测试用例中获取，详见 `test_src/uFTB-with-ftq`。
## 编写测试用例
参与验证的同学需要编写测试用例，以验证 BPU 子模块的功能正确性，在本仓库中，所有的测试用例都需要被放置在 `tests` 目录下。
我们基于 pytest 提供了一套测试用例的运行框架，可以方便地编写测试用例、定义功能覆盖率、生成测试报告等，因此在编写测试用例时，需要遵循本节中介绍的一些规范。
### 运行测试
我们已经为 uFTB 提供了两个基础的测试用例，每个测试用例被放置在 `tests` 目录下单独的子目录中，子目录名称即为测试用例的名称。在运行测试这两个测试用例之前，请确保 uFTB 模块己经被正确编译，并且测试用例需要的依赖已经被安装。
之后，便可运行相应测试用例。以运行 `uFTB_raw` 测试用例为例，只需在 `tests` 目录下运行如下命令即可：
```bash
make TEST=uFTB_raw run
```
该命令会自动运行 `uFTB_raw` 测试用例，并生成波形、覆盖率和测试报告等信息。测试报告会被保存在 `tests/report` 目录中，可通过浏览器打开 `tests/report/report.html` 查看本次测试报告内容，测试报告样式如下图所示，其余文件也会在 `tests` 目录下生成。
<div style="text-align: center;">
<img src="/.github/image/test-report.png" width="700">
</div>
若需要一次性运行所有测试用例，可以运行如下命令：
```bash
make run
```
此时生成的测试报告会包含所有测试用例的测试结果。
### 添加测试用例
在编写自己的测试用例时，只需要在 `tests` 目录下新建一个子目录以作为新测试用例的目录，子目录的名称命名为测试用例的名称。你可以在该目录下添加任意的代码文件，只需要保证测试用例的入口文件为 `test_<测试名称>.py`，在该文件中，测试用例的入口函数也需要被命名为 `test_<测试名称>`。你可以编写一个或多个入口文件和入口函数。
在每个入口函数中，需要遵循如下的格式：
```python
import mlvp.funcov as fc
from mlvp.reporter import set_func_coverage, set_line_coverage
def test_mydut(request):
# 创建 DUT，并指定本次测试的波形文件和覆盖率文件名称
# 请注意，每个测试函数所对应的波形文件及覆盖率文件名称应该互不相同，否则会导致文件被覆盖
my_dut = DUTMydut(waveform_filename="my_test.fst", coverage_filename="my_test_coverage.dat")
# 指定功能覆盖规则
g1 = fc.CovGroup("group1")
# ...
g2 = fc.CovGroup("group2")
# ...
# 测试运行代码
# ...
# 结束测试，并录入覆盖率信息，覆盖率文件名称应该与上述指定的覆盖率文件名称相同
my_dut.Finish()
set_func_coverage(request, [g1, g2])
set_line_coverage(request, "my_test_coverage.dat")
```
测试用例编写完成后，可以直接在 `tests` 目录运行：
```python
make TEST=<测试用例名> run
```
即可自动完成测试用例的运行、波形生成、覆盖率统计和测试报告生成等工作。
当本地测试通过后，即可提交测试用例。提交时，测试报告中的测试结果需满足以下要求：
1. 所有测试用例均通过
2. 代码行覆盖率大于 95%
3. 功能覆盖率达到 100%
### 日志输出
在 mlvp 库中，提供了一个专用的日志记录器(logger)，我们推荐使用该 logger 来记录测试过程中的信息。
具体地，你可以使用如下的方式来记录日志：
```python
import mlvp
mlvp.debug("This is a debug message", extra={"log_id": "dut"})
mlvp.info("This is an info message")
mlvp.warning("This is a warning message", extra={"log_id": "bundle"})
mlvp.error("This is an error message")
mlvp.critical("This is a critical message")
```
如果需要改变日志记录格式、日志级别以及写入文件等信息，可通过调用 `mlvp` 库中的 `setup_logging` 函数进行设置：
```python
def setup_logging(
log_level =logging.INFO,
format=default_format,
console_display=True,
log_file=None)
```
## 建议验证流程（必读）
**1. 阅读文档，梳理测试点。** 阅读BPU文档时可对功能点进行梳理和细化。
**2. 阅读代码，封装并驱动DUT。** 代码中包含了所有实现细节，基于其可对DUT的基本功能封装为一个个函数。然后测试这些函数功能是否正常。
**3. 根据测试点编写对应测试用例。** 基于测点和DUT基本功能函数，完成绝大部分功能的测试。（**不要一来就写参考模型**）
**4. 编写参考模型。** 当所有基本功能点都测试完成后，再基于自己理解完成参考模型编写。（如果所有功能点都完成测试，且功能、代码行覆盖率已达到要求，可忽略参考模型）
**5. 随机全系统测试。** 同时随机驱动DUT和参考模型，对比测试结果。进行覆盖率分析，并构造特定输入提升覆盖率。
**6. 编写测试报告。** 按照基础文档中的报告格式要求完成文档撰写。
*注：在上述验证过程中，如果发现bug可随时通过PR进行提交

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# BPU Verification Environment
This environment provides all dependencies and toolkits required for BPU verification. This verification environment needs to run under the Linux system and includes the following components:
1. Generate the Python DUT module to be verified
2. Example project for DUT verification
3. Component to generate verification report
Project to be verified:
- Module to be verified: [XiangShan 545d7b](https://github.com/OpenXiangShan/XiangShan/tree/545d7be08861a078dc54ccc114bf1792e894ab54)
## Install Dependencies
In addition to the basic gcc/python3 development environment, this repository also depends on the following two projects. Please install them first, **and install the dependencies of the corresponding projects**.
1. [picker](https://github.com/XS-MLVP/picker)
2. [mlvp](https://github.com/XS-MLVP/mlvp)
Then install other dependencies through the following command:
```bash
apt install lcov # genhtml
pip install pytest-sugar pytest-rerunfailures pytest-xdist pytest-assume pytest-html # pytest
```
## Generate Module to be Verified
Download the repository
```bash
git clone https://github.com/XS-MLVP/env-xs-ov-00-bpu.git
cd env-xs-ov-00-bpu
```
### Generate uFTB
```bash
make uftb TL=python
```
The above command will generate an out directory in the current directory, and the UT_FauFTB in the picker_out_uFTB directory is the Python Module to be verified. It can be directly imported in the python environment. Because the Python DUT to be verified is related to the python version, a universal version of python-dut cannot be provided, and it needs to be compiled by yourself.
```bash
out
`-- picker_out_uFTB
`-- UT_FauFTB
|-- _UT_FauFTB.so
|-- __init__.py
|-- libDPIFauFTB.a
|-- libUTFauFTB.so
|-- libUT_FauFTB.py
|-- uFTB.fst.hier
`-- xspcomm
|-- __init__.py
|-- __pycache__
| |-- __init__.cpython-38.pyc
| `-- pyxspcomm.cpython-38.pyc
|-- _pyxspcomm.so -> _pyxspcomm.so.0.0.1
|-- _pyxspcomm.so.0.0.1
|-- info.py
`-- pyxspcomm.py
4 directories, 13 files
```
After importing the UT_FauFTB module, you can perform simple tests in the Python environment.
```python
from UT_FauFTB import *
if __name__ == "__main__":
# Create DUT
uftb = DUTFauFTB()
# Init DUT with clock pin name
uftb.InitClock("clock")
# Your testcases here
# ...
# Destroy DUT
utb.Finish()
```
Other modules to be verified, such as TAGE-SC, FTB can also be generated by similar commands.
**Supported module names are: uftb, tage_sc, ftb, ras, ittage. You can also generate all DUT modules at once with the following command.**
```bash
make all TL=python
```
## BPU Peripheral Environment
BPU is a module in the CPU. This environment provides the peripheral environment required for it to drive the BPU to execute trace data (**when verifying, you can choose whether to use it according to the actual situation**).
### Branch Trace Tool: BRTParser
BRTParser is a tool we specifically designed for BPU verification that can automatically capture and parse branch information in the program instruction stream. It is based on the Xiangshan frontend development tool `OracleBP`. BRTParser integrates the NEMU simulator internally, can directly run programs, and capture branch information in it. BRTParser will parse the captured branch information into a universal format, which is convenient for subsequent verification work.
Please refer to `BRTParser` in the `utils` directory for details.
### FTQ Running Environment
Since a single sub-predictor module cannot run real programs, it is even more impossible to verify its prediction accuracy and functional correctness in actual programs. Therefore, we provide a simple FTQ environment. This environment uses the branch information generated by BRTParser to generate the program instruction execution stream. FTQ will parse the predictor's prediction results and compare them with the actual branch information to verify the accuracy of the predictor. In addition, FTQ will also issue redirection information and update information to the BPU, so that the predictor can run continuously in the FTQ environment.
In order for a sub-predictor to work normally, we also simulated the BPU top-level module to provide timing control and other functions for the sub-predictor. For non-FTB type sub-predictors, we also provide a simple FTB implementation, which is used to add FTB basic prediction result information to the sub-predictor result.
Currently, we use the FTQ environment to drive the uFTB sub-predictor and have written a timing-accurate uFTB reference model. The specific implementation and usage of the FTQ environment can be obtained in this test case, see `test_src/uFTB-with-ftq` for details.
## Write Test Cases
Participants in the verification need to write test cases to verify the functional correctness of the BPU sub-module. In this repository, all test cases need to be placed in the `tests` directory.
We provide a test case running framework based on pytest, which can easily write test cases, define function coverage, generate test reports, etc. Therefore, when writing test cases, you need to follow some specifications introduced in this section.
### Running Tests
We have provided two basic test cases for uFTB, each test case is placed in a separate subdirectory under the [`tests`](command:_github.copilot.openRelativePath?%5B%7B%22scheme%22%3A%22file%22%2C%22authority%22%3A%22%22%2C%22path%22%3A%22%2Fhome%2Fyaozhicheng%2Fworkspace%2Fenv-xs-ov-00-bpu%2Ftests%22%2C%22query%22%3A%22%22%2C%22fragment%22%3A%22%22%7D%5D "/home/yaozhicheng/workspace/env-xs-ov-00-bpu/tests") directory, and the subdirectory name is the name of the test case. Before running these two test cases, please ensure that the uFTB module has been correctly compiled and the dependencies required for the test case have been installed.
Afterwards, you can run the corresponding test cases. For example, to run the `uFTB_raw` test case, just run the following command in the [`tests`](command:_github.copilot.openRelativePath?%5B%7B%22scheme%22%3A%22file%22%2C%22authority%22%3A%22%22%2C%22path%22%3A%22%2Fhome%2Fyaozhicheng%2Fworkspace%2Fenv-xs-ov-00-bpu%2Ftests%22%2C%22query%22%3A%22%22%2C%22fragment%22%3A%22%22%7D%5D "/home/yaozhicheng/workspace/env-xs-ov-00-bpu/tests") directory:
```bash
make TEST=uFTB_raw run
```
This command will automatically run the `uFTB_raw` test case and generate waveform, coverage, and test report information. The test report will be saved in the `tests/report` directory. You can open `tests/report/report.html` in your browser to view the content of this test report. The test report style is shown in the following figure, and other files will also be generated in the `tests` directory.
<div style="text-align: center;">
<img src="/.github/image/test-report.png" width="700">
</div>
If you need to run all test cases at once, you can run the following command:
```bash
make run
```
The generated test report will include the test results of all test cases.
### Adding Test Cases
When writing your own test cases, you only need to create a new subdirectory under the [`tests`](command:_github.copilot.openRelativePath?%5B%7B%22scheme%22%3A%22file%22%2C%22authority%22%3A%22%22%2C%22path%22%3A%22%2Fhome%2Fyaozhicheng%2Fworkspace%2Fenv-xs-ov-00-bpu%2Ftests%22%2C%22query%22%3A%22%22%2C%22fragment%22%3A%22%22%7D%5D "/home/yaozhicheng/workspace/env-xs-ov-00-bpu/tests") directory as the directory for the new test case. The name of the subdirectory should be the name of the test case. You can add any code files in this directory, just make sure that the entry file of the test case is `test_<test name>.py`. In this file, the entry function of the test case also needs to be named `test_<test name>`. You can write one or more entry files and entry functions.
In each entry function, you need to follow the format below:
```python
import mlvp.funcov as fc
from mlvp.reporter import set_func_coverage, set_line_coverage
def test_mydut(request):
# Create DUT, and specify the waveform file and coverage file name for this test
# Please note that the waveform file and coverage file names corresponding to each test function should be different, otherwise the files will be overwritten
my_dut = DUTMydut(waveform_filename="my_test.fst", coverage_filename="my_test_coverage.dat")
# Specify function coverage rules
g1 = fc.CovGroup("group1")
# ...
g2 = fc.CovGroup("group2")
# ...
# Test running code
# ...
# End the test, and enter the coverage information. The coverage file name should be the same as the coverage file name specified above
my_dut.Finish()
set_func_coverage(request, [g1, g2])
set_line_coverage(request, "my_test_coverage.dat")
```
After the test case is written, you can directly run in the `tests` directory:
```python
make TEST=<test case name> run
```
This will automatically complete the running of the test case, waveform generation, coverage statistics, and test report generation.
When the local test passes, you can submit the test case. When submitting, the test results in the test report need to meet the following requirements:
1. All test cases pass
2. Code line coverage is greater than 95%
3. Function coverage reaches 100%
### Log Output
In the mlvp library, a dedicated logger is provided. We recommend using this logger to record information during the test.
Specifically, you can record logs in the following way:
```python
import mlvp
mlvp.debug("This is a debug message", extra={"log_id": "dut"})
mlvp.info("This is an info message")
mlvp.warning("This is a warning message", extra={"log_id": "bundle"})
mlvp.error("This is an error message")
mlvp.critical("This is a critical message")
```
If you need to change the log recording format, log level, and write to file information, you can set it by calling the `setup_logging` function in the `mlvp` library:
```python
def setup_logging(
log_level =logging.INFO,
format=default_format,
console_display=True,
log_file=None)
```
## Suggested Verification Process (Must Read)
**1. Read the document and sort out the test points.** When reading the BPU document, you can sort out and refine the function points.
**2. Read the code, encapsulate and drive the DUT.** The code contains all implementation details, based on which you can encapsulate the basic functions of the DUT into individual functions. Then test whether these function features are normal.
**3. Write corresponding test cases based on the test points.** Based on the test points and DUT basic function functions, complete the testing of most functions. (**Don't write the reference model right away**)
**4. Write the reference model.** When all basic function points have been tested, you can complete the writing of the reference model based on your understanding. (If all function points have been tested and the function and code line coverage have met the requirements, the reference model can be ignored)
**5. Random full system testing.** At the same time, randomly drive the DUT and reference model, compare the test results. Perform coverage analysis and construct specific inputs to improve coverage.
**6. Write the test report.** Complete the document writing according to the report format requirements in the basic document.
*Note: During the above verification process, if you find a bug, you can submit it at any time through PR.

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## 如何参与本活动
参与本验证活动，取得名次能够获得丰厚大奖，[报名问卷](https://iz9a87wn37.feishu.cn/share/base/form/shrcnwpiyWaVUzyo47QdPBGy5Yd)
### 流程介绍
参与验证的流程如下图所示：
<img src="/.github/image/ov-pipline.svg" width="800px">
#### （0）在线报名
参加本活动的队伍队员数没有限制，可以是一个也可以是多个。最终奖金按队伍积分发放给队长，且在活动开放期间，队名和队长的名称会被群内公开。
#### （1）资格认证
为了对参赛队伍进行能力评估，本活动提供了数个具有已知bug的DUT让参加队伍进行验证测试，能发现其中的80%以上的bug并能进行原因分析的队伍才能获得获得参加资格。其中发现的bug数，也会变成对应的队伍积分。
#### （2）Fork仓库
Fork本仓库，然后在本地进行环境搭建，参与测试任务。
#### （3）领取任务
任务在本仓库Issue中进行描述，队长以Issue的方式在Issue下方进行报名。管理员会进行统计，然后群内发布公告。
#### （4）分解测试点与编写验证方案
测试点分解和验证方案是芯片验证过程中的重要步骤，直接影响验证结果。在本阶段，需要通过PR提交对应报告，组织方会对报告进行评审和打分。
#### （5）编写测试用例
测试用例编写，具体格式可以参考`tests`目录中的模板。测试用例需要覆盖到对应的测试点。
#### （6）编写测试代码&测试发现bug
测试过程中，发现bug后，需要对bug进行分析。
#### （7）通过Issue和PR汇报bug获得积分
可以通过PR随时进行bug提交，但是一天组织方只对一个队伍进行一次bug审查。组织方根据bug类型，等级发放对应积分。
#### （8）编写测试报告
参考模板 [NutShell Cache](https://open-verify.cc/mlvp/docs/basic/report/) 进行编写。
#### （9）PPT在线答辩
编写PPT在线进行对整个验证任务的答辩。答辩根据给队伍的完成情况集中组织。
## 基础任务
### 任务1. uFTB & TFB
源代码地址: [FauFTB.sv](https://github.com/XS-MLVP/env-xs-ov-00-bpu/tree/main/rtl/uFTB)
功能描述文档：[uFTB分支预测器](https://open-verify.cc/xs-bpu/docs/modules/01_uftb/)
参考功能点文档：[uFTB功能列表](https://open-verify.cc/xs-bpu/docs/feature/01_uftbfeature/)
源代码地址: [FTB.sv](https://github.com/XS-MLVP/env-xs-ov-00-bpu/tree/main/rtl/FTB)
功能描述文档：[FTB 分支预测器](https://open-verify.cc/xs-bpu/docs/modules/03_ftb/)
参考功能点文档：[FTB 功能列表](https://open-verify.cc/xs-bpu/docs/feature/02_ftbfeature/)
1. 完成对 uFTB 子预测器的代码及文档阅读，了解 uFTB 的工作原理及模块功能。明确 uFTB 使用的 FTB 项缓存的结构。
2. 根据给出的参考功能点，完善 uFTB 需要验证的功能点，并针对这些功能点分解出具体的测试点。同时解释每个测试点对验证功能点的意义。
3. 依据分解出的测试点，完成对 uFTB 的测试用例编写。测试用例需要覆盖到所有的测试点。同时，需要对测试用例进行详细的说明，包括测试用例的目的、输入、输出、预期结果及原理等。
4. 完成对 uFTB 的测试用例的代码编写，建议完成**参考模型的编写**。确保测试用例能够通过验证环境的运行。在编码的过程中，需要保证代码的质量，包括代码的可读性、可维护性、可扩展性等。
5. 完成对 uFTB 的测试用例的运行，生成测试报告。测试报告需要包括测试用例的运行结果、代码行覆盖率、功能覆盖率等信息。测试报告需要保存在 `tests/report` 目录中，可通过浏览器打开 `tests/report/uFTB-yourId.html` 查看本次测试报告内容。
6. 最终提交前，需要对测试报告进行检查，确保测试报告符合提交PR的基本要求。
### 任务2. TageSC
源代码地址: [TageSC.sv](https://github.com/XS-MLVP/env-xs-ov-00-bpu/tree/main/rtl/TageSC)
功能描述文档：[TAGE-SC 分支预测器](https://open-verify.cc/xs-bpu/docs/modules/02_tage_sc/)
参考功能点文档：[TAGE-SC 功能列表](https://open-verify.cc/xs-bpu/docs/feature/03_tagescfeature/)
1. 完成对 TageSC 子预测器的代码及文档阅读，了解 Tage 及 SC 单个模块的工作原理及功能，再了解 TageSC 整体模块的功能。明确使用的 Tage 表项及 SC 表项的结构，以及分支折叠历史的工作原理。
2. 根据给出的参考功能点，完善 Tage、SC、TageSC 需要验证的功能点，并针对这些功能点分解出具体的测试点。同时解释每个测试点对验证功能点的意义。
3. 依据分解出的测试点，完成对 TageSC 的测试用例编写。测试用例需要覆盖到所有的测试点。同时，需要对测试用例进行详细的说明，包括测试用例的目的、输入、输出、预期结果及原理等。
4. 完成对 TageSC 的测试用例的代码编写，要求完成**参考模型的编写**。确保测试用例能够通过验证环境的运行。在编码的过程中，需要保证代码的质量，包括代码的可读性、可维护性、可扩展性等。
5. 完成对 TageSC 的测试用例的运行，生成测试报告。测试报告需要包括测试用例的运行结果、代码行覆盖率、功能覆盖率等信息。测试报告需要保存在 `tests/report` 目录中，可通过浏览器打开 `tests/report/TageSC-yourId.html` 查看本次测试报告内容。
6. 最终提交前，需要对测试报告进行检查，确保测试报告符合提交PR的基本要求。
### 任务3. ITTAGE
源代码地址: [ITTAGE.sv](https://github.com/XS-MLVP/env-xs-ov-00-bpu/tree/main/rtl/ITTAGE)
功能描述文档：[ITTAGE 分支预测器](https://open-verify.cc/xs-bpu/docs/modules/04_ittage/)
参考功能点文档：[ITTAGE 功能列表](https://open-verify.cc/xs-bpu/docs/feature/04_ittagefeature/)
1. 完成对 ITTAGE 子预测器的代码及文档阅读，了解 ITTAGE 的工作原理及模块功能。明确 ITTAGE 使用的 Tage 表项的结构，了解 ITTAGE 的预测器结构。同时了解分支折叠历史的工作原理。
2. 根据给出的参考功能点，完善 ITTAGE 需要验证的功能点，并针对这些功能点分解出具体的测试点。同时解释每个测试点对验证功能点的意义。
3. 依据分解出的测试点，完成对 ITTAGE 的测试用例编写。测试用例需要覆盖到所有的测试点。同时，需要对测试用例进行详细的说明，包括测试用例的目的、输入、输出、预期结果及原理等。
4. 完成对 ITTAGE 的测试用例的代码编写，要求完成**参考模型的编写**。确保测试用例能够通过验证环境的运行。在编码的过程中，需要保证代码的质量，包括代码的可读性、可维护性、可扩展性等。
5. 完成对 ITTAGE 的测试用例的运行，生成测试报告。测试报告需要包括测试用例的运行结果、代码行覆盖率、功能覆盖率等信息。测试报告需要保存在 `tests/report` 目录中，可通过浏览器打开 `tests/report/ITTAGE-yourId.html` 查看本次测试报告内容。
6. 最终提交前，需要对测试报告进行检查，确保测试报告符合提交PR的基本要求。
### 任务4. RAS
源代码地址: [RAS.sv](https://github.com/XS-MLVP/env-xs-ov-00-bpu/tree/main/rtl/RAS)
功能描述文档：[RAS 分支预测器](https://open-verify.cc/xs-bpu/docs/modules/05_ras/)
参考功能点文档：[RAS 功能列表](https://open-verify.cc/xs-bpu/docs/feature/05_rasfeature/)
1. 完成对 RAS 子预测器的代码及文档阅读，了解 RAS 的工作原理及模块功能。了解程序运行时栈帧的工作原理，再明确 RAS 的 RAS 栈的工作原理。最明确 RAS 的预测器如何为 call 和 ret 指令提供预测。
2. 根据给出的参考功能点，完善 RAS 需要验证的功能点，并针对这些功能点分解出具体的测试点。同时解释每个测试点对验证功能点的意义。
3. 依据分解出的测试点，完成对 RAS 的测试用例编写。测试用例需要覆盖到所有的测试点。同时，需要对测试用例进行详细的说明，包括测试用例的目的、输入、输出、预期结果及原理等。
4. 完成对 RAS 的测试用例的代码编写，要求完成**参考模型的编写**。确保测试用例能够通过验证环境的运行。在编码的过程中，需要保证代码的质量，包括代码的可读性、可维护性、可扩展性等。
5. 完成对 RAS 的测试用例的运行，生成测试报告。测试报告需要包括测试用例的运行结果、代码行覆盖率、功能覆盖率等信息。测试报告需要保存在 `tests/report` 目录中，可通过浏览器打开 `tests/report/RAS-yourId.html` 查看本次测试报告内容。
6. 最终提交前，需要对测试报告进行检查，确保测试报告符合提交PR的基本要求。
### 任务5. BPU Top
源代码地址: [Predictor.sv & Composer.sv](https://github.com/XS-MLVP/env-xs-ov-00-bpu/tree/main/rtl/common)
功能描述文档：[BPU 顶层模块](https://open-verify.cc/xs-bpu/docs/modules/00_bpu_top/)
参考功能点文档：[BPU Top 功能列表](https://open-verify.cc/xs-bpu/docs/feature/00_bpufeature/)
1. 完成对 BPU Top 子预测器的代码及文档阅读，了解 BPU Top 的工作原理及模块功能。了解 BPU Top 的预测器结构，明确 BPU Top 的预测器如何为不同类型的分支提供预测。同时了解 BPU Top 如何与外界的 FTQ 模块进行交互。
2. 根据给出的参考功能点，完善 BPU Top 需要验证的功能点，并针对这些功能点分解出具体的测试点。同时解释每个测试点对验证功能点的意义。
3. 依据分解出的测试点，完成对 BPU Top 的测试用例编写。测试用例需要覆盖到所有的测试点。同时，需要对测试用例进行详细的说明，包括测试用例的目的、输入、输出、预期结果及原理等。
4. 完成对 BPU Top 的测试用例的代码编写，要求完成**参考模型，以及FTQ模拟验证环境的编写**。确保测试用例能够通过验证环境的运行。在编码的过程中，需要保证代码的质量，包括代码的可读性、可维护性、可扩展性等。
5. 完成对 BPU Top 的测试用例的运行，生成测试报告。测试报告需要包括测试用例的运行结果、代码行覆盖率、功能覆盖率等信息。测试报告需要保存在 `tests/report` 目录中，可通过浏览器打开 `tests/report/BPU-Top-yourId.html` 查看本次测试报告内容。
6. 最终提交前，需要对测试报告进行检查，确保测试报告符合提交PR的基本要求。
## 里程碑
1. 完成功能点及测试点分解：经过`1.`的阅读工作完成学习后，进行`2.`。与我们进行沟通确认完成`2.`后才可以开始后面的工作。
2. 完成测试用例沟通：完成`3.`后，与我们进行沟通确认完成`3.`的行为符合预期及原理正确后才可以开始后面的工作。
3. 完成测试报告：经过`4.`和`5.`的过程，会生成一个测试报告。当经过不断迭代，报告最终满足PR提交基本要求后，同时我们审核通过，即认为验证任务完成。在完成迭代的过程中，如果遇到bug需要和我们进行沟通，我们会给予相应的积分。同时如果有**值得提问的问题**，可以在讨论群中进行讨论。
## PR提交基本要求
覆盖率要求：
1. 代码行覆盖率需要大于 95% ，并解释未覆盖到的代码原因。
1. 功能覆盖率必要达到 100%
1. 覆盖率有验证环境运行得到，不可对报告和生成逻辑进行修改
文档要求：
1. 对功能点进行合理的测试点分解。功能点可以自行增加，但不能对原始功能点进行删除。
1. 设计的测试用例必要覆盖所有测试点和功能点
1. 请按模板进行编写测试文档
1. 领取多个验证任务后，其验证报告需要分开写
积分获取方式：
1. 合理的测点分解、合理的验证方案、规范的验证文档
1. 验出bug并分析出bug原因，按bug确认等级获取积分
1. 修复本项目中文档，代码中出现的错误，按错误等级获取积分
1. 提交最终验证报告，按报告质量，覆盖率获得积分
1. 最终汇报得分

152
doc/join_en.md
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@ -1,152 +0,0 @@
## How to Participate in this Event
Participating in this verification event can earn you a chance to win generous prizes. [Registration Form](https://iz9a87wn37.feishu.cn/share/base/form/shrcnwpiyWaVUzyo47QdPBGy5Yd)
### Process Introduction
The process of participation is as shown below:
<img src="/.github/image/ov-pipline.svg" width="800px">
#### (0) Online Registration
There is no limit to the number of team members for this event. It can be one or more. The final prize will be distributed to the team leader according to the team's points. During the event, the team name and the name of the team leader will be made public in the group.
#### (1) Qualification Verification
In order to assess the capabilities of the participating teams, this event provides several DUTs with known bugs for the teams to perform verification tests. Teams that can find more than 80% of the bugs and can perform root cause analysis can qualify to participate. The number of bugs found will also become the corresponding team points.
#### (2) Fork Repository
Fork this repository, then set up the environment locally and participate in the testing tasks.
#### (3) Task Assignment
Tasks are described in the Issues of this repository. Team leaders sign up in the form of Issues under the Issues. The administrator will do the statistics, and then announce it in the group.
#### (4) Decompose Test Points & Write Verification Plan
Decomposing test points and verification plans are important steps in the chip verification process, which directly affect the verification results. At this stage, you need to submit the corresponding report through PR, and the organizer will review and score the report.
#### (5) Write Test Cases
Write test cases, the specific format can refer to the template in the [`tests`](command:_github.copilot.openRelativePath?%5B%7B%22scheme%22%3A%22file%22%2C%22authority%22%3A%22%22%2C%22path%22%3A%22%2Fhome%2Fyaozhicheng%2Fworkspace%2Fenv-xs-ov-00-bpu%2Ftests%22%2C%22query%22%3A%22%22%2C%22fragment%22%3A%22%22%7D%5D "/home/yaozhicheng/workspace/env-xs-ov-00-bpu/tests") directory. Test cases need to cover the corresponding test points.
#### (6) Write Test Code & Discover Bugs in Testing
During the testing process, after discovering a bug, you need to analyze the bug.
#### (7) Report Bugs through Issue and PR to Earn Points
You can submit bugs at any time through PR, but the organizer will only review bugs for a team once a day. The organizer will issue corresponding points based on the type and level of the bug.
#### (8) Write Test Report
Refer to the template [NutShell Cache](https://open-verify.cc/mlvp/docs/basic/report/) for writing.
#### (9) PPT Online Defense
Write PPT online for the defense of the entire verification task. The defense is organized centrally according to the completion situation of the team.
## Basic Tasks
### Task 1. uFTB & TFB
Source code address: [FauFTB.sv](https://github.com/XS-MLVP/env-xs-ov-00-bpu/tree/main/rtl/uFTB)
Function description document: [uFTB Branch Predictor](https://open-verify.cc/xs-bpu/en/docs/modules/01_uftb/)
Reference function point document: [uFTB Function List](https://open-verify.cc/xs-bpu/en/docs/feature/01_uftbfeature/)
Source code address: [FTB.sv](https://github.com/XS-MLVP/env-xs-ov-00-bpu/tree/main/rtl/FTB)
Function description document: [FTB Branch Predictor](https://open-verify.cc/xs-bpu/en/docs/modules/03_ftb/)
Reference function point document: [FTB Function List](https://open-verify.cc/xs-bpu/en/docs/feature/02_ftbfeature/)
1. Complete the code and document reading of the uFTB sub-predictor, understand the working principle and module functions of the uFTB. Clarify the structure of the FTB item cache used by the uFTB.
2. Based on the given reference function points, improve the function points that uFTB needs to verify, and decompose specific test points for these function points. At the same time, explain the significance of each test point to verify the function points.
3. Based on the decomposed test points, complete the test case writing for uFTB. Test cases need to cover all test points. At the same time, a detailed explanation of the test cases is required, including the purpose, input, output, expected results, and principles of the test cases.
4. Complete the code writing of the test cases for uFTB, it is recommended to complete **the writing of the reference model**. Ensure that the test cases can run through the verification environment. In the coding process, the quality of the code needs to be ensured, including the readability, maintainability, and scalability of the code.
5. Complete the running of the test cases for uFTB and generate a test report. The test report needs to include the running results of the test cases, code line coverage, function coverage, etc. The test report needs to be saved in the [`tests/report`](command:_github.copilot.openRelativePath?%5B%7B%22scheme%22%3A%22file%22%2C%22authority%22%3A%22%22%2C%22path%22%3A%22%2Fhome%2Fyaozhicheng%2Fworkspace%2Fenv-xs-ov-00-bpu%2Ftests%2Freport%22%2C%22query%22%3A%22%22%2C%22fragment%22%3A%22%22%7D%5D "/home/yaozhicheng/workspace/env-xs-ov-00-bpu/tests/report") directory, and you can open `tests/report/uFTB-yourId.html` in the browser to view the content of this test report.
6. Before the final submission, you need to check the test report to ensure that the test report meets the basic requirements for submitting PR.
### Task 2. TageSC
Source code address: [TageSC.sv](https://github.com/XS-MLVP/env-xs-ov-00-bpu/tree/main/rtl/TageSC)
Function description document: [TAGE-SC Branch Predictor](https://open-verify.cc/xs-bpu/en/docs/modules/02_tage_sc/)
Reference function point document: [TAGE-SC Function List](https://open-verify.cc/xs-bpu/en/docs/feature/03_tagescfeature/)
1. Complete the code and document reading of the TageSC sub-predictor, understand the working principles and functions of the Tage and SC single modules, and then understand the overall functions of the TageSC module. Clarify the structure of the Tage and SC table items used, and the working principle of branch folding history.
2. Based on the given reference function points, improve the function points that Tage, SC, TageSC need to verify, and decompose specific test points for these function points. At the same time, explain the significance of each test point to verify the function points.
3. Based on the decomposed test points, complete the test case writing for TageSC. Test cases need to cover all test points. At the same time, a detailed explanation of the test cases is required, including the purpose, input, output, expected results, and principles of the test cases.
4. Complete the code writing of the test cases for TageSC, it is required to complete **the writing of the reference model**. Ensure that the test cases can run through the verification environment. In the coding process, the quality of the code needs to be ensured, including the readability, maintainability, and scalability of the code.
5. Complete the running of the test cases for TageSC and generate a test report. The test report needs to include the running results of the test cases, code line coverage, function coverage, etc. The test report needs to be saved in the [`tests/report`](command:_github.copilot.openRelativePath?%5B%7B%22scheme%22%3A%22file%22%2C%22authority%22%3A%22%22%2C%22path%22%3A%22%2Fhome%2Fyaozhicheng%2Fworkspace%2Fenv-xs-ov-00-bpu%2Ftests%2Freport%22%2C%22query%22%3A%22%22%2C%22fragment%22%3A%22%22%7D%5D "/home/yaozhicheng/workspace/env-xs-ov-00-bpu/tests/report") directory, and you can open `tests/report/TageSC-yourId.html` in the browser to view the content of this test report.
6. Before the final submission, you need to check the test report to ensure that the test report meets the basic requirements for submitting PR.
### Task 3. ITTAGE
Source code address: [ITTAGE.sv](https://github.com/XS-MLVP/env-xs-ov-00-bpu/tree/main/rtl/ITTAGE)
Function description document: [ITTAGE Branch Predictor](https://open-verify.cc/xs-bpu/en/docs/modules/04_ittage/)
Reference function point document: [ITTAGE Function List](https://open-verify.cc/xs-bpu/en/docs/feature/04_ittagefeature/)
1. Complete the code and document reading of the ITTAGE sub-predictor, understand the working principles and functions of the ITTAGE. Clarify the structure of the Tage table items used by ITTAGE, understand the predictor structure of ITTAGE. Also understand the working principle of branch folding history.
2. Based on the given reference function points, improve the function points that ITTAGE needs to verify, and decompose specific test points for these function points. At the same time, explain the significance of each test point to verify the function points.
3. Based on the decomposed test points, complete the test case writing for ITTAGE. Test cases need to cover all test points. At the same time, a detailed explanation of the test cases is required, including the purpose, input, output, expected results, and principles of the test cases.
4. Complete the code writing of the test cases for ITTAGE, it is required to complete **the writing of the reference model**. Ensure that the test cases can run through the verification environment. In the coding process, the quality of the code needs to be ensured, including the readability, maintainability, and scalability of the code.
5. Complete the running of the test cases for ITTAGE and generate a test report. The test report needs to include the running results of the test cases, code line coverage, function coverage, etc. The test report needs to be saved in the [`tests/report`](command:_github.copilot.openRelativePath?%5B%7B%22scheme%22%3A%22file%22%2C%22authority%22%3A%22%22%2C%22path%22%3A%22%2Fhome%2Fyaozhicheng%2Fworkspace%2Fenv-xs-ov-00-bpu%2Ftests%2Freport%22%2C%22query%22%3A%22%22%2C%22fragment%22%3A%22%22%7D%5D "/home/yaozhicheng/workspace/env-xs-ov-00-bpu/tests/report") directory, and you can open `tests/report/ITTAGE-yourId.html` in the browser to view the content of this test report.
6. Before the final submission, you need to check the test report to ensure that the test report meets the basic requirements for submitting PR.
Translate the following markdown from Chinese to American English:
### Task 4. RAS
Source code address: [RAS.sv](https://github.com/XS-MLVP/env-xs-ov-00-bpu/tree/main/rtl/RAS)
Function description document: [RAS Branch Predictor](https://open-verify.cc/xs-bpu/en/docs/modules/05_ras/)
Reference function point document: [RAS Function List](https://open-verify.cc/xs-bpu/en/docs/feature/05_rasfeature/)
1. Complete the code and document reading of the RAS sub-predictor, understand the working principle and module function of RAS. Understand the working principle of the stack frame when the program runs, and then clarify the working principle of the RAS stack of RAS. Most clearly, the RAS predictor provides predictions for call and ret instructions.
2. Based on the given reference function points, improve the function points that RAS needs to verify, and decompose specific test points for these function points. At the same time, explain the significance of each test point to the verification function point.
3. Based on the decomposed test points, complete the test case writing for RAS. The test cases need to cover all test points. At the same time, a detailed explanation of the test cases is required, including the purpose, input, output, expected results, and principles of the test cases.
4. Complete the code writing of the RAS test cases, and require the completion of **writing the reference model**. Ensure that the test cases can pass the verification environment. During the coding process, the quality of the code needs to be ensured, including the readability, maintainability, and scalability of the code.
5. Complete the running of the RAS test cases and generate a test report. The test report needs to include the running results of the test cases, code line coverage, function coverage, and other information. The test report needs to be saved in the [`tests/report`](command:_github.copilot.openRelativePath?%5B%7B%22scheme%22%3A%22file%22%2C%22authority%22%3A%22%22%2C%22path%22%3A%22%2Fhome%2Fyaozhicheng%2Fworkspace%2Fenv-xs-ov-00-bpu%2Ftests%2Freport%22%2C%22query%22%3A%22%22%2C%22fragment%22%3A%22%22%7D%5D "/home/yaozhicheng/workspace/env-xs-ov-00-bpu/tests/report") directory, and you can open `tests/report/RAS-yourId.html` in the browser to view the content of this test report.
6. Before the final submission, you need to check the test report to ensure that the test report meets the basic requirements for submitting PR.
### Task 5. BPU Top
Source code address: [Predictor.sv & Composer.sv](https://github.com/XS-MLVP/env-xs-ov-00-bpu/tree/main/rtl/common)
Function description document: [BPU Top Module](https://open-verify.cc/xs-bpu/en/docs/modules/00_bpu_top/)
Reference function point document: [BPU Top Function List](https://open-verify.cc/xs-bpu/en/docs/feature/00_bpufeature/)
1. Complete the code and document reading of the BPU Top sub-predictor, understand the working principle and module function of BPU Top. Understand the predictor structure of BPU Top, clarify how the BPU Top predictor provides predictions for different types of branches. At the same time, understand how BPU Top interacts with the external FTQ module.
2. Based on the given reference function points, improve the function points that BPU Top needs to verify, and decompose specific test points for these function points. At the same time, explain the significance of each test point to the verification function point.
3. Based on the decomposed test points, complete the test case writing for BPU Top. The test cases need to cover all test points. At the same time, a detailed explanation of the test cases is required, including the purpose, input, output, expected results, and principles of the test cases.
4. Complete the code writing of the BPU Top test cases, and require the completion of **writing the reference model and the FTQ simulation verification environment**. Ensure that the test cases can pass the verification environment. During the coding process, the quality of the code needs to be ensured, including the readability, maintainability, and scalability of the code.
5. Complete the running of the BPU Top test cases and generate a test report. The test report needs to include the running results of the test cases, code line coverage, function coverage, and other information. The test report needs to be saved in the [`tests/report`](command:_github.copilot.openRelativePath?%5B%7B%22scheme%22%3A%22file%22%2C%22authority%22%3A%22%22%2C%22path%22%3A%22%2Fhome%2Fyaozhicheng%2Fworkspace%2Fenv-xs-ov-00-bpu%2Ftests%2Freport%22%2C%22query%22%3A%22%22%2C%22fragment%22%3A%22%22%7D%5D "/home/yaozhicheng/workspace/env-xs-ov-00-bpu/tests/report") directory, and you can open `tests/report/BPU-Top-yourId.html` in the browser to view the content of this test report.
6. Before the final submission, you need to check the test report to ensure that the test report meets the basic requirements for submitting PR.
## Milestones
1. Complete function point and test point decomposition: After completing the reading work of `1.`, proceed to `2.`. You can start the following work after communicating with us to confirm the completion of `2.`.
2. Complete test case communication: After completing `3.`, communicate with us to confirm that the behavior of `3.` meets expectations and the principle is correct before you can start the following work.
3. Complete the test report: After the process of `4.` and `5.`, a test report will be generated. When the report finally meets the basic requirements for PR submission after continuous iteration, and we review and pass, it is considered that the verification task is completed. During the process of completing the iteration, if you encounter bugs, you need to communicate with us, and we will give corresponding points. At the same time, if there are **questions worth asking**, you can discuss them in the discussion group.
## Basic requirements for PR submission
Coverage requirements:
1. The code line coverage needs to be greater than 95%, and explain the reasons for the uncovered code.
1. The function coverage must reach 100%
1. The coverage is obtained by running the verification environment, and the report and generation logic cannot be modified
Document requirements:
1. Reasonably decompose the function points into test points. Function points can be added by yourself, but the original function points cannot be deleted.
1. The designed test cases must cover all test points and function points
1. Please write the test document according to the template
1. After receiving multiple verification tasks, their verification reports need to be written separately
Ways to get points:
1. Reasonable test point decomposition, reasonable verification plan, standardized verification document
1. Find out the bug and analyze the cause of the bug, get points according to the bug confirmation level
1. Fix errors in the project's documents and code, and get points according to the error level
1. Submit the final verification report, get points according to the report quality, coverage
1. Final report score

45
mk/BPUTop.mk
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@ -1,45 +0,0 @@
TOP_ENTRY := ./rtl/BPUTop/Predictor.sv
TOP_FILES := ./rtl/BPUTop.txt
TL ?= cpp
ifneq ($(TARGET),)
TARGET := $(TARGET)
else
TARGET := out/picker_out_BPUTop
endif
# if EXAMPLE is set, then _EXAMPLE is set to -e
ifneq ($(EXAMPLE), false)
_EXAMPLE := -e
endif
_EXAMPLE ?=
# if VERBOSE is set, then _VERBOSE is set to -v
ifneq ($(VERBOSE), false)
_VERBOSE := --verbose
endif
_VERBOSE ?=
# if WAVE is set, then _WAVEFORM is set to -w
ifneq ($(WAVE), false)
ifneq ($(WAVE), true)
_WAVEFORM := -w $(WAVE)
else
_WAVEFORM := -w BPUTop.fst
endif
endif
_WAVEFORM ?=
BPUTop:
@echo "Building tage module with parameters: "
@echo "TL=${TL}"
@echo "TOP_ENTRY=${TOP_ENTRY}"
@echo "TOP_FILES=${TOP_FILES}"
@echo "TARGET=${TARGET}"
@echo "WAVEFORM=${_WAVEFORM}"
@echo "VERBOSE=${_VERBOSE}"
@echo "EXAMPLE=${_EXAMPLE}"
@mkdir -p out
rm -rf ${TARGET}
picker export ${TOP_ENTRY} --fs ${TOP_FILES} --lang ${TL} -c\
--tdir ${TARGET} ${_WAVEFORM} ${_EXAMPLE} ${_VERBOSE}

45
mk/FTB.mk
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@ -1,45 +0,0 @@
TOP_ENTRY := ./rtl/FTB/FTB.sv
TOP_FILES := ./rtl/FTB.txt
TL ?= cpp
ifneq ($(TARGET),)
TARGET := $(TARGET)
else
TARGET := out/picker_out_FTB
endif
# if EXAMPLE is set, then _EXAMPLE is set to -e
ifneq ($(EXAMPLE), false)
_EXAMPLE := -e
endif
_EXAMPLE ?=
# if VERBOSE is set, then _VERBOSE is set to -v
ifneq ($(VERBOSE), false)
_VERBOSE := --verbose
endif
_VERBOSE ?=
# if WAVE is set, then _WAVEFORM is set to -w
ifneq ($(WAVE), false)
ifneq ($(WAVE), true)
_WAVEFORM := -w $(WAVE)
else
_WAVEFORM := -w FTB.fst
endif
endif
_WAVEFORM ?=
ftb:
@echo "Building tage module with parameters: "
@echo "TL=${TL}"
@echo "TOP_ENTRY=${TOP_ENTRY}"
@echo "TOP_FILES=${TOP_FILES}"
@echo "TARGET=${TARGET}"
@echo "WAVEFORM=${_WAVEFORM}"
@echo "VERBOSE=${_VERBOSE}"
@echo "EXAMPLE=${_EXAMPLE}"
@mkdir -p out
rm -rf ${TARGET}
picker export ${TOP_ENTRY} --fs ${TOP_FILES} --lang ${TL} -c\
--tdir ${TARGET} ${_WAVEFORM}${_EXAMPLE} ${_VERBOSE}

45
mk/ITTAGE.mk
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@ -1,45 +0,0 @@
TOP_ENTRY := ./rtl/ITTAGE/ITTage.sv
TOP_FILES := ./rtl/ITTAGE.txt
TL ?= cpp
ifneq ($(TARGET),)
TARGET := $(TARGET)
else
TARGET := out/picker_out_ITTAGE
endif
# if EXAMPLE is set, then _EXAMPLE is set to -e
ifneq ($(EXAMPLE), false)
_EXAMPLE := -e
endif
_EXAMPLE ?=
# if VERBOSE is set, then _VERBOSE is set to -v
ifneq ($(VERBOSE), false)
_VERBOSE := --verbose
endif
_VERBOSE ?=
# if WAVE is set, then _WAVEFORM is set to -w
ifneq ($(WAVE), false)
ifneq ($(WAVE), true)
_WAVEFORM := -w $(WAVE)
else
_WAVEFORM := -w ITTAGE.fst
endif
endif
_WAVEFORM ?=
ittage:
@echo "Building tage module with parameters: "
@echo "TL=${TL}"
@echo "TOP_ENTRY=${TOP_ENTRY}"
@echo "TOP_FILES=${TOP_FILES}"
@echo "TARGET=${TARGET}"
@echo "WAVEFORM=${_WAVEFORM}"
@echo "VERBOSE=${_VERBOSE}"
@echo "EXAMPLE=${_EXAMPLE}"
@mkdir -p out
rm -rf ${TARGET}
picker export ${TOP_ENTRY} --fs ${TOP_FILES} --lang ${TL} -c\
--tdir ${TARGET} ${_WAVEFORM}${_EXAMPLE} ${_VERBOSE}

45
mk/RAS.mk
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@ -1,45 +0,0 @@
TOP_ENTRY := ./rtl/RAS/RAS.sv
TOP_FILES := ./rtl/RAS.txt
TL ?= cpp
ifneq ($(TARGET),)
TARGET := $(TARGET)
else
TARGET := out/picker_out_RAS
endif
# if EXAMPLE is set, then _EXAMPLE is set to -e
ifneq ($(EXAMPLE), false)
_EXAMPLE := -e
endif
_EXAMPLE ?=
# if VERBOSE is set, then _VERBOSE is set to -v
ifneq ($(VERBOSE), false)
_VERBOSE := --verbose
endif
_VERBOSE ?=
# if WAVE is set, then _WAVEFORM is set to -w
ifneq ($(WAVE), false)
ifneq ($(WAVE), true)
_WAVEFORM := -w $(WAVE)
else
_WAVEFORM := -w RAS.fst
endif
endif
_WAVEFORM ?=
ras:
@echo "Building tage module with parameters: "
@echo "TL=${TL}"
@echo "TOP_ENTRY=${TOP_ENTRY}"
@echo "TOP_FILES=${TOP_FILES}"
@echo "TARGET=${TARGET}"
@echo "WAVEFORM=${_WAVEFORM}"
@echo "VERBOSE=${_VERBOSE}"
@echo "EXAMPLE=${_EXAMPLE}"
@mkdir -p out
rm -rf ${TARGET}
picker export ${TOP_ENTRY} --fs ${TOP_FILES} --lang ${TL} -c\
--tdir ${TARGET} ${_WAVEFORM}${_EXAMPLE} ${_VERBOSE}

45
mk/Tage.mk
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@ -1,45 +0,0 @@
TOP_ENTRY := ./rtl/TageSC/Tage_SC.sv
TOP_FILES := ./rtl/Tage_SC.txt
TL ?= cpp
ifneq ($(TARGET),)
TARGET := $(TARGET)
else
TARGET := out/picker_out_TageSC
endif
# if EXAMPLE is set, then _EXAMPLE is set to -e
ifneq ($(EXAMPLE), false)
_EXAMPLE := -e
endif
_EXAMPLE ?=
# if VERBOSE is set, then _VERBOSE is set to -v
ifneq ($(VERBOSE), false)
_VERBOSE := --verbose
endif
_VERBOSE ?=
# if WAVE is set, then _WAVEFORM is set to -w
ifneq ($(WAVE), false)
ifneq ($(WAVE), true)
_WAVEFORM := -w $(WAVE)
else
_WAVEFORM := -w TageSC.fst
endif
endif
_WAVEFORM ?=
tage_sc:
@echo "Building tage module with parameters: "
@echo "TL=${TL}"
@echo "TOP_ENTRY=${TOP_ENTRY}"
@echo "TOP_FILES=${TOP_FILES}"
@echo "TARGET=${TARGET}"
@echo "WAVEFORM=${_WAVEFORM}"
@echo "VERBOSE=${_VERBOSE}"
@echo "EXAMPLE=${_EXAMPLE}"
@mkdir -p out
rm -rf ${TARGET}
picker export ${TOP_ENTRY} --fs ${TOP_FILES} --lang ${TL} -c\
--tdir ${TARGET} ${_WAVEFORM}${_EXAMPLE} ${_VERBOSE}

45
mk/uFTB.mk
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@ -1,45 +0,0 @@
TOP_ENTRY := ./rtl/uFTB/FauFTB.sv
TOP_FILES := ./rtl/uFTB.txt
TL ?= cpp
ifneq ($(TARGET),)
TARGET := $(TARGET)
else
TARGET := out/picker_out_uFTB
endif
# if EXAMPLE is set, then _EXAMPLE is set to -e
ifneq ($(EXAMPLE), false)
_EXAMPLE := -e
endif
_EXAMPLE ?=
# if VERBOSE is set, then _VERBOSE is set to -v
ifneq ($(VERBOSE), false)
_VERBOSE := --verbose
endif
_VERBOSE ?=
# if WAVE is set, then _WAVEFORM is set to -w
ifneq ($(WAVE), false)
ifneq ($(WAVE), true)
_WAVEFORM := -w $(WAVE)
else
_WAVEFORM := -w uFTB.fst
endif
endif
_WAVEFORM ?=
uftb:
@echo "Building tage module with parameters: "
@echo "TL=${TL}"
@echo "TOP_ENTRY=${TOP_ENTRY}"
@echo "TOP_FILES=${TOP_FILES}"
@echo "TARGET=${TARGET}"
@echo "WAVEFORM=${_WAVEFORM}"
@echo "VERBOSE=${_VERBOSE}"
@echo "EXAMPLE=${_EXAMPLE}"
@mkdir -p out
rm -rf ${TARGET}
picker export ${TOP_ENTRY} --fs ${TOP_FILES} --lang ${TL} -c\
--tdir ${TARGET} ${_WAVEFORM}${_EXAMPLE} ${_VERBOSE}

33
parse_relay.sh
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@ -1,33 +0,0 @@
#!/bin/bash
## 初始文件名
filename="$1"
# 用于存储已经处理过的文件，避免重复处理
declare -A processed_files
# 递归查找依赖模块的函数
find_dependencies() {
# 查看$1是否在数组中
if [ -n "${processed_files[$1]}" ]; then
return
fi
# 添加文件到已处理列表
processed_files[$1]=$1
# 查找文件中的依赖模块
while read -r module; do
# 递归查找模块的依赖
if [ -f "${module}.sv" ]; then
find_dependencies "${module}.sv"
elif [ -f "${module}.v" ]; then
find_dependencies "${module}.v"
fi
done < <(grep -E '^\s*[a-zA-Z0-9_]+\s+[a-zA-Z0-9_]+\s* \(' "$1" | awk '{print $1}' | uniq)
}
# 开始查找依赖
find_dependencies "$filename"
# 输出所有查找到的文件
echo ${processed_files[@]}

79
rtl/BPUTop.txt
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@ -1,79 +0,0 @@
./rtl/BPUTop/DelayN_4.sv
./rtl/BPUTop/ITTageTable_4.sv
./rtl/BPUTop/SRAMTemplate_39.sv
./rtl/BPUTop/PriorityMuxModule_4.sv
./rtl/BPUTop/array_0_0.sv
./rtl/BPUTop/data_mem_8x4.sv
./rtl/BPUTop/WrBypass_32.sv
./rtl/BPUTop/array_8.sv
./rtl/BPUTop/array_6_ext.v
./rtl/BPUTop/array_6.sv
./rtl/BPUTop/Folded1WDataModuleTemplate_2.sv
./rtl/BPUTop/array_3.sv
./rtl/BPUTop/DelayNWithValid_1.sv
./rtl/BPUTop/array_5_ext.v
./rtl/BPUTop/PriorityMuxModule_20.sv
./rtl/BPUTop/ITTage.sv
./rtl/BPUTop/WrBypass_41.sv
./rtl/BPUTop/ITTageTable_1.sv
./rtl/BPUTop/data_16x16.sv
./rtl/BPUTop/DelayN_2.sv
./rtl/BPUTop/Tage_SC.sv
./rtl/BPUTop/SRAMTemplate_15.sv
./rtl/BPUTop/data_32x16.sv
./rtl/BPUTop/DelayN_1.sv
./rtl/BPUTop/CAMTemplate_32.sv
./rtl/BPUTop/RAS.sv
./rtl/BPUTop/TageTable_2.sv
./rtl/BPUTop/data_mem_0_8x3.sv
./rtl/BPUTop/SRAMTemplate_34.sv
./rtl/BPUTop/SRAMTemplate_35.sv
./rtl/BPUTop/WrBypass_33.sv
./rtl/BPUTop/DelayNWithValid.sv
./rtl/BPUTop/PriorityMuxModule.sv
./rtl/BPUTop/PriorityMuxModule_8.sv
./rtl/BPUTop/SCTable.sv
./rtl/BPUTop/CAMTemplate.sv
./rtl/BPUTop/SCTable_1.sv
./rtl/BPUTop/FTB.sv
./rtl/BPUTop/FTBBank.sv
./rtl/BPUTop/WrBypass.sv
./rtl/BPUTop/TageTable_1.sv
./rtl/BPUTop/array_7_ext.v
./rtl/BPUTop/SRAMTemplate_14.sv
./rtl/BPUTop/FauFTBWay.sv
./rtl/BPUTop/data_mem_0_4x2.sv
./rtl/BPUTop/SRAMTemplate_43.sv
./rtl/BPUTop/RASStack.sv
./rtl/BPUTop/CAMTemplate_33.sv
./rtl/BPUTop/array_4_ext.v
./rtl/BPUTop/Predictor.sv
./rtl/BPUTop/array_4.sv
./rtl/BPUTop/SCTable_3.sv
./rtl/BPUTop/ITTageTable.sv
./rtl/BPUTop/CAMTemplate_43.sv
./rtl/BPUTop/TageTable_3.sv
./rtl/BPUTop/PriorityMuxModule_16.sv
./rtl/BPUTop/array_0_0_ext.v
./rtl/BPUTop/CAMTemplate_41.sv
./rtl/BPUTop/PriorityMuxModule_12.sv
./rtl/BPUTop/array_8_ext.v
./rtl/BPUTop/array_3_ext.v
./rtl/BPUTop/array_7.sv
./rtl/BPUTop/TageBTable.sv
./rtl/BPUTop/FoldedSRAMTemplate_1.sv
./rtl/BPUTop/FoldedSRAMTemplate_20.sv
./rtl/BPUTop/ITTageTable_2.sv
./rtl/BPUTop/WrBypass_43.sv
./rtl/BPUTop/FoldedSRAMTemplate_21.sv
./rtl/BPUTop/array_5.sv
./rtl/BPUTop/FoldedSRAMTemplate_25.sv
./rtl/BPUTop/Folded1WDataModuleTemplate.sv
./rtl/BPUTop/data_mem_16x12.sv
./rtl/BPUTop/FauFTB.sv
./rtl/BPUTop/SRAMTemplate_13.sv
./rtl/BPUTop/ITTageTable_3.sv
./rtl/BPUTop/Composer.sv
./rtl/BPUTop/FoldedSRAMTemplate.sv
./rtl/BPUTop/TageTable.sv
./rtl/BPUTop/SCTable_2.sv

136
rtl/BPUTop/CAMTemplate.sv
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@ -1,136 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module CAMTemplate(
input clock,
input [8:0] io_r_req_0_idx,
output io_r_resp_0_0,
output io_r_resp_0_1,
output io_r_resp_0_2,
output io_r_resp_0_3,
output io_r_resp_0_4,
output io_r_resp_0_5,
output io_r_resp_0_6,
output io_r_resp_0_7,
input io_w_valid,
input [8:0] io_w_bits_data_idx,
input [2:0] io_w_bits_index
);
reg [8:0] array_0;
reg [8:0] array_1;
reg [8:0] array_2;
reg [8:0] array_3;
reg [8:0] array_4;
reg [8:0] array_5;
reg [8:0] array_6;
reg [8:0] array_7;
always @(posedge clock) begin
if (io_w_valid & io_w_bits_index == 3'h0)
array_0 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 3'h1)
array_1 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 3'h2)
array_2 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 3'h3)
array_3 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 3'h4)
array_4 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 3'h5)
array_5 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 3'h6)
array_6 <= io_w_bits_data_idx;
if (io_w_valid & (&io_w_bits_index))
array_7 <= io_w_bits_data_idx;
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:2];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
for (logic [1:0] i = 2'h0; i < 2'h3; i += 2'h1) begin
_RANDOM[i] = `RANDOM;
end
array_0 = _RANDOM[2'h0][8:0];
array_1 = _RANDOM[2'h0][17:9];
array_2 = _RANDOM[2'h0][26:18];
array_3 = {_RANDOM[2'h0][31:27], _RANDOM[2'h1][3:0]};
array_4 = _RANDOM[2'h1][12:4];
array_5 = _RANDOM[2'h1][21:13];
array_6 = _RANDOM[2'h1][30:22];
array_7 = {_RANDOM[2'h1][31], _RANDOM[2'h2][7:0]};
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
assign io_r_resp_0_0 = io_r_req_0_idx == array_0;
assign io_r_resp_0_1 = io_r_req_0_idx == array_1;
assign io_r_resp_0_2 = io_r_req_0_idx == array_2;
assign io_r_resp_0_3 = io_r_req_0_idx == array_3;
assign io_r_resp_0_4 = io_r_req_0_idx == array_4;
assign io_r_resp_0_5 = io_r_req_0_idx == array_5;
assign io_r_resp_0_6 = io_r_req_0_idx == array_6;
assign io_r_resp_0_7 = io_r_req_0_idx == array_7;
endmodule

136
rtl/BPUTop/CAMTemplate_32.sv
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@ -1,136 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module CAMTemplate_32(
input clock,
input [10:0] io_r_req_0_idx,
output io_r_resp_0_0,
output io_r_resp_0_1,
output io_r_resp_0_2,
output io_r_resp_0_3,
output io_r_resp_0_4,
output io_r_resp_0_5,
output io_r_resp_0_6,
output io_r_resp_0_7,
input io_w_valid,
input [10:0] io_w_bits_data_idx,
input [2:0] io_w_bits_index
);
reg [10:0] array_0;
reg [10:0] array_1;
reg [10:0] array_2;
reg [10:0] array_3;
reg [10:0] array_4;
reg [10:0] array_5;
reg [10:0] array_6;
reg [10:0] array_7;
always @(posedge clock) begin
if (io_w_valid & io_w_bits_index == 3'h0)
array_0 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 3'h1)
array_1 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 3'h2)
array_2 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 3'h3)
array_3 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 3'h4)
array_4 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 3'h5)
array_5 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 3'h6)
array_6 <= io_w_bits_data_idx;
if (io_w_valid & (&io_w_bits_index))
array_7 <= io_w_bits_data_idx;
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:2];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
for (logic [1:0] i = 2'h0; i < 2'h3; i += 2'h1) begin
_RANDOM[i] = `RANDOM;
end
array_0 = _RANDOM[2'h0][10:0];
array_1 = _RANDOM[2'h0][21:11];
array_2 = {_RANDOM[2'h0][31:22], _RANDOM[2'h1][0]};
array_3 = _RANDOM[2'h1][11:1];
array_4 = _RANDOM[2'h1][22:12];
array_5 = {_RANDOM[2'h1][31:23], _RANDOM[2'h2][1:0]};
array_6 = _RANDOM[2'h2][12:2];
array_7 = _RANDOM[2'h2][23:13];
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
assign io_r_resp_0_0 = io_r_req_0_idx == array_0;
assign io_r_resp_0_1 = io_r_req_0_idx == array_1;
assign io_r_resp_0_2 = io_r_req_0_idx == array_2;
assign io_r_resp_0_3 = io_r_req_0_idx == array_3;
assign io_r_resp_0_4 = io_r_req_0_idx == array_4;
assign io_r_resp_0_5 = io_r_req_0_idx == array_5;
assign io_r_resp_0_6 = io_r_req_0_idx == array_6;
assign io_r_resp_0_7 = io_r_req_0_idx == array_7;
endmodule

184
rtl/BPUTop/CAMTemplate_33.sv
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@ -1,184 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module CAMTemplate_33(
input clock,
input [7:0] io_r_req_0_idx,
output io_r_resp_0_0,
output io_r_resp_0_1,
output io_r_resp_0_2,
output io_r_resp_0_3,
output io_r_resp_0_4,
output io_r_resp_0_5,
output io_r_resp_0_6,
output io_r_resp_0_7,
output io_r_resp_0_8,
output io_r_resp_0_9,
output io_r_resp_0_10,
output io_r_resp_0_11,
output io_r_resp_0_12,
output io_r_resp_0_13,
output io_r_resp_0_14,
output io_r_resp_0_15,
input io_w_valid,
input [7:0] io_w_bits_data_idx,
input [3:0] io_w_bits_index
);
reg [7:0] array_0;
reg [7:0] array_1;
reg [7:0] array_2;
reg [7:0] array_3;
reg [7:0] array_4;
reg [7:0] array_5;
reg [7:0] array_6;
reg [7:0] array_7;
reg [7:0] array_8;
reg [7:0] array_9;
reg [7:0] array_10;
reg [7:0] array_11;
reg [7:0] array_12;
reg [7:0] array_13;
reg [7:0] array_14;
reg [7:0] array_15;
always @(posedge clock) begin
if (io_w_valid & io_w_bits_index == 4'h0)
array_0 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 4'h1)
array_1 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 4'h2)
array_2 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 4'h3)
array_3 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 4'h4)
array_4 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 4'h5)
array_5 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 4'h6)
array_6 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 4'h7)
array_7 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 4'h8)
array_8 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 4'h9)
array_9 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 4'hA)
array_10 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 4'hB)
array_11 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 4'hC)
array_12 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 4'hD)
array_13 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 4'hE)
array_14 <= io_w_bits_data_idx;
if (io_w_valid & (&io_w_bits_index))
array_15 <= io_w_bits_data_idx;
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:3];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin
_RANDOM[i[1:0]] = `RANDOM;
end
array_0 = _RANDOM[2'h0][7:0];
array_1 = _RANDOM[2'h0][15:8];
array_2 = _RANDOM[2'h0][23:16];
array_3 = _RANDOM[2'h0][31:24];
array_4 = _RANDOM[2'h1][7:0];
array_5 = _RANDOM[2'h1][15:8];
array_6 = _RANDOM[2'h1][23:16];
array_7 = _RANDOM[2'h1][31:24];
array_8 = _RANDOM[2'h2][7:0];
array_9 = _RANDOM[2'h2][15:8];
array_10 = _RANDOM[2'h2][23:16];
array_11 = _RANDOM[2'h2][31:24];
array_12 = _RANDOM[2'h3][7:0];
array_13 = _RANDOM[2'h3][15:8];
array_14 = _RANDOM[2'h3][23:16];
array_15 = _RANDOM[2'h3][31:24];
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
assign io_r_resp_0_0 = io_r_req_0_idx == array_0;
assign io_r_resp_0_1 = io_r_req_0_idx == array_1;
assign io_r_resp_0_2 = io_r_req_0_idx == array_2;
assign io_r_resp_0_3 = io_r_req_0_idx == array_3;
assign io_r_resp_0_4 = io_r_req_0_idx == array_4;
assign io_r_resp_0_5 = io_r_req_0_idx == array_5;
assign io_r_resp_0_6 = io_r_req_0_idx == array_6;
assign io_r_resp_0_7 = io_r_req_0_idx == array_7;
assign io_r_resp_0_8 = io_r_req_0_idx == array_8;
assign io_r_resp_0_9 = io_r_req_0_idx == array_9;
assign io_r_resp_0_10 = io_r_req_0_idx == array_10;
assign io_r_resp_0_11 = io_r_req_0_idx == array_11;
assign io_r_resp_0_12 = io_r_req_0_idx == array_12;
assign io_r_resp_0_13 = io_r_req_0_idx == array_13;
assign io_r_resp_0_14 = io_r_req_0_idx == array_14;
assign io_r_resp_0_15 = io_r_req_0_idx == array_15;
endmodule

110
rtl/BPUTop/CAMTemplate_41.sv
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@ -1,110 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module CAMTemplate_41(
input clock,
input [7:0] io_r_req_0_idx,
output io_r_resp_0_0,
output io_r_resp_0_1,
output io_r_resp_0_2,
output io_r_resp_0_3,
input io_w_valid,
input [7:0] io_w_bits_data_idx,
input [1:0] io_w_bits_index
);
reg [7:0] array_0;
reg [7:0] array_1;
reg [7:0] array_2;
reg [7:0] array_3;
always @(posedge clock) begin
if (io_w_valid & io_w_bits_index == 2'h0)
array_0 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 2'h1)
array_1 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 2'h2)
array_2 <= io_w_bits_data_idx;
if (io_w_valid & (&io_w_bits_index))
array_3 <= io_w_bits_data_idx;
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
array_0 = _RANDOM[/*Zero width*/ 1'b0][7:0];
array_1 = _RANDOM[/*Zero width*/ 1'b0][15:8];
array_2 = _RANDOM[/*Zero width*/ 1'b0][23:16];
array_3 = _RANDOM[/*Zero width*/ 1'b0][31:24];
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
assign io_r_resp_0_0 = io_r_req_0_idx == array_0;
assign io_r_resp_0_1 = io_r_req_0_idx == array_1;
assign io_r_resp_0_2 = io_r_req_0_idx == array_2;
assign io_r_resp_0_3 = io_r_req_0_idx == array_3;
endmodule

112
rtl/BPUTop/CAMTemplate_43.sv
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@ -1,112 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module CAMTemplate_43(
input clock,
input [8:0] io_r_req_0_idx,
output io_r_resp_0_0,
output io_r_resp_0_1,
output io_r_resp_0_2,
output io_r_resp_0_3,
input io_w_valid,
input [8:0] io_w_bits_data_idx,
input [1:0] io_w_bits_index
);
reg [8:0] array_0;
reg [8:0] array_1;
reg [8:0] array_2;
reg [8:0] array_3;
always @(posedge clock) begin
if (io_w_valid & io_w_bits_index == 2'h0)
array_0 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 2'h1)
array_1 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 2'h2)
array_2 <= io_w_bits_data_idx;
if (io_w_valid & (&io_w_bits_index))
array_3 <= io_w_bits_data_idx;
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:1];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin
_RANDOM[i[0]] = `RANDOM;
end
array_0 = _RANDOM[1'h0][8:0];
array_1 = _RANDOM[1'h0][17:9];
array_2 = _RANDOM[1'h0][26:18];
array_3 = {_RANDOM[1'h0][31:27], _RANDOM[1'h1][3:0]};
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
assign io_r_resp_0_0 = io_r_req_0_idx == array_0;
assign io_r_resp_0_1 = io_r_req_0_idx == array_1;
assign io_r_resp_0_2 = io_r_req_0_idx == array_2;
assign io_r_resp_0_3 = io_r_req_0_idx == array_3;
endmodule

2426
rtl/BPUTop/Composer.sv
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File diff suppressed because it is too large Load Diff

107
rtl/BPUTop/DelayNWithValid.sv
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@ -1,107 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module DelayNWithValid(
input clock,
input reset,
input [40:0] io_in_bits,
input io_in_valid,
output [40:0] io_out_bits
);
reg valid_REG;
reg [40:0] data;
reg [40:0] res_bits;
always @(posedge clock or posedge reset) begin
if (reset)
valid_REG <= 1'h0;
else
valid_REG <= io_in_valid;
end // always @(posedge, posedge)
always @(posedge clock) begin
if (io_in_valid)
data <= io_in_bits;
if (valid_REG)
res_bits <= data;
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:2];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
for (logic [1:0] i = 2'h0; i < 2'h3; i += 2'h1) begin
_RANDOM[i] = `RANDOM;
end
valid_REG = _RANDOM[2'h0][0];
data = {_RANDOM[2'h0][31:1], _RANDOM[2'h1][9:0]};
res_bits = {_RANDOM[2'h1][31:11], _RANDOM[2'h2][19:0]};
`endif // RANDOMIZE_REG_INIT
if (reset)
valid_REG = 1'h0;
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
assign io_out_bits = res_bits;
endmodule

271
rtl/BPUTop/DelayNWithValid_1.sv
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@ -1,271 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module DelayNWithValid_1(
input clock,
input reset,
input io_in_bits_valid,
input [3:0] io_in_bits_brSlots_0_offset,
input [11:0] io_in_bits_brSlots_0_lower,
input [1:0] io_in_bits_brSlots_0_tarStat,
input io_in_bits_brSlots_0_sharing,
input io_in_bits_brSlots_0_valid,
input [3:0] io_in_bits_tailSlot_offset,
input [19:0] io_in_bits_tailSlot_lower,
input [1:0] io_in_bits_tailSlot_tarStat,
input io_in_bits_tailSlot_sharing,
input io_in_bits_tailSlot_valid,
input [3:0] io_in_bits_pftAddr,
input io_in_bits_carry,
input io_in_bits_isCall,
input io_in_bits_isRet,
input io_in_bits_isJalr,
input io_in_bits_last_may_be_rvi_call,
input io_in_bits_always_taken_0,
input io_in_bits_always_taken_1,
input io_in_valid,
output io_out_bits_valid,
output [3:0] io_out_bits_brSlots_0_offset,
output [11:0] io_out_bits_brSlots_0_lower,
output [1:0] io_out_bits_brSlots_0_tarStat,
output io_out_bits_brSlots_0_sharing,
output io_out_bits_brSlots_0_valid,
output [3:0] io_out_bits_tailSlot_offset,
output [19:0] io_out_bits_tailSlot_lower,
output [1:0] io_out_bits_tailSlot_tarStat,
output io_out_bits_tailSlot_sharing,
output io_out_bits_tailSlot_valid,
output [3:0] io_out_bits_pftAddr,
output io_out_bits_carry,
output io_out_bits_isCall,
output io_out_bits_isRet,
output io_out_bits_isJalr,
output io_out_bits_last_may_be_rvi_call,
output io_out_bits_always_taken_0,
output io_out_bits_always_taken_1
);
reg valid_REG;
reg data_valid;
reg [3:0] data_brSlots_0_offset;
reg [11:0] data_brSlots_0_lower;
reg [1:0] data_brSlots_0_tarStat;
reg data_brSlots_0_sharing;
reg data_brSlots_0_valid;
reg [3:0] data_tailSlot_offset;
reg [19:0] data_tailSlot_lower;
reg [1:0] data_tailSlot_tarStat;
reg data_tailSlot_sharing;
reg data_tailSlot_valid;
reg [3:0] data_pftAddr;
reg data_carry;
reg data_isCall;
reg data_isRet;
reg data_isJalr;
reg data_last_may_be_rvi_call;
reg data_always_taken_0;
reg data_always_taken_1;
reg res_bits_valid;
reg [3:0] res_bits_brSlots_0_offset;
reg [11:0] res_bits_brSlots_0_lower;
reg [1:0] res_bits_brSlots_0_tarStat;
reg res_bits_brSlots_0_sharing;
reg res_bits_brSlots_0_valid;
reg [3:0] res_bits_tailSlot_offset;
reg [19:0] res_bits_tailSlot_lower;
reg [1:0] res_bits_tailSlot_tarStat;
reg res_bits_tailSlot_sharing;
reg res_bits_tailSlot_valid;
reg [3:0] res_bits_pftAddr;
reg res_bits_carry;
reg res_bits_isCall;
reg res_bits_isRet;
reg res_bits_isJalr;
reg res_bits_last_may_be_rvi_call;
reg res_bits_always_taken_0;
reg res_bits_always_taken_1;
always @(posedge clock or posedge reset) begin
if (reset)
valid_REG <= 1'h0;
else
valid_REG <= io_in_valid;
end // always @(posedge, posedge)
always @(posedge clock) begin
if (io_in_valid) begin
data_valid <= io_in_bits_valid;
data_brSlots_0_offset <= io_in_bits_brSlots_0_offset;
data_brSlots_0_lower <= io_in_bits_brSlots_0_lower;
data_brSlots_0_tarStat <= io_in_bits_brSlots_0_tarStat;
data_brSlots_0_sharing <= io_in_bits_brSlots_0_sharing;
data_brSlots_0_valid <= io_in_bits_brSlots_0_valid;
data_tailSlot_offset <= io_in_bits_tailSlot_offset;
data_tailSlot_lower <= io_in_bits_tailSlot_lower;
data_tailSlot_tarStat <= io_in_bits_tailSlot_tarStat;
data_tailSlot_sharing <= io_in_bits_tailSlot_sharing;
data_tailSlot_valid <= io_in_bits_tailSlot_valid;
data_pftAddr <= io_in_bits_pftAddr;
data_carry <= io_in_bits_carry;
data_isCall <= io_in_bits_isCall;
data_isRet <= io_in_bits_isRet;
data_isJalr <= io_in_bits_isJalr;
data_last_may_be_rvi_call <= io_in_bits_last_may_be_rvi_call;
data_always_taken_0 <= io_in_bits_always_taken_0;
data_always_taken_1 <= io_in_bits_always_taken_1;
end
if (valid_REG) begin
res_bits_valid <= data_valid;
res_bits_brSlots_0_offset <= data_brSlots_0_offset;
res_bits_brSlots_0_lower <= data_brSlots_0_lower;
res_bits_brSlots_0_tarStat <= data_brSlots_0_tarStat;
res_bits_brSlots_0_sharing <= data_brSlots_0_sharing;
res_bits_brSlots_0_valid <= data_brSlots_0_valid;
res_bits_tailSlot_offset <= data_tailSlot_offset;
res_bits_tailSlot_lower <= data_tailSlot_lower;
res_bits_tailSlot_tarStat <= data_tailSlot_tarStat;
res_bits_tailSlot_sharing <= data_tailSlot_sharing;
res_bits_tailSlot_valid <= data_tailSlot_valid;
res_bits_pftAddr <= data_pftAddr;
res_bits_carry <= data_carry;
res_bits_isCall <= data_isCall;
res_bits_isRet <= data_isRet;
res_bits_isJalr <= data_isJalr;
res_bits_last_may_be_rvi_call <= data_last_may_be_rvi_call;
res_bits_always_taken_0 <= data_always_taken_0;
res_bits_always_taken_1 <= data_always_taken_1;
end
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:3];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin
_RANDOM[i[1:0]] = `RANDOM;
end
valid_REG = _RANDOM[2'h0][0];
data_valid = _RANDOM[2'h0][1];
data_brSlots_0_offset = _RANDOM[2'h0][5:2];
data_brSlots_0_lower = _RANDOM[2'h0][17:6];
data_brSlots_0_tarStat = _RANDOM[2'h0][19:18];
data_brSlots_0_sharing = _RANDOM[2'h0][20];
data_brSlots_0_valid = _RANDOM[2'h0][21];
data_tailSlot_offset = _RANDOM[2'h0][25:22];
data_tailSlot_lower = {_RANDOM[2'h0][31:26], _RANDOM[2'h1][13:0]};
data_tailSlot_tarStat = _RANDOM[2'h1][15:14];
data_tailSlot_sharing = _RANDOM[2'h1][16];
data_tailSlot_valid = _RANDOM[2'h1][17];
data_pftAddr = _RANDOM[2'h1][21:18];
data_carry = _RANDOM[2'h1][22];
data_isCall = _RANDOM[2'h1][23];
data_isRet = _RANDOM[2'h1][24];
data_isJalr = _RANDOM[2'h1][25];
data_last_may_be_rvi_call = _RANDOM[2'h1][26];
data_always_taken_0 = _RANDOM[2'h1][27];
data_always_taken_1 = _RANDOM[2'h1][28];
res_bits_valid = _RANDOM[2'h1][30];
res_bits_brSlots_0_offset = {_RANDOM[2'h1][31], _RANDOM[2'h2][2:0]};
res_bits_brSlots_0_lower = _RANDOM[2'h2][14:3];
res_bits_brSlots_0_tarStat = _RANDOM[2'h2][16:15];
res_bits_brSlots_0_sharing = _RANDOM[2'h2][17];
res_bits_brSlots_0_valid = _RANDOM[2'h2][18];
res_bits_tailSlot_offset = _RANDOM[2'h2][22:19];
res_bits_tailSlot_lower = {_RANDOM[2'h2][31:23], _RANDOM[2'h3][10:0]};
res_bits_tailSlot_tarStat = _RANDOM[2'h3][12:11];
res_bits_tailSlot_sharing = _RANDOM[2'h3][13];
res_bits_tailSlot_valid = _RANDOM[2'h3][14];
res_bits_pftAddr = _RANDOM[2'h3][18:15];
res_bits_carry = _RANDOM[2'h3][19];
res_bits_isCall = _RANDOM[2'h3][20];
res_bits_isRet = _RANDOM[2'h3][21];
res_bits_isJalr = _RANDOM[2'h3][22];
res_bits_last_may_be_rvi_call = _RANDOM[2'h3][23];
res_bits_always_taken_0 = _RANDOM[2'h3][24];
res_bits_always_taken_1 = _RANDOM[2'h3][25];
`endif // RANDOMIZE_REG_INIT
if (reset)
valid_REG = 1'h0;
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
assign io_out_bits_valid = res_bits_valid;
assign io_out_bits_brSlots_0_offset = res_bits_brSlots_0_offset;
assign io_out_bits_brSlots_0_lower = res_bits_brSlots_0_lower;
assign io_out_bits_brSlots_0_tarStat = res_bits_brSlots_0_tarStat;
assign io_out_bits_brSlots_0_sharing = res_bits_brSlots_0_sharing;
assign io_out_bits_brSlots_0_valid = res_bits_brSlots_0_valid;
assign io_out_bits_tailSlot_offset = res_bits_tailSlot_offset;
assign io_out_bits_tailSlot_lower = res_bits_tailSlot_lower;
assign io_out_bits_tailSlot_tarStat = res_bits_tailSlot_tarStat;
assign io_out_bits_tailSlot_sharing = res_bits_tailSlot_sharing;
assign io_out_bits_tailSlot_valid = res_bits_tailSlot_valid;
assign io_out_bits_pftAddr = res_bits_pftAddr;
assign io_out_bits_carry = res_bits_carry;
assign io_out_bits_isCall = res_bits_isCall;
assign io_out_bits_isRet = res_bits_isRet;
assign io_out_bits_isJalr = res_bits_isJalr;
assign io_out_bits_last_may_be_rvi_call = res_bits_last_may_be_rvi_call;
assign io_out_bits_always_taken_0 = res_bits_always_taken_0;
assign io_out_bits_always_taken_1 = res_bits_always_taken_1;
endmodule

112
rtl/BPUTop/DelayN_1.sv
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@ -1,112 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module DelayN_1(
input clock,
input io_in_ubtb_enable,
input io_in_btb_enable,
input io_in_tage_enable,
input io_in_sc_enable,
input io_in_ras_enable,
output io_out_ubtb_enable,
output io_out_btb_enable,
output io_out_tage_enable,
output io_out_sc_enable,
output io_out_ras_enable
);
reg REG_ubtb_enable;
reg REG_btb_enable;
reg REG_tage_enable;
reg REG_sc_enable;
reg REG_ras_enable;
always @(posedge clock) begin
REG_ubtb_enable <= io_in_ubtb_enable;
REG_btb_enable <= io_in_btb_enable;
REG_tage_enable <= io_in_tage_enable;
REG_sc_enable <= io_in_sc_enable;
REG_ras_enable <= io_in_ras_enable;
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
REG_ubtb_enable = _RANDOM[/*Zero width*/ 1'b0][0];
REG_btb_enable = _RANDOM[/*Zero width*/ 1'b0][1];
REG_tage_enable = _RANDOM[/*Zero width*/ 1'b0][3];
REG_sc_enable = _RANDOM[/*Zero width*/ 1'b0][4];
REG_ras_enable = _RANDOM[/*Zero width*/ 1'b0][5];
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
assign io_out_ubtb_enable = REG_ubtb_enable;
assign io_out_btb_enable = REG_btb_enable;
assign io_out_tage_enable = REG_tage_enable;
assign io_out_sc_enable = REG_sc_enable;
assign io_out_ras_enable = REG_ras_enable;
endmodule

102
rtl/BPUTop/DelayN_2.sv
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@ -1,102 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module DelayN_2(
input clock,
input [35:0] io_in,
output [35:0] io_out
);
reg [35:0] REG;
reg [35:0] REG_1;
reg [35:0] REG_2;
reg [35:0] REG_3;
reg [35:0] REG_4;
always @(posedge clock) begin
REG <= io_in;
REG_1 <= REG;
REG_2 <= REG_1;
REG_3 <= REG_2;
REG_4 <= REG_3;
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:5];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
for (logic [2:0] i = 3'h0; i < 3'h6; i += 3'h1) begin
_RANDOM[i] = `RANDOM;
end
REG = {_RANDOM[3'h0], _RANDOM[3'h1][3:0]};
REG_1 = {_RANDOM[3'h1][31:4], _RANDOM[3'h2][7:0]};
REG_2 = {_RANDOM[3'h2][31:8], _RANDOM[3'h3][11:0]};
REG_3 = {_RANDOM[3'h3][31:12], _RANDOM[3'h4][15:0]};
REG_4 = {_RANDOM[3'h4][31:16], _RANDOM[3'h5][19:0]};
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
assign io_out = REG_4;
endmodule

91
rtl/BPUTop/DelayN_4.sv
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@ -1,91 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module DelayN_4(
input clock,
input io_in,
output io_out
);
reg REG;
reg REG_1;
always @(posedge clock) begin
REG <= io_in;
REG_1 <= REG;
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
REG = _RANDOM[/*Zero width*/ 1'b0][0];
REG_1 = _RANDOM[/*Zero width*/ 1'b0][1];
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
assign io_out = REG_1;
endmodule

1644
rtl/BPUTop/FTB.sv
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6369
rtl/BPUTop/FTBBank.sv
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4755
rtl/BPUTop/FauFTB.sv
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187
rtl/BPUTop/FauFTBWay.sv
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@ -1,187 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module FauFTBWay(
input clock,
input reset,
input [15:0] io_req_tag,
output [3:0] io_resp_brSlots_0_offset,
output [11:0] io_resp_brSlots_0_lower,
output [1:0] io_resp_brSlots_0_tarStat,
output io_resp_brSlots_0_valid,
output [3:0] io_resp_tailSlot_offset,
output [19:0] io_resp_tailSlot_lower,
output [1:0] io_resp_tailSlot_tarStat,
output io_resp_tailSlot_sharing,
output io_resp_tailSlot_valid,
output [3:0] io_resp_pftAddr,
output io_resp_carry,
output io_resp_always_taken_0,
output io_resp_always_taken_1,
output io_resp_hit,
input [15:0] io_update_req_tag,
output io_update_hit,
input io_write_valid,
input [3:0] io_write_entry_brSlots_0_offset,
input [11:0] io_write_entry_brSlots_0_lower,
input [1:0] io_write_entry_brSlots_0_tarStat,
input io_write_entry_brSlots_0_valid,
input [3:0] io_write_entry_tailSlot_offset,
input [19:0] io_write_entry_tailSlot_lower,
input [1:0] io_write_entry_tailSlot_tarStat,
input io_write_entry_tailSlot_sharing,
input io_write_entry_tailSlot_valid,
input [3:0] io_write_entry_pftAddr,
input io_write_entry_carry,
input io_write_entry_always_taken_0,
input io_write_entry_always_taken_1,
input [15:0] io_write_tag
);
reg [3:0] data_brSlots_0_offset;
reg [11:0] data_brSlots_0_lower;
reg [1:0] data_brSlots_0_tarStat;
reg data_brSlots_0_valid;
reg [3:0] data_tailSlot_offset;
reg [19:0] data_tailSlot_lower;
reg [1:0] data_tailSlot_tarStat;
reg data_tailSlot_sharing;
reg data_tailSlot_valid;
reg [3:0] data_pftAddr;
reg data_carry;
reg data_always_taken_0;
reg data_always_taken_1;
reg [15:0] tag;
reg valid;
always @(posedge clock) begin
if (io_write_valid) begin
data_brSlots_0_offset <= io_write_entry_brSlots_0_offset;
data_brSlots_0_lower <= io_write_entry_brSlots_0_lower;
data_brSlots_0_tarStat <= io_write_entry_brSlots_0_tarStat;
data_brSlots_0_valid <= io_write_entry_brSlots_0_valid;
data_tailSlot_offset <= io_write_entry_tailSlot_offset;
data_tailSlot_lower <= io_write_entry_tailSlot_lower;
data_tailSlot_tarStat <= io_write_entry_tailSlot_tarStat;
data_tailSlot_sharing <= io_write_entry_tailSlot_sharing;
data_tailSlot_valid <= io_write_entry_tailSlot_valid;
data_pftAddr <= io_write_entry_pftAddr;
data_carry <= io_write_entry_carry;
data_always_taken_0 <= io_write_entry_always_taken_0;
data_always_taken_1 <= io_write_entry_always_taken_1;
tag <= io_write_tag;
end
end // always @(posedge)
always @(posedge clock or posedge reset) begin
if (reset)
valid <= 1'h0;
else
valid <= io_write_valid & ~valid | valid;
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:2];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
for (logic [1:0] i = 2'h0; i < 2'h3; i += 2'h1) begin
_RANDOM[i] = `RANDOM;
end
data_brSlots_0_offset = _RANDOM[2'h0][4:1];
data_brSlots_0_lower = _RANDOM[2'h0][16:5];
data_brSlots_0_tarStat = _RANDOM[2'h0][18:17];
data_brSlots_0_valid = _RANDOM[2'h0][20];
data_tailSlot_offset = _RANDOM[2'h0][24:21];
data_tailSlot_lower = {_RANDOM[2'h0][31:25], _RANDOM[2'h1][12:0]};
data_tailSlot_tarStat = _RANDOM[2'h1][14:13];
data_tailSlot_sharing = _RANDOM[2'h1][15];
data_tailSlot_valid = _RANDOM[2'h1][16];
data_pftAddr = _RANDOM[2'h1][20:17];
data_carry = _RANDOM[2'h1][21];
data_always_taken_0 = _RANDOM[2'h1][26];
data_always_taken_1 = _RANDOM[2'h1][27];
tag = {_RANDOM[2'h1][31:28], _RANDOM[2'h2][11:0]};
valid = _RANDOM[2'h2][12];
`endif // RANDOMIZE_REG_INIT
if (reset)
valid = 1'h0;
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
assign io_resp_brSlots_0_offset = data_brSlots_0_offset;
assign io_resp_brSlots_0_lower = data_brSlots_0_lower;
assign io_resp_brSlots_0_tarStat = data_brSlots_0_tarStat;
assign io_resp_brSlots_0_valid = data_brSlots_0_valid;
assign io_resp_tailSlot_offset = data_tailSlot_offset;
assign io_resp_tailSlot_lower = data_tailSlot_lower;
assign io_resp_tailSlot_tarStat = data_tailSlot_tarStat;
assign io_resp_tailSlot_sharing = data_tailSlot_sharing;
assign io_resp_tailSlot_valid = data_tailSlot_valid;
assign io_resp_pftAddr = data_pftAddr;
assign io_resp_carry = data_carry;
assign io_resp_always_taken_0 = data_always_taken_0;
assign io_resp_always_taken_1 = data_always_taken_1;
assign io_resp_hit = tag == io_req_tag & valid;
assign io_update_hit =
tag == io_update_req_tag & valid | io_write_tag == io_update_req_tag & io_write_valid;
endmodule

146
rtl/BPUTop/Folded1WDataModuleTemplate.sv
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@ -1,146 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module Folded1WDataModuleTemplate(
input clock,
input reset,
input io_ren_0,
input [7:0] io_raddr_0,
output io_rdata_0,
input io_wen,
input [7:0] io_waddr,
input io_wdata,
input io_resetEn
);
wire [15:0] _data_ext_R0_data;
reg doing_reset;
reg [3:0] resetRow;
reg [7:0] raddr_0;
wire [15:0] _GEN =
{{_data_ext_R0_data[15]},
{_data_ext_R0_data[14]},
{_data_ext_R0_data[13]},
{_data_ext_R0_data[12]},
{_data_ext_R0_data[11]},
{_data_ext_R0_data[10]},
{_data_ext_R0_data[9]},
{_data_ext_R0_data[8]},
{_data_ext_R0_data[7]},
{_data_ext_R0_data[6]},
{_data_ext_R0_data[5]},
{_data_ext_R0_data[4]},
{_data_ext_R0_data[3]},
{_data_ext_R0_data[2]},
{_data_ext_R0_data[1]},
{_data_ext_R0_data[0]}};
always @(posedge clock or posedge reset) begin
if (reset) begin
doing_reset <= 1'h1;
resetRow <= 4'h0;
end
else begin
doing_reset <= resetRow != 4'hF & (io_resetEn | doing_reset);
if (doing_reset)
resetRow <= 4'(resetRow + 4'h1);
end
end // always @(posedge, posedge)
always @(posedge clock) begin
if (io_ren_0)
raddr_0 <= io_raddr_0;
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
doing_reset = _RANDOM[/*Zero width*/ 1'b0][0];
resetRow = _RANDOM[/*Zero width*/ 1'b0][4:1];
raddr_0 = _RANDOM[/*Zero width*/ 1'b0][12:5];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
doing_reset = 1'h1;
resetRow = 4'h0;
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
data_16x16 data_ext (
.R0_addr (raddr_0[7:4]),
.R0_en (1'h1),
.R0_clk (clock),
.R0_data (_data_ext_R0_data),
.W0_addr (io_waddr[7:4]),
.W0_en (~doing_reset & io_wen),
.W0_clk (clock),
.W0_data ({16{io_wdata}}),
.W1_addr (resetRow),
.W1_en (doing_reset),
.W1_clk (clock),
.W1_data (16'h0)
);
assign io_rdata_0 = ~doing_reset & _GEN[raddr_0[3:0]];
endmodule

146
rtl/BPUTop/Folded1WDataModuleTemplate_2.sv
View File

@ -1,146 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module Folded1WDataModuleTemplate_2(
input clock,
input reset,
input io_ren_0,
input [8:0] io_raddr_0,
output io_rdata_0,
input io_wen,
input [8:0] io_waddr,
input io_wdata,
input io_resetEn
);
wire [15:0] _data_ext_R0_data;
reg doing_reset;
reg [4:0] resetRow;
reg [8:0] raddr_0;
wire [15:0] _GEN =
{{_data_ext_R0_data[15]},
{_data_ext_R0_data[14]},
{_data_ext_R0_data[13]},
{_data_ext_R0_data[12]},
{_data_ext_R0_data[11]},
{_data_ext_R0_data[10]},
{_data_ext_R0_data[9]},
{_data_ext_R0_data[8]},
{_data_ext_R0_data[7]},
{_data_ext_R0_data[6]},
{_data_ext_R0_data[5]},
{_data_ext_R0_data[4]},
{_data_ext_R0_data[3]},
{_data_ext_R0_data[2]},
{_data_ext_R0_data[1]},
{_data_ext_R0_data[0]}};
always @(posedge clock or posedge reset) begin
if (reset) begin
doing_reset <= 1'h1;
resetRow <= 5'h0;
end
else begin
doing_reset <= resetRow != 5'h1F & (io_resetEn | doing_reset);
if (doing_reset)
resetRow <= 5'(resetRow + 5'h1);
end
end // always @(posedge, posedge)
always @(posedge clock) begin
if (io_ren_0)
raddr_0 <= io_raddr_0;
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
doing_reset = _RANDOM[/*Zero width*/ 1'b0][0];
resetRow = _RANDOM[/*Zero width*/ 1'b0][5:1];
raddr_0 = _RANDOM[/*Zero width*/ 1'b0][14:6];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
doing_reset = 1'h1;
resetRow = 5'h0;
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
data_32x16 data_ext (
.R0_addr (raddr_0[8:4]),
.R0_en (1'h1),
.R0_clk (clock),
.R0_data (_data_ext_R0_data),
.W0_addr (io_waddr[8:4]),
.W0_en (~doing_reset & io_wen),
.W0_clk (clock),
.W0_data ({16{io_wdata}}),
.W1_addr (resetRow),
.W1_en (doing_reset),
.W1_clk (clock),
.W1_data (16'h0)
);
assign io_rdata_0 = ~doing_reset & _GEN[raddr_0[3:0]];
endmodule

224
rtl/BPUTop/FoldedSRAMTemplate.sv
View File

@ -1,224 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module FoldedSRAMTemplate(
input clock,
input reset,
output io_r_req_ready,
input io_r_req_valid,
input [10:0] io_r_req_bits_setIdx,
output io_r_resp_data_0,
output io_r_resp_data_1,
input io_w_req_valid,
input [10:0] io_w_req_bits_setIdx,
input io_w_req_bits_data_0,
input io_w_req_bits_data_1,
input [1:0] io_w_req_bits_waymask,
input extra_reset
);
wire _array_io_r_resp_data_0;
wire _array_io_r_resp_data_1;
wire _array_io_r_resp_data_2;
wire _array_io_r_resp_data_3;
wire _array_io_r_resp_data_4;
wire _array_io_r_resp_data_5;
wire _array_io_r_resp_data_6;
wire _array_io_r_resp_data_7;
wire _array_io_r_resp_data_8;
wire _array_io_r_resp_data_9;
wire _array_io_r_resp_data_10;
wire _array_io_r_resp_data_11;
wire _array_io_r_resp_data_12;
wire _array_io_r_resp_data_13;
wire _array_io_r_resp_data_14;
wire _array_io_r_resp_data_15;
reg [2:0] ridx;
reg holdRidx_last_r;
reg [2:0] holdRidx_hold_data;
wire [2:0] holdRidx = holdRidx_last_r ? ridx : holdRidx_hold_data;
reg holdRidx_last_r_1;
reg [2:0] holdRidx_hold_data_1;
wire [2:0] holdRidx_1 = holdRidx_last_r_1 ? ridx : holdRidx_hold_data_1;
wire _wmask_T_3 = io_w_req_bits_setIdx[2:0] == 3'h0;
wire _wmask_T_9 = io_w_req_bits_setIdx[2:0] == 3'h1;
wire _wmask_T_15 = io_w_req_bits_setIdx[2:0] == 3'h2;
wire _wmask_T_21 = io_w_req_bits_setIdx[2:0] == 3'h3;
wire _wmask_T_27 = io_w_req_bits_setIdx[2:0] == 3'h4;
wire _wmask_T_33 = io_w_req_bits_setIdx[2:0] == 3'h5;
wire _wmask_T_39 = io_w_req_bits_setIdx[2:0] == 3'h6;
always @(posedge clock) begin
if (io_r_req_valid)
ridx <= io_r_req_bits_setIdx[2:0];
if (holdRidx_last_r)
holdRidx_hold_data <= ridx;
if (holdRidx_last_r_1)
holdRidx_hold_data_1 <= ridx;
end // always @(posedge)
always @(posedge clock or posedge reset) begin
if (reset) begin
holdRidx_last_r <= 1'h0;
holdRidx_last_r_1 <= 1'h0;
end
else begin
if (io_r_req_valid | holdRidx_last_r)
holdRidx_last_r <= io_r_req_valid;
if (io_r_req_valid | holdRidx_last_r_1)
holdRidx_last_r_1 <= io_r_req_valid;
end
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
ridx = _RANDOM[/*Zero width*/ 1'b0][2:0];
holdRidx_last_r = _RANDOM[/*Zero width*/ 1'b0][3];
holdRidx_hold_data = _RANDOM[/*Zero width*/ 1'b0][6:4];
holdRidx_last_r_1 = _RANDOM[/*Zero width*/ 1'b0][7];
holdRidx_hold_data_1 = _RANDOM[/*Zero width*/ 1'b0][10:8];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
holdRidx_last_r = 1'h0;
holdRidx_last_r_1 = 1'h0;
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
SRAMTemplate_14 array (
.clock (clock),
.reset (reset),
.io_r_req_ready (io_r_req_ready),
.io_r_req_valid (io_r_req_valid),
.io_r_req_bits_setIdx (io_r_req_bits_setIdx[10:3]),
.io_r_resp_data_0 (_array_io_r_resp_data_0),
.io_r_resp_data_1 (_array_io_r_resp_data_1),
.io_r_resp_data_2 (_array_io_r_resp_data_2),
.io_r_resp_data_3 (_array_io_r_resp_data_3),
.io_r_resp_data_4 (_array_io_r_resp_data_4),
.io_r_resp_data_5 (_array_io_r_resp_data_5),
.io_r_resp_data_6 (_array_io_r_resp_data_6),
.io_r_resp_data_7 (_array_io_r_resp_data_7),
.io_r_resp_data_8 (_array_io_r_resp_data_8),
.io_r_resp_data_9 (_array_io_r_resp_data_9),
.io_r_resp_data_10 (_array_io_r_resp_data_10),
.io_r_resp_data_11 (_array_io_r_resp_data_11),
.io_r_resp_data_12 (_array_io_r_resp_data_12),
.io_r_resp_data_13 (_array_io_r_resp_data_13),
.io_r_resp_data_14 (_array_io_r_resp_data_14),
.io_r_resp_data_15 (_array_io_r_resp_data_15),
.io_w_req_valid (io_w_req_valid),
.io_w_req_bits_setIdx (io_w_req_bits_setIdx[10:3]),
.io_w_req_bits_data_0 (io_w_req_bits_data_0),
.io_w_req_bits_data_1 (io_w_req_bits_data_1),
.io_w_req_bits_data_2 (io_w_req_bits_data_0),
.io_w_req_bits_data_3 (io_w_req_bits_data_1),
.io_w_req_bits_data_4 (io_w_req_bits_data_0),
.io_w_req_bits_data_5 (io_w_req_bits_data_1),
.io_w_req_bits_data_6 (io_w_req_bits_data_0),
.io_w_req_bits_data_7 (io_w_req_bits_data_1),
.io_w_req_bits_data_8 (io_w_req_bits_data_0),
.io_w_req_bits_data_9 (io_w_req_bits_data_1),
.io_w_req_bits_data_10 (io_w_req_bits_data_0),
.io_w_req_bits_data_11 (io_w_req_bits_data_1),
.io_w_req_bits_data_12 (io_w_req_bits_data_0),
.io_w_req_bits_data_13 (io_w_req_bits_data_1),
.io_w_req_bits_data_14 (io_w_req_bits_data_0),
.io_w_req_bits_data_15 (io_w_req_bits_data_1),
.io_w_req_bits_waymask
({(&(io_w_req_bits_setIdx[2:0])) & io_w_req_bits_waymask[1],
(&(io_w_req_bits_setIdx[2:0])) & io_w_req_bits_waymask[0],
_wmask_T_39 & io_w_req_bits_waymask[1],
_wmask_T_39 & io_w_req_bits_waymask[0],
_wmask_T_33 & io_w_req_bits_waymask[1],
_wmask_T_33 & io_w_req_bits_waymask[0],
_wmask_T_27 & io_w_req_bits_waymask[1],
_wmask_T_27 & io_w_req_bits_waymask[0],
_wmask_T_21 & io_w_req_bits_waymask[1],
_wmask_T_21 & io_w_req_bits_waymask[0],
_wmask_T_15 & io_w_req_bits_waymask[1],
_wmask_T_15 & io_w_req_bits_waymask[0],
_wmask_T_9 & io_w_req_bits_waymask[1],
_wmask_T_9 & io_w_req_bits_waymask[0],
_wmask_T_3 & io_w_req_bits_waymask[1],
_wmask_T_3 & io_w_req_bits_waymask[0]}),
.extra_reset (extra_reset)
);
assign io_r_resp_data_0 =
holdRidx == 3'h0 & _array_io_r_resp_data_0 | holdRidx == 3'h1
& _array_io_r_resp_data_2 | holdRidx == 3'h2 & _array_io_r_resp_data_4
| holdRidx == 3'h3 & _array_io_r_resp_data_6 | holdRidx == 3'h4
& _array_io_r_resp_data_8 | holdRidx == 3'h5 & _array_io_r_resp_data_10
| holdRidx == 3'h6 & _array_io_r_resp_data_12 | (&holdRidx)
& _array_io_r_resp_data_14;
assign io_r_resp_data_1 =
holdRidx_1 == 3'h0 & _array_io_r_resp_data_1 | holdRidx_1 == 3'h1
& _array_io_r_resp_data_3 | holdRidx_1 == 3'h2 & _array_io_r_resp_data_5
| holdRidx_1 == 3'h3 & _array_io_r_resp_data_7 | holdRidx_1 == 3'h4
& _array_io_r_resp_data_9 | holdRidx_1 == 3'h5 & _array_io_r_resp_data_11
| holdRidx_1 == 3'h6 & _array_io_r_resp_data_13 | (&holdRidx_1)
& _array_io_r_resp_data_15;
endmodule

100
rtl/BPUTop/FoldedSRAMTemplate_1.sv
View File

@ -1,100 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module FoldedSRAMTemplate_1(
input clock,
input reset,
output io_r_req_ready,
input io_r_req_valid,
input [8:0] io_r_req_bits_setIdx,
output io_r_resp_data_0_valid,
output [7:0] io_r_resp_data_0_tag,
output [2:0] io_r_resp_data_0_ctr,
output io_r_resp_data_1_valid,
output [7:0] io_r_resp_data_1_tag,
output [2:0] io_r_resp_data_1_ctr,
input io_w_req_valid,
input [8:0] io_w_req_bits_setIdx,
input [7:0] io_w_req_bits_data_0_tag,
input [2:0] io_w_req_bits_data_0_ctr,
input [7:0] io_w_req_bits_data_1_tag,
input [2:0] io_w_req_bits_data_1_ctr,
input [1:0] io_w_req_bits_waymask
);
SRAMTemplate_15 array (
.clock (clock),
.reset (reset),
.io_r_req_ready (io_r_req_ready),
.io_r_req_valid (io_r_req_valid),
.io_r_req_bits_setIdx (io_r_req_bits_setIdx),
.io_r_resp_data_0_valid (io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (io_r_resp_data_1_ctr),
.io_w_req_valid (io_w_req_valid),
.io_w_req_bits_setIdx (io_w_req_bits_setIdx),
.io_w_req_bits_data_0_tag (io_w_req_bits_data_0_tag),
.io_w_req_bits_data_0_ctr (io_w_req_bits_data_0_ctr),
.io_w_req_bits_data_1_tag (io_w_req_bits_data_1_tag),
.io_w_req_bits_data_1_ctr (io_w_req_bits_data_1_ctr),
.io_w_req_bits_waymask (io_w_req_bits_waymask)
);
endmodule

180
rtl/BPUTop/FoldedSRAMTemplate_20.sv
View File

@ -1,180 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module FoldedSRAMTemplate_20(
input clock,
input reset,
input io_r_req_valid,
input [10:0] io_r_req_bits_setIdx,
output [1:0] io_r_resp_data_0,
output [1:0] io_r_resp_data_1,
input io_w_req_valid,
input [10:0] io_w_req_bits_setIdx,
input [1:0] io_w_req_bits_data_0,
input [1:0] io_w_req_bits_data_1,
input [1:0] io_w_req_bits_waymask
);
wire [1:0] _array_io_r_resp_data_0;
wire [1:0] _array_io_r_resp_data_1;
wire [1:0] _array_io_r_resp_data_2;
wire [1:0] _array_io_r_resp_data_3;
wire [1:0] _array_io_r_resp_data_4;
wire [1:0] _array_io_r_resp_data_5;
wire [1:0] _array_io_r_resp_data_6;
wire [1:0] _array_io_r_resp_data_7;
reg [1:0] ridx;
reg holdRidx_last_r;
reg [1:0] holdRidx_hold_data;
wire [1:0] holdRidx = holdRidx_last_r ? ridx : holdRidx_hold_data;
reg holdRidx_last_r_1;
reg [1:0] holdRidx_hold_data_1;
wire [1:0] holdRidx_1 = holdRidx_last_r_1 ? ridx : holdRidx_hold_data_1;
wire _wmask_T_3 = io_w_req_bits_setIdx[1:0] == 2'h0;
wire _wmask_T_9 = io_w_req_bits_setIdx[1:0] == 2'h1;
wire _wmask_T_15 = io_w_req_bits_setIdx[1:0] == 2'h2;
always @(posedge clock) begin
if (io_r_req_valid)
ridx <= io_r_req_bits_setIdx[1:0];
if (holdRidx_last_r)
holdRidx_hold_data <= ridx;
if (holdRidx_last_r_1)
holdRidx_hold_data_1 <= ridx;
end // always @(posedge)
always @(posedge clock or posedge reset) begin
if (reset) begin
holdRidx_last_r <= 1'h0;
holdRidx_last_r_1 <= 1'h0;
end
else begin
if (io_r_req_valid | holdRidx_last_r)
holdRidx_last_r <= io_r_req_valid;
if (io_r_req_valid | holdRidx_last_r_1)
holdRidx_last_r_1 <= io_r_req_valid;
end
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
ridx = _RANDOM[/*Zero width*/ 1'b0][1:0];
holdRidx_last_r = _RANDOM[/*Zero width*/ 1'b0][2];
holdRidx_hold_data = _RANDOM[/*Zero width*/ 1'b0][4:3];
holdRidx_last_r_1 = _RANDOM[/*Zero width*/ 1'b0][5];
holdRidx_hold_data_1 = _RANDOM[/*Zero width*/ 1'b0][7:6];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
holdRidx_last_r = 1'h0;
holdRidx_last_r_1 = 1'h0;
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
SRAMTemplate_34 array (
.clock (clock),
.reset (reset),
.io_r_req_valid (io_r_req_valid),
.io_r_req_bits_setIdx (io_r_req_bits_setIdx[10:2]),
.io_r_resp_data_0 (_array_io_r_resp_data_0),
.io_r_resp_data_1 (_array_io_r_resp_data_1),
.io_r_resp_data_2 (_array_io_r_resp_data_2),
.io_r_resp_data_3 (_array_io_r_resp_data_3),
.io_r_resp_data_4 (_array_io_r_resp_data_4),
.io_r_resp_data_5 (_array_io_r_resp_data_5),
.io_r_resp_data_6 (_array_io_r_resp_data_6),
.io_r_resp_data_7 (_array_io_r_resp_data_7),
.io_w_req_valid (io_w_req_valid),
.io_w_req_bits_setIdx (io_w_req_bits_setIdx[10:2]),
.io_w_req_bits_data_0 (io_w_req_bits_data_0),
.io_w_req_bits_data_1 (io_w_req_bits_data_1),
.io_w_req_bits_data_2 (io_w_req_bits_data_0),
.io_w_req_bits_data_3 (io_w_req_bits_data_1),
.io_w_req_bits_data_4 (io_w_req_bits_data_0),
.io_w_req_bits_data_5 (io_w_req_bits_data_1),
.io_w_req_bits_data_6 (io_w_req_bits_data_0),
.io_w_req_bits_data_7 (io_w_req_bits_data_1),
.io_w_req_bits_waymask
({(&(io_w_req_bits_setIdx[1:0])) & io_w_req_bits_waymask[1],
(&(io_w_req_bits_setIdx[1:0])) & io_w_req_bits_waymask[0],
_wmask_T_15 & io_w_req_bits_waymask[1],
_wmask_T_15 & io_w_req_bits_waymask[0],
_wmask_T_9 & io_w_req_bits_waymask[1],
_wmask_T_9 & io_w_req_bits_waymask[0],
_wmask_T_3 & io_w_req_bits_waymask[1],
_wmask_T_3 & io_w_req_bits_waymask[0]})
);
assign io_r_resp_data_0 =
(holdRidx == 2'h0 ? _array_io_r_resp_data_0 : 2'h0)
| (holdRidx == 2'h1 ? _array_io_r_resp_data_2 : 2'h0)
| (holdRidx == 2'h2 ? _array_io_r_resp_data_4 : 2'h0)
| ((&holdRidx) ? _array_io_r_resp_data_6 : 2'h0);
assign io_r_resp_data_1 =
(holdRidx_1 == 2'h0 ? _array_io_r_resp_data_1 : 2'h0)
| (holdRidx_1 == 2'h1 ? _array_io_r_resp_data_3 : 2'h0)
| (holdRidx_1 == 2'h2 ? _array_io_r_resp_data_5 : 2'h0)
| ((&holdRidx_1) ? _array_io_r_resp_data_7 : 2'h0);
endmodule

90
rtl/BPUTop/FoldedSRAMTemplate_21.sv
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@ -1,90 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module FoldedSRAMTemplate_21(
input clock,
input reset,
input io_r_req_valid,
input [6:0] io_r_req_bits_setIdx,
output io_r_resp_data_0_valid,
output [8:0] io_r_resp_data_0_tag,
output [1:0] io_r_resp_data_0_ctr,
output [40:0] io_r_resp_data_0_target,
input io_w_req_valid,
input [6:0] io_w_req_bits_setIdx,
input [8:0] io_w_req_bits_data_0_tag,
input [1:0] io_w_req_bits_data_0_ctr,
input [40:0] io_w_req_bits_data_0_target
);
SRAMTemplate_39 array (
.clock (clock),
.reset (reset),
.io_r_req_valid (io_r_req_valid),
.io_r_req_bits_setIdx (io_r_req_bits_setIdx),
.io_r_resp_data_0_valid (io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (io_r_resp_data_0_ctr),
.io_r_resp_data_0_target (io_r_resp_data_0_target),
.io_w_req_valid (io_w_req_valid),
.io_w_req_bits_setIdx (io_w_req_bits_setIdx),
.io_w_req_bits_data_0_tag (io_w_req_bits_data_0_tag),
.io_w_req_bits_data_0_ctr (io_w_req_bits_data_0_ctr),
.io_w_req_bits_data_0_target (io_w_req_bits_data_0_target)
);
endmodule

155
rtl/BPUTop/FoldedSRAMTemplate_25.sv
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@ -1,155 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module FoldedSRAMTemplate_25(
input clock,
input reset,
input io_r_req_valid,
input [7:0] io_r_req_bits_setIdx,
output io_r_resp_data_0_valid,
output [8:0] io_r_resp_data_0_tag,
output [1:0] io_r_resp_data_0_ctr,
output [40:0] io_r_resp_data_0_target,
input io_w_req_valid,
input [7:0] io_w_req_bits_setIdx,
input [8:0] io_w_req_bits_data_0_tag,
input [1:0] io_w_req_bits_data_0_ctr,
input [40:0] io_w_req_bits_data_0_target
);
wire _array_io_r_resp_data_0_valid;
wire [8:0] _array_io_r_resp_data_0_tag;
wire [1:0] _array_io_r_resp_data_0_ctr;
wire [40:0] _array_io_r_resp_data_0_target;
wire _array_io_r_resp_data_1_valid;
wire [8:0] _array_io_r_resp_data_1_tag;
wire [1:0] _array_io_r_resp_data_1_ctr;
wire [40:0] _array_io_r_resp_data_1_target;
reg ridx;
reg holdRidx_last_r;
reg holdRidx_hold_data;
wire holdRidx = holdRidx_last_r ? ridx : holdRidx_hold_data;
always @(posedge clock) begin
if (io_r_req_valid)
ridx <= io_r_req_bits_setIdx[0];
if (holdRidx_last_r)
holdRidx_hold_data <= ridx;
end // always @(posedge)
always @(posedge clock or posedge reset) begin
if (reset)
holdRidx_last_r <= 1'h0;
else if (io_r_req_valid | holdRidx_last_r)
holdRidx_last_r <= io_r_req_valid;
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
ridx = _RANDOM[/*Zero width*/ 1'b0][0];
holdRidx_last_r = _RANDOM[/*Zero width*/ 1'b0][1];
holdRidx_hold_data = _RANDOM[/*Zero width*/ 1'b0][2];
`endif // RANDOMIZE_REG_INIT
if (reset)
holdRidx_last_r = 1'h0;
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
SRAMTemplate_43 array (
.clock (clock),
.reset (reset),
.io_r_req_valid (io_r_req_valid),
.io_r_req_bits_setIdx (io_r_req_bits_setIdx[7:1]),
.io_r_resp_data_0_valid (_array_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_array_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_array_io_r_resp_data_0_ctr),
.io_r_resp_data_0_target (_array_io_r_resp_data_0_target),
.io_r_resp_data_1_valid (_array_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_array_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_array_io_r_resp_data_1_ctr),
.io_r_resp_data_1_target (_array_io_r_resp_data_1_target),
.io_w_req_valid (io_w_req_valid),
.io_w_req_bits_setIdx (io_w_req_bits_setIdx[7:1]),
.io_w_req_bits_data_0_tag (io_w_req_bits_data_0_tag),
.io_w_req_bits_data_0_ctr (io_w_req_bits_data_0_ctr),
.io_w_req_bits_data_0_target (io_w_req_bits_data_0_target),
.io_w_req_bits_data_1_tag (io_w_req_bits_data_0_tag),
.io_w_req_bits_data_1_ctr (io_w_req_bits_data_0_ctr),
.io_w_req_bits_data_1_target (io_w_req_bits_data_0_target),
.io_w_req_bits_waymask (2'h1 << io_w_req_bits_setIdx[0])
);
assign io_r_resp_data_0_valid =
~holdRidx & _array_io_r_resp_data_0_valid | holdRidx & _array_io_r_resp_data_1_valid;
assign io_r_resp_data_0_tag =
(holdRidx ? 9'h0 : _array_io_r_resp_data_0_tag)
| (holdRidx ? _array_io_r_resp_data_1_tag : 9'h0);
assign io_r_resp_data_0_ctr =
(holdRidx ? 2'h0 : _array_io_r_resp_data_0_ctr)
| (holdRidx ? _array_io_r_resp_data_1_ctr : 2'h0);
assign io_r_resp_data_0_target =
(holdRidx ? 41'h0 : _array_io_r_resp_data_0_target)
| (holdRidx ? _array_io_r_resp_data_1_target : 41'h0);
endmodule

1269
rtl/BPUTop/ITTage.sv
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226
rtl/BPUTop/ITTageTable.sv
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@ -1,226 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module ITTageTable(
input clock,
input reset,
input io_req_valid,
input [40:0] io_req_bits_pc,
input [3:0] io_req_bits_folded_hist_hist_12_folded_hist,
output io_resp_valid,
output [1:0] io_resp_bits_ctr,
output [1:0] io_resp_bits_u,
output [40:0] io_resp_bits_target,
input [40:0] io_update_pc,
input [3:0] io_update_folded_hist_hist_12_folded_hist,
input io_update_valid,
input io_update_correct,
input io_update_alloc,
input [1:0] io_update_oldCtr,
input io_update_uValid,
input io_update_u,
input io_update_reset_u,
input [40:0] io_update_target,
input [40:0] io_update_old_target
);
wire _resp_invalid_by_write_T_2;
wire _wrbypass_io_hit;
wire [1:0] _wrbypass_io_hit_data_0_bits;
wire _table_banks_1_io_r_resp_data_0_valid;
wire [8:0] _table_banks_1_io_r_resp_data_0_tag;
wire [1:0] _table_banks_1_io_r_resp_data_0_ctr;
wire [40:0] _table_banks_1_io_r_resp_data_0_target;
wire _table_banks_0_io_r_resp_data_0_valid;
wire [8:0] _table_banks_0_io_r_resp_data_0_tag;
wire [1:0] _table_banks_0_io_r_resp_data_0_ctr;
wire [40:0] _table_banks_0_io_r_resp_data_0_target;
wire _us_io_rdata_0;
wire [3:0] _GEN = io_req_bits_pc[4:1] ^ io_req_bits_folded_hist_hist_12_folded_hist;
reg [8:0] s1_tag;
reg s1_bank_req_1h_0;
reg s1_bank_req_1h_1;
wire [6:0] _table_banks_1_io_r_req_bits_setIdx_T = {io_req_bits_pc[8:5], _GEN[3:1]};
reg s1_bank_has_write_on_this_req_0;
reg s1_bank_has_write_on_this_req_1;
wire [3:0] _GEN_0 = io_update_pc[4:1] ^ io_update_folded_hist_hist_12_folded_hist;
wire [7:0] update_idx = {io_update_pc[8:5], _GEN_0};
wire [8:0] update_tag =
{io_update_pc[17:14],
{io_update_pc[13], io_update_pc[12:9] ^ io_update_folded_hist_hist_12_folded_hist}
^ {io_update_folded_hist_hist_12_folded_hist, 1'h0}};
wire [6:0] update_idx_in_bank = {io_update_pc[8:5], _GEN_0[3:1]};
assign _resp_invalid_by_write_T_2 =
s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1
& s1_bank_has_write_on_this_req_1;
wire _s1_bank_has_write_on_this_req_WIRE_0 = io_update_valid & ~(_GEN_0[0]);
wire _s1_bank_has_write_on_this_req_WIRE_1 = io_update_valid & _GEN_0[0];
wire [1:0] old_ctr =
_wrbypass_io_hit ? _wrbypass_io_hit_data_0_bits : io_update_oldCtr;
wire update_wdata_ctr_oldSatNotTaken = old_ctr == 2'h0;
wire [1:0] update_wdata_ctr =
io_update_alloc
? 2'h2
: (&old_ctr) & io_update_correct
? 2'h3
: update_wdata_ctr_oldSatNotTaken & ~io_update_correct
? 2'h0
: io_update_correct ? 2'(old_ctr + 2'h1) : 2'(old_ctr - 2'h1);
wire [40:0] update_wdata_target =
io_update_alloc | update_wdata_ctr_oldSatNotTaken
? io_update_target
: io_update_old_target;
always @(posedge clock) begin
if (io_req_valid) begin
s1_tag <=
{io_req_bits_pc[17:14],
{io_req_bits_pc[13],
io_req_bits_pc[12:9] ^ io_req_bits_folded_hist_hist_12_folded_hist}
^ {io_req_bits_folded_hist_hist_12_folded_hist, 1'h0}};
s1_bank_req_1h_0 <= ~(_GEN[0]);
s1_bank_req_1h_1 <= _GEN[0];
s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0;
s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1;
end
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
s1_tag = _RANDOM[/*Zero width*/ 1'b0][16:8];
s1_bank_req_1h_0 = _RANDOM[/*Zero width*/ 1'b0][17];
s1_bank_req_1h_1 = _RANDOM[/*Zero width*/ 1'b0][18];
s1_bank_has_write_on_this_req_0 = _RANDOM[/*Zero width*/ 1'b0][19];
s1_bank_has_write_on_this_req_1 = _RANDOM[/*Zero width*/ 1'b0][20];
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
Folded1WDataModuleTemplate us (
.clock (clock),
.reset (reset),
.io_ren_0 (io_req_valid),
.io_raddr_0 ({io_req_bits_pc[8:5], _GEN}),
.io_rdata_0 (_us_io_rdata_0),
.io_wen (io_update_uValid),
.io_waddr (update_idx),
.io_wdata (io_update_u),
.io_resetEn (io_update_reset_u)
);
FoldedSRAMTemplate_21 table_banks_0 (
.clock (clock),
.reset (reset),
.io_r_req_valid (io_req_valid & ~(_GEN[0])),
.io_r_req_bits_setIdx (_table_banks_1_io_r_req_bits_setIdx_T),
.io_r_resp_data_0_valid (_table_banks_0_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr),
.io_r_resp_data_0_target (_table_banks_0_io_r_resp_data_0_target),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0),
.io_w_req_bits_setIdx (update_idx_in_bank),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (update_wdata_ctr),
.io_w_req_bits_data_0_target (update_wdata_target)
);
FoldedSRAMTemplate_21 table_banks_1 (
.clock (clock),
.reset (reset),
.io_r_req_valid (io_req_valid & _GEN[0]),
.io_r_req_bits_setIdx (_table_banks_1_io_r_req_bits_setIdx_T),
.io_r_resp_data_0_valid (_table_banks_1_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr),
.io_r_resp_data_0_target (_table_banks_1_io_r_resp_data_0_target),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1),
.io_w_req_bits_setIdx (update_idx_in_bank),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (update_wdata_ctr),
.io_w_req_bits_data_0_target (update_wdata_target)
);
WrBypass_41 wrbypass (
.clock (clock),
.reset (reset),
.io_wen (io_update_valid),
.io_write_idx (update_idx),
.io_write_data_0 (update_wdata_ctr),
.io_hit (_wrbypass_io_hit),
.io_hit_data_0_bits (_wrbypass_io_hit_data_0_bits)
);
assign io_resp_valid =
(s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_0_valid | s1_bank_req_1h_1
& _table_banks_1_io_r_resp_data_0_valid)
& ((s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_tag : 9'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_tag : 9'h0)) == s1_tag
& ~_resp_invalid_by_write_T_2;
assign io_resp_bits_ctr =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 2'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 2'h0);
assign io_resp_bits_u = {1'h0, _us_io_rdata_0};
assign io_resp_bits_target =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_target : 41'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_target : 41'h0);
endmodule

221
rtl/BPUTop/ITTageTable_1.sv
View File

@ -1,221 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module ITTageTable_1(
input clock,
input reset,
input io_req_valid,
input [40:0] io_req_bits_pc,
input [7:0] io_req_bits_folded_hist_hist_14_folded_hist,
output io_resp_valid,
output [1:0] io_resp_bits_ctr,
output [1:0] io_resp_bits_u,
output [40:0] io_resp_bits_target,
input [40:0] io_update_pc,
input [7:0] io_update_folded_hist_hist_14_folded_hist,
input io_update_valid,
input io_update_correct,
input io_update_alloc,
input [1:0] io_update_oldCtr,
input io_update_uValid,
input io_update_u,
input io_update_reset_u,
input [40:0] io_update_target,
input [40:0] io_update_old_target
);
wire _resp_invalid_by_write_T_2;
wire _wrbypass_io_hit;
wire [1:0] _wrbypass_io_hit_data_0_bits;
wire _table_banks_1_io_r_resp_data_0_valid;
wire [8:0] _table_banks_1_io_r_resp_data_0_tag;
wire [1:0] _table_banks_1_io_r_resp_data_0_ctr;
wire [40:0] _table_banks_1_io_r_resp_data_0_target;
wire _table_banks_0_io_r_resp_data_0_valid;
wire [8:0] _table_banks_0_io_r_resp_data_0_tag;
wire [1:0] _table_banks_0_io_r_resp_data_0_ctr;
wire [40:0] _table_banks_0_io_r_resp_data_0_target;
wire _us_io_rdata_0;
wire [7:0] s0_idx = io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_14_folded_hist;
reg [8:0] s1_tag;
reg s1_bank_req_1h_0;
reg s1_bank_req_1h_1;
reg s1_bank_has_write_on_this_req_0;
reg s1_bank_has_write_on_this_req_1;
wire [7:0] update_idx = io_update_pc[8:1] ^ io_update_folded_hist_hist_14_folded_hist;
wire [8:0] update_tag =
{io_update_pc[17], io_update_pc[16:9] ^ io_update_folded_hist_hist_14_folded_hist}
^ {io_update_folded_hist_hist_14_folded_hist, 1'h0};
assign _resp_invalid_by_write_T_2 =
s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1
& s1_bank_has_write_on_this_req_1;
wire _s1_bank_has_write_on_this_req_WIRE_0 = io_update_valid & ~(update_idx[0]);
wire _s1_bank_has_write_on_this_req_WIRE_1 = io_update_valid & update_idx[0];
wire [1:0] old_ctr =
_wrbypass_io_hit ? _wrbypass_io_hit_data_0_bits : io_update_oldCtr;
wire update_wdata_ctr_oldSatNotTaken = old_ctr == 2'h0;
wire [1:0] update_wdata_ctr =
io_update_alloc
? 2'h2
: (&old_ctr) & io_update_correct
? 2'h3
: update_wdata_ctr_oldSatNotTaken & ~io_update_correct
? 2'h0
: io_update_correct ? 2'(old_ctr + 2'h1) : 2'(old_ctr - 2'h1);
wire [40:0] update_wdata_target =
io_update_alloc | update_wdata_ctr_oldSatNotTaken
? io_update_target
: io_update_old_target;
always @(posedge clock) begin
if (io_req_valid) begin
s1_tag <=
{io_req_bits_pc[17],
io_req_bits_pc[16:9] ^ io_req_bits_folded_hist_hist_14_folded_hist}
^ {io_req_bits_folded_hist_hist_14_folded_hist, 1'h0};
s1_bank_req_1h_0 <= ~(s0_idx[0]);
s1_bank_req_1h_1 <= s0_idx[0];
s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0;
s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1;
end
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
s1_tag = _RANDOM[/*Zero width*/ 1'b0][16:8];
s1_bank_req_1h_0 = _RANDOM[/*Zero width*/ 1'b0][17];
s1_bank_req_1h_1 = _RANDOM[/*Zero width*/ 1'b0][18];
s1_bank_has_write_on_this_req_0 = _RANDOM[/*Zero width*/ 1'b0][19];
s1_bank_has_write_on_this_req_1 = _RANDOM[/*Zero width*/ 1'b0][20];
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
Folded1WDataModuleTemplate us (
.clock (clock),
.reset (reset),
.io_ren_0 (io_req_valid),
.io_raddr_0 (s0_idx),
.io_rdata_0 (_us_io_rdata_0),
.io_wen (io_update_uValid),
.io_waddr (update_idx),
.io_wdata (io_update_u),
.io_resetEn (io_update_reset_u)
);
FoldedSRAMTemplate_21 table_banks_0 (
.clock (clock),
.reset (reset),
.io_r_req_valid (io_req_valid & ~(s0_idx[0])),
.io_r_req_bits_setIdx (s0_idx[7:1]),
.io_r_resp_data_0_valid (_table_banks_0_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr),
.io_r_resp_data_0_target (_table_banks_0_io_r_resp_data_0_target),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0),
.io_w_req_bits_setIdx (update_idx[7:1]),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (update_wdata_ctr),
.io_w_req_bits_data_0_target (update_wdata_target)
);
FoldedSRAMTemplate_21 table_banks_1 (
.clock (clock),
.reset (reset),
.io_r_req_valid (io_req_valid & s0_idx[0]),
.io_r_req_bits_setIdx (s0_idx[7:1]),
.io_r_resp_data_0_valid (_table_banks_1_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr),
.io_r_resp_data_0_target (_table_banks_1_io_r_resp_data_0_target),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1),
.io_w_req_bits_setIdx (update_idx[7:1]),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (update_wdata_ctr),
.io_w_req_bits_data_0_target (update_wdata_target)
);
WrBypass_41 wrbypass (
.clock (clock),
.reset (reset),
.io_wen (io_update_valid),
.io_write_idx (update_idx),
.io_write_data_0 (update_wdata_ctr),
.io_hit (_wrbypass_io_hit),
.io_hit_data_0_bits (_wrbypass_io_hit_data_0_bits)
);
assign io_resp_valid =
(s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_0_valid | s1_bank_req_1h_1
& _table_banks_1_io_r_resp_data_0_valid)
& ((s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_tag : 9'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_tag : 9'h0)) == s1_tag
& ~_resp_invalid_by_write_T_2;
assign io_resp_bits_ctr =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 2'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 2'h0);
assign io_resp_bits_u = {1'h0, _us_io_rdata_0};
assign io_resp_bits_target =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_target : 41'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_target : 41'h0);
endmodule

222
rtl/BPUTop/ITTageTable_2.sv
View File

@ -1,222 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module ITTageTable_2(
input clock,
input reset,
input io_req_valid,
input [40:0] io_req_bits_pc,
input [8:0] io_req_bits_folded_hist_hist_13_folded_hist,
input [7:0] io_req_bits_folded_hist_hist_4_folded_hist,
output io_resp_valid,
output [1:0] io_resp_bits_ctr,
output [1:0] io_resp_bits_u,
output [40:0] io_resp_bits_target,
input [40:0] io_update_pc,
input [8:0] io_update_folded_hist_hist_13_folded_hist,
input [7:0] io_update_folded_hist_hist_4_folded_hist,
input io_update_valid,
input io_update_correct,
input io_update_alloc,
input [1:0] io_update_oldCtr,
input io_update_uValid,
input io_update_u,
input io_update_reset_u,
input [40:0] io_update_target,
input [40:0] io_update_old_target
);
wire _resp_invalid_by_write_T_2;
wire _wrbypass_io_hit;
wire [1:0] _wrbypass_io_hit_data_0_bits;
wire _table_banks_1_io_r_resp_data_0_valid;
wire [8:0] _table_banks_1_io_r_resp_data_0_tag;
wire [1:0] _table_banks_1_io_r_resp_data_0_ctr;
wire [40:0] _table_banks_1_io_r_resp_data_0_target;
wire _table_banks_0_io_r_resp_data_0_valid;
wire [8:0] _table_banks_0_io_r_resp_data_0_tag;
wire [1:0] _table_banks_0_io_r_resp_data_0_ctr;
wire [40:0] _table_banks_0_io_r_resp_data_0_target;
wire _us_io_rdata_0;
wire [8:0] s0_idx = io_req_bits_pc[9:1] ^ io_req_bits_folded_hist_hist_13_folded_hist;
reg [8:0] s1_tag;
reg s1_bank_req_1h_0;
reg s1_bank_req_1h_1;
reg s1_bank_has_write_on_this_req_0;
reg s1_bank_has_write_on_this_req_1;
wire [8:0] update_idx = io_update_pc[9:1] ^ io_update_folded_hist_hist_13_folded_hist;
wire [8:0] update_tag =
io_update_pc[18:10] ^ io_update_folded_hist_hist_13_folded_hist
^ {io_update_folded_hist_hist_4_folded_hist, 1'h0};
assign _resp_invalid_by_write_T_2 =
s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1
& s1_bank_has_write_on_this_req_1;
wire _s1_bank_has_write_on_this_req_WIRE_0 = io_update_valid & ~(update_idx[0]);
wire _s1_bank_has_write_on_this_req_WIRE_1 = io_update_valid & update_idx[0];
wire [1:0] old_ctr =
_wrbypass_io_hit ? _wrbypass_io_hit_data_0_bits : io_update_oldCtr;
wire update_wdata_ctr_oldSatNotTaken = old_ctr == 2'h0;
wire [1:0] update_wdata_ctr =
io_update_alloc
? 2'h2
: (&old_ctr) & io_update_correct
? 2'h3
: update_wdata_ctr_oldSatNotTaken & ~io_update_correct
? 2'h0
: io_update_correct ? 2'(old_ctr + 2'h1) : 2'(old_ctr - 2'h1);
wire [40:0] update_wdata_target =
io_update_alloc | update_wdata_ctr_oldSatNotTaken
? io_update_target
: io_update_old_target;
always @(posedge clock) begin
if (io_req_valid) begin
s1_tag <=
io_req_bits_pc[18:10] ^ io_req_bits_folded_hist_hist_13_folded_hist
^ {io_req_bits_folded_hist_hist_4_folded_hist, 1'h0};
s1_bank_req_1h_0 <= ~(s0_idx[0]);
s1_bank_req_1h_1 <= s0_idx[0];
s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0;
s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1;
end
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
s1_tag = _RANDOM[/*Zero width*/ 1'b0][17:9];
s1_bank_req_1h_0 = _RANDOM[/*Zero width*/ 1'b0][18];
s1_bank_req_1h_1 = _RANDOM[/*Zero width*/ 1'b0][19];
s1_bank_has_write_on_this_req_0 = _RANDOM[/*Zero width*/ 1'b0][20];
s1_bank_has_write_on_this_req_1 = _RANDOM[/*Zero width*/ 1'b0][21];
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
Folded1WDataModuleTemplate_2 us (
.clock (clock),
.reset (reset),
.io_ren_0 (io_req_valid),
.io_raddr_0 (s0_idx),
.io_rdata_0 (_us_io_rdata_0),
.io_wen (io_update_uValid),
.io_waddr (update_idx),
.io_wdata (io_update_u),
.io_resetEn (io_update_reset_u)
);
FoldedSRAMTemplate_25 table_banks_0 (
.clock (clock),
.reset (reset),
.io_r_req_valid (io_req_valid & ~(s0_idx[0])),
.io_r_req_bits_setIdx (s0_idx[8:1]),
.io_r_resp_data_0_valid (_table_banks_0_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr),
.io_r_resp_data_0_target (_table_banks_0_io_r_resp_data_0_target),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0),
.io_w_req_bits_setIdx (update_idx[8:1]),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (update_wdata_ctr),
.io_w_req_bits_data_0_target (update_wdata_target)
);
FoldedSRAMTemplate_25 table_banks_1 (
.clock (clock),
.reset (reset),
.io_r_req_valid (io_req_valid & s0_idx[0]),
.io_r_req_bits_setIdx (s0_idx[8:1]),
.io_r_resp_data_0_valid (_table_banks_1_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr),
.io_r_resp_data_0_target (_table_banks_1_io_r_resp_data_0_target),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1),
.io_w_req_bits_setIdx (update_idx[8:1]),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (update_wdata_ctr),
.io_w_req_bits_data_0_target (update_wdata_target)
);
WrBypass_43 wrbypass (
.clock (clock),
.reset (reset),
.io_wen (io_update_valid),
.io_write_idx (update_idx),
.io_write_data_0 (update_wdata_ctr),
.io_hit (_wrbypass_io_hit),
.io_hit_data_0_bits (_wrbypass_io_hit_data_0_bits)
);
assign io_resp_valid =
(s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_0_valid | s1_bank_req_1h_1
& _table_banks_1_io_r_resp_data_0_valid)
& ((s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_tag : 9'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_tag : 9'h0)) == s1_tag
& ~_resp_invalid_by_write_T_2;
assign io_resp_bits_ctr =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 2'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 2'h0);
assign io_resp_bits_u = {1'h0, _us_io_rdata_0};
assign io_resp_bits_target =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_target : 41'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_target : 41'h0);
endmodule

222
rtl/BPUTop/ITTageTable_3.sv
View File

@ -1,222 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module ITTageTable_3(
input clock,
input reset,
input io_req_valid,
input [40:0] io_req_bits_pc,
input [8:0] io_req_bits_folded_hist_hist_6_folded_hist,
input [7:0] io_req_bits_folded_hist_hist_2_folded_hist,
output io_resp_valid,
output [1:0] io_resp_bits_ctr,
output [1:0] io_resp_bits_u,
output [40:0] io_resp_bits_target,
input [40:0] io_update_pc,
input [8:0] io_update_folded_hist_hist_6_folded_hist,
input [7:0] io_update_folded_hist_hist_2_folded_hist,
input io_update_valid,
input io_update_correct,
input io_update_alloc,
input [1:0] io_update_oldCtr,
input io_update_uValid,
input io_update_u,
input io_update_reset_u,
input [40:0] io_update_target,
input [40:0] io_update_old_target
);
wire _resp_invalid_by_write_T_2;
wire _wrbypass_io_hit;
wire [1:0] _wrbypass_io_hit_data_0_bits;
wire _table_banks_1_io_r_resp_data_0_valid;
wire [8:0] _table_banks_1_io_r_resp_data_0_tag;
wire [1:0] _table_banks_1_io_r_resp_data_0_ctr;
wire [40:0] _table_banks_1_io_r_resp_data_0_target;
wire _table_banks_0_io_r_resp_data_0_valid;
wire [8:0] _table_banks_0_io_r_resp_data_0_tag;
wire [1:0] _table_banks_0_io_r_resp_data_0_ctr;
wire [40:0] _table_banks_0_io_r_resp_data_0_target;
wire _us_io_rdata_0;
wire [8:0] s0_idx = io_req_bits_pc[9:1] ^ io_req_bits_folded_hist_hist_6_folded_hist;
reg [8:0] s1_tag;
reg s1_bank_req_1h_0;
reg s1_bank_req_1h_1;
reg s1_bank_has_write_on_this_req_0;
reg s1_bank_has_write_on_this_req_1;
wire [8:0] update_idx = io_update_pc[9:1] ^ io_update_folded_hist_hist_6_folded_hist;
wire [8:0] update_tag =
io_update_pc[18:10] ^ io_update_folded_hist_hist_6_folded_hist
^ {io_update_folded_hist_hist_2_folded_hist, 1'h0};
assign _resp_invalid_by_write_T_2 =
s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1
& s1_bank_has_write_on_this_req_1;
wire _s1_bank_has_write_on_this_req_WIRE_0 = io_update_valid & ~(update_idx[0]);
wire _s1_bank_has_write_on_this_req_WIRE_1 = io_update_valid & update_idx[0];
wire [1:0] old_ctr =
_wrbypass_io_hit ? _wrbypass_io_hit_data_0_bits : io_update_oldCtr;
wire update_wdata_ctr_oldSatNotTaken = old_ctr == 2'h0;
wire [1:0] update_wdata_ctr =
io_update_alloc
? 2'h2
: (&old_ctr) & io_update_correct
? 2'h3
: update_wdata_ctr_oldSatNotTaken & ~io_update_correct
? 2'h0
: io_update_correct ? 2'(old_ctr + 2'h1) : 2'(old_ctr - 2'h1);
wire [40:0] update_wdata_target =
io_update_alloc | update_wdata_ctr_oldSatNotTaken
? io_update_target
: io_update_old_target;
always @(posedge clock) begin
if (io_req_valid) begin
s1_tag <=
io_req_bits_pc[18:10] ^ io_req_bits_folded_hist_hist_6_folded_hist
^ {io_req_bits_folded_hist_hist_2_folded_hist, 1'h0};
s1_bank_req_1h_0 <= ~(s0_idx[0]);
s1_bank_req_1h_1 <= s0_idx[0];
s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0;
s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1;
end
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
s1_tag = _RANDOM[/*Zero width*/ 1'b0][17:9];
s1_bank_req_1h_0 = _RANDOM[/*Zero width*/ 1'b0][18];
s1_bank_req_1h_1 = _RANDOM[/*Zero width*/ 1'b0][19];
s1_bank_has_write_on_this_req_0 = _RANDOM[/*Zero width*/ 1'b0][20];
s1_bank_has_write_on_this_req_1 = _RANDOM[/*Zero width*/ 1'b0][21];
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
Folded1WDataModuleTemplate_2 us (
.clock (clock),
.reset (reset),
.io_ren_0 (io_req_valid),
.io_raddr_0 (s0_idx),
.io_rdata_0 (_us_io_rdata_0),
.io_wen (io_update_uValid),
.io_waddr (update_idx),
.io_wdata (io_update_u),
.io_resetEn (io_update_reset_u)
);
FoldedSRAMTemplate_25 table_banks_0 (
.clock (clock),
.reset (reset),
.io_r_req_valid (io_req_valid & ~(s0_idx[0])),
.io_r_req_bits_setIdx (s0_idx[8:1]),
.io_r_resp_data_0_valid (_table_banks_0_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr),
.io_r_resp_data_0_target (_table_banks_0_io_r_resp_data_0_target),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0),
.io_w_req_bits_setIdx (update_idx[8:1]),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (update_wdata_ctr),
.io_w_req_bits_data_0_target (update_wdata_target)
);
FoldedSRAMTemplate_25 table_banks_1 (
.clock (clock),
.reset (reset),
.io_r_req_valid (io_req_valid & s0_idx[0]),
.io_r_req_bits_setIdx (s0_idx[8:1]),
.io_r_resp_data_0_valid (_table_banks_1_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr),
.io_r_resp_data_0_target (_table_banks_1_io_r_resp_data_0_target),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1),
.io_w_req_bits_setIdx (update_idx[8:1]),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (update_wdata_ctr),
.io_w_req_bits_data_0_target (update_wdata_target)
);
WrBypass_43 wrbypass (
.clock (clock),
.reset (reset),
.io_wen (io_update_valid),
.io_write_idx (update_idx),
.io_write_data_0 (update_wdata_ctr),
.io_hit (_wrbypass_io_hit),
.io_hit_data_0_bits (_wrbypass_io_hit_data_0_bits)
);
assign io_resp_valid =
(s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_0_valid | s1_bank_req_1h_1
& _table_banks_1_io_r_resp_data_0_valid)
& ((s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_tag : 9'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_tag : 9'h0)) == s1_tag
& ~_resp_invalid_by_write_T_2;
assign io_resp_bits_ctr =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 2'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 2'h0);
assign io_resp_bits_u = {1'h0, _us_io_rdata_0};
assign io_resp_bits_target =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_target : 41'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_target : 41'h0);
endmodule

222
rtl/BPUTop/ITTageTable_4.sv
View File

@ -1,222 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module ITTageTable_4(
input clock,
input reset,
input io_req_valid,
input [40:0] io_req_bits_pc,
input [8:0] io_req_bits_folded_hist_hist_10_folded_hist,
input [7:0] io_req_bits_folded_hist_hist_3_folded_hist,
output io_resp_valid,
output [1:0] io_resp_bits_ctr,
output [1:0] io_resp_bits_u,
output [40:0] io_resp_bits_target,
input [40:0] io_update_pc,
input [8:0] io_update_folded_hist_hist_10_folded_hist,
input [7:0] io_update_folded_hist_hist_3_folded_hist,
input io_update_valid,
input io_update_correct,
input io_update_alloc,
input [1:0] io_update_oldCtr,
input io_update_uValid,
input io_update_u,
input io_update_reset_u,
input [40:0] io_update_target,
input [40:0] io_update_old_target
);
wire _resp_invalid_by_write_T_2;
wire _wrbypass_io_hit;
wire [1:0] _wrbypass_io_hit_data_0_bits;
wire _table_banks_1_io_r_resp_data_0_valid;
wire [8:0] _table_banks_1_io_r_resp_data_0_tag;
wire [1:0] _table_banks_1_io_r_resp_data_0_ctr;
wire [40:0] _table_banks_1_io_r_resp_data_0_target;
wire _table_banks_0_io_r_resp_data_0_valid;
wire [8:0] _table_banks_0_io_r_resp_data_0_tag;
wire [1:0] _table_banks_0_io_r_resp_data_0_ctr;
wire [40:0] _table_banks_0_io_r_resp_data_0_target;
wire _us_io_rdata_0;
wire [8:0] s0_idx = io_req_bits_pc[9:1] ^ io_req_bits_folded_hist_hist_10_folded_hist;
reg [8:0] s1_tag;
reg s1_bank_req_1h_0;
reg s1_bank_req_1h_1;
reg s1_bank_has_write_on_this_req_0;
reg s1_bank_has_write_on_this_req_1;
wire [8:0] update_idx = io_update_pc[9:1] ^ io_update_folded_hist_hist_10_folded_hist;
wire [8:0] update_tag =
io_update_pc[18:10] ^ io_update_folded_hist_hist_10_folded_hist
^ {io_update_folded_hist_hist_3_folded_hist, 1'h0};
assign _resp_invalid_by_write_T_2 =
s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1
& s1_bank_has_write_on_this_req_1;
wire _s1_bank_has_write_on_this_req_WIRE_0 = io_update_valid & ~(update_idx[0]);
wire _s1_bank_has_write_on_this_req_WIRE_1 = io_update_valid & update_idx[0];
wire [1:0] old_ctr =
_wrbypass_io_hit ? _wrbypass_io_hit_data_0_bits : io_update_oldCtr;
wire update_wdata_ctr_oldSatNotTaken = old_ctr == 2'h0;
wire [1:0] update_wdata_ctr =
io_update_alloc
? 2'h2
: (&old_ctr) & io_update_correct
? 2'h3
: update_wdata_ctr_oldSatNotTaken & ~io_update_correct
? 2'h0
: io_update_correct ? 2'(old_ctr + 2'h1) : 2'(old_ctr - 2'h1);
wire [40:0] update_wdata_target =
io_update_alloc | update_wdata_ctr_oldSatNotTaken
? io_update_target
: io_update_old_target;
always @(posedge clock) begin
if (io_req_valid) begin
s1_tag <=
io_req_bits_pc[18:10] ^ io_req_bits_folded_hist_hist_10_folded_hist
^ {io_req_bits_folded_hist_hist_3_folded_hist, 1'h0};
s1_bank_req_1h_0 <= ~(s0_idx[0]);
s1_bank_req_1h_1 <= s0_idx[0];
s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0;
s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1;
end
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
s1_tag = _RANDOM[/*Zero width*/ 1'b0][17:9];
s1_bank_req_1h_0 = _RANDOM[/*Zero width*/ 1'b0][18];
s1_bank_req_1h_1 = _RANDOM[/*Zero width*/ 1'b0][19];
s1_bank_has_write_on_this_req_0 = _RANDOM[/*Zero width*/ 1'b0][20];
s1_bank_has_write_on_this_req_1 = _RANDOM[/*Zero width*/ 1'b0][21];
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
Folded1WDataModuleTemplate_2 us (
.clock (clock),
.reset (reset),
.io_ren_0 (io_req_valid),
.io_raddr_0 (s0_idx),
.io_rdata_0 (_us_io_rdata_0),
.io_wen (io_update_uValid),
.io_waddr (update_idx),
.io_wdata (io_update_u),
.io_resetEn (io_update_reset_u)
);
FoldedSRAMTemplate_25 table_banks_0 (
.clock (clock),
.reset (reset),
.io_r_req_valid (io_req_valid & ~(s0_idx[0])),
.io_r_req_bits_setIdx (s0_idx[8:1]),
.io_r_resp_data_0_valid (_table_banks_0_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr),
.io_r_resp_data_0_target (_table_banks_0_io_r_resp_data_0_target),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0),
.io_w_req_bits_setIdx (update_idx[8:1]),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (update_wdata_ctr),
.io_w_req_bits_data_0_target (update_wdata_target)
);
FoldedSRAMTemplate_25 table_banks_1 (
.clock (clock),
.reset (reset),
.io_r_req_valid (io_req_valid & s0_idx[0]),
.io_r_req_bits_setIdx (s0_idx[8:1]),
.io_r_resp_data_0_valid (_table_banks_1_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr),
.io_r_resp_data_0_target (_table_banks_1_io_r_resp_data_0_target),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1),
.io_w_req_bits_setIdx (update_idx[8:1]),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (update_wdata_ctr),
.io_w_req_bits_data_0_target (update_wdata_target)
);
WrBypass_43 wrbypass (
.clock (clock),
.reset (reset),
.io_wen (io_update_valid),
.io_write_idx (update_idx),
.io_write_data_0 (update_wdata_ctr),
.io_hit (_wrbypass_io_hit),
.io_hit_data_0_bits (_wrbypass_io_hit_data_0_bits)
);
assign io_resp_valid =
(s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_0_valid | s1_bank_req_1h_1
& _table_banks_1_io_r_resp_data_0_valid)
& ((s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_tag : 9'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_tag : 9'h0)) == s1_tag
& ~_resp_invalid_by_write_T_2;
assign io_resp_bits_ctr =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 2'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 2'h0);
assign io_resp_bits_u = {1'h0, _us_io_rdata_0};
assign io_resp_bits_target =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_target : 41'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_target : 41'h0);
endmodule

33300
rtl/BPUTop/Predictor.sv
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File diff suppressed because it is too large Load Diff

80
rtl/BPUTop/PriorityMuxModule.sv
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@ -1,80 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module PriorityMuxModule(
input s2_target_sel,
input [40:0] s2_target_src,
input s1_target_sel,
input [40:0] s1_target_src,
input s3_target_sel,
input [40:0] s3_target_src,
input redirect_target_sel,
input [40:0] redirect_target_src,
input [40:0] stallPC_src,
output [40:0] out_res
);
assign out_res =
s2_target_sel
? s2_target_src
: s1_target_sel
? s1_target_src
: s3_target_sel
? s3_target_src
: redirect_target_sel ? redirect_target_src : stallPC_src;
endmodule

450
rtl/BPUTop/PriorityMuxModule_12.sv
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@ -1,450 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module PriorityMuxModule_12(
input s2_AFHOB_sel,
input s2_AFHOB_src_afhob_5_bits_0,
input s2_AFHOB_src_afhob_5_bits_1,
input s2_AFHOB_src_afhob_5_bits_2,
input s2_AFHOB_src_afhob_5_bits_3,
input s2_AFHOB_src_afhob_4_bits_0,
input s2_AFHOB_src_afhob_4_bits_1,
input s2_AFHOB_src_afhob_4_bits_2,
input s2_AFHOB_src_afhob_4_bits_3,
input s2_AFHOB_src_afhob_3_bits_0,
input s2_AFHOB_src_afhob_3_bits_1,
input s2_AFHOB_src_afhob_3_bits_2,
input s2_AFHOB_src_afhob_3_bits_3,
input s2_AFHOB_src_afhob_2_bits_0,
input s2_AFHOB_src_afhob_2_bits_1,
input s2_AFHOB_src_afhob_2_bits_2,
input s2_AFHOB_src_afhob_2_bits_3,
input s2_AFHOB_src_afhob_1_bits_0,
input s2_AFHOB_src_afhob_1_bits_1,
input s2_AFHOB_src_afhob_1_bits_2,
input s2_AFHOB_src_afhob_1_bits_3,
input s2_AFHOB_src_afhob_0_bits_0,
input s2_AFHOB_src_afhob_0_bits_1,
input s2_AFHOB_src_afhob_0_bits_2,
input s2_AFHOB_src_afhob_0_bits_3,
input s1_AFHOB_sel,
input s1_AFHOB_src_afhob_5_bits_0,
input s1_AFHOB_src_afhob_5_bits_1,
input s1_AFHOB_src_afhob_5_bits_2,
input s1_AFHOB_src_afhob_5_bits_3,
input s1_AFHOB_src_afhob_4_bits_0,
input s1_AFHOB_src_afhob_4_bits_1,
input s1_AFHOB_src_afhob_4_bits_2,
input s1_AFHOB_src_afhob_4_bits_3,
input s1_AFHOB_src_afhob_3_bits_0,
input s1_AFHOB_src_afhob_3_bits_1,
input s1_AFHOB_src_afhob_3_bits_2,
input s1_AFHOB_src_afhob_3_bits_3,
input s1_AFHOB_src_afhob_2_bits_0,
input s1_AFHOB_src_afhob_2_bits_1,
input s1_AFHOB_src_afhob_2_bits_2,
input s1_AFHOB_src_afhob_2_bits_3,
input s1_AFHOB_src_afhob_1_bits_0,
input s1_AFHOB_src_afhob_1_bits_1,
input s1_AFHOB_src_afhob_1_bits_2,
input s1_AFHOB_src_afhob_1_bits_3,
input s1_AFHOB_src_afhob_0_bits_0,
input s1_AFHOB_src_afhob_0_bits_1,
input s1_AFHOB_src_afhob_0_bits_2,
input s1_AFHOB_src_afhob_0_bits_3,
input s3_AFHOB_sel,
input s3_AFHOB_src_afhob_5_bits_0,
input s3_AFHOB_src_afhob_5_bits_1,
input s3_AFHOB_src_afhob_5_bits_2,
input s3_AFHOB_src_afhob_5_bits_3,
input s3_AFHOB_src_afhob_4_bits_0,
input s3_AFHOB_src_afhob_4_bits_1,
input s3_AFHOB_src_afhob_4_bits_2,
input s3_AFHOB_src_afhob_4_bits_3,
input s3_AFHOB_src_afhob_3_bits_0,
input s3_AFHOB_src_afhob_3_bits_1,
input s3_AFHOB_src_afhob_3_bits_2,
input s3_AFHOB_src_afhob_3_bits_3,
input s3_AFHOB_src_afhob_2_bits_0,
input s3_AFHOB_src_afhob_2_bits_1,
input s3_AFHOB_src_afhob_2_bits_2,
input s3_AFHOB_src_afhob_2_bits_3,
input s3_AFHOB_src_afhob_1_bits_0,
input s3_AFHOB_src_afhob_1_bits_1,
input s3_AFHOB_src_afhob_1_bits_2,
input s3_AFHOB_src_afhob_1_bits_3,
input s3_AFHOB_src_afhob_0_bits_0,
input s3_AFHOB_src_afhob_0_bits_1,
input s3_AFHOB_src_afhob_0_bits_2,
input s3_AFHOB_src_afhob_0_bits_3,
input redirect_AFHOB_sel,
input redirect_AFHOB_src_afhob_5_bits_0,
input redirect_AFHOB_src_afhob_5_bits_1,
input redirect_AFHOB_src_afhob_5_bits_2,
input redirect_AFHOB_src_afhob_5_bits_3,
input redirect_AFHOB_src_afhob_4_bits_0,
input redirect_AFHOB_src_afhob_4_bits_1,
input redirect_AFHOB_src_afhob_4_bits_2,
input redirect_AFHOB_src_afhob_4_bits_3,
input redirect_AFHOB_src_afhob_3_bits_0,
input redirect_AFHOB_src_afhob_3_bits_1,
input redirect_AFHOB_src_afhob_3_bits_2,
input redirect_AFHOB_src_afhob_3_bits_3,
input redirect_AFHOB_src_afhob_2_bits_0,
input redirect_AFHOB_src_afhob_2_bits_1,
input redirect_AFHOB_src_afhob_2_bits_2,
input redirect_AFHOB_src_afhob_2_bits_3,
input redirect_AFHOB_src_afhob_1_bits_0,
input redirect_AFHOB_src_afhob_1_bits_1,
input redirect_AFHOB_src_afhob_1_bits_2,
input redirect_AFHOB_src_afhob_1_bits_3,
input redirect_AFHOB_src_afhob_0_bits_0,
input redirect_AFHOB_src_afhob_0_bits_1,
input redirect_AFHOB_src_afhob_0_bits_2,
input redirect_AFHOB_src_afhob_0_bits_3,
input stallAFHOB_src_afhob_5_bits_0,
input stallAFHOB_src_afhob_5_bits_1,
input stallAFHOB_src_afhob_5_bits_2,
input stallAFHOB_src_afhob_5_bits_3,
input stallAFHOB_src_afhob_4_bits_0,
input stallAFHOB_src_afhob_4_bits_1,
input stallAFHOB_src_afhob_4_bits_2,
input stallAFHOB_src_afhob_4_bits_3,
input stallAFHOB_src_afhob_3_bits_0,
input stallAFHOB_src_afhob_3_bits_1,
input stallAFHOB_src_afhob_3_bits_2,
input stallAFHOB_src_afhob_3_bits_3,
input stallAFHOB_src_afhob_2_bits_0,
input stallAFHOB_src_afhob_2_bits_1,
input stallAFHOB_src_afhob_2_bits_2,
input stallAFHOB_src_afhob_2_bits_3,
input stallAFHOB_src_afhob_1_bits_0,
input stallAFHOB_src_afhob_1_bits_1,
input stallAFHOB_src_afhob_1_bits_2,
input stallAFHOB_src_afhob_1_bits_3,
input stallAFHOB_src_afhob_0_bits_0,
input stallAFHOB_src_afhob_0_bits_1,
input stallAFHOB_src_afhob_0_bits_2,
input stallAFHOB_src_afhob_0_bits_3,
output out_res_afhob_5_bits_0,
output out_res_afhob_5_bits_1,
output out_res_afhob_5_bits_2,
output out_res_afhob_5_bits_3,
output out_res_afhob_4_bits_0,
output out_res_afhob_4_bits_1,
output out_res_afhob_4_bits_2,
output out_res_afhob_4_bits_3,
output out_res_afhob_3_bits_0,
output out_res_afhob_3_bits_1,
output out_res_afhob_3_bits_2,
output out_res_afhob_3_bits_3,
output out_res_afhob_2_bits_0,
output out_res_afhob_2_bits_1,
output out_res_afhob_2_bits_2,
output out_res_afhob_2_bits_3,
output out_res_afhob_1_bits_0,
output out_res_afhob_1_bits_1,
output out_res_afhob_1_bits_2,
output out_res_afhob_1_bits_3,
output out_res_afhob_0_bits_0,
output out_res_afhob_0_bits_1,
output out_res_afhob_0_bits_2,
output out_res_afhob_0_bits_3
);
assign out_res_afhob_5_bits_0 =
s2_AFHOB_sel
? s2_AFHOB_src_afhob_5_bits_0
: s1_AFHOB_sel
? s1_AFHOB_src_afhob_5_bits_0
: s3_AFHOB_sel
? s3_AFHOB_src_afhob_5_bits_0
: redirect_AFHOB_sel
? redirect_AFHOB_src_afhob_5_bits_0
: stallAFHOB_src_afhob_5_bits_0;
assign out_res_afhob_5_bits_1 =
s2_AFHOB_sel
? s2_AFHOB_src_afhob_5_bits_1
: s1_AFHOB_sel
? s1_AFHOB_src_afhob_5_bits_1
: s3_AFHOB_sel
? s3_AFHOB_src_afhob_5_bits_1
: redirect_AFHOB_sel
? redirect_AFHOB_src_afhob_5_bits_1
: stallAFHOB_src_afhob_5_bits_1;
assign out_res_afhob_5_bits_2 =
s2_AFHOB_sel
? s2_AFHOB_src_afhob_5_bits_2
: s1_AFHOB_sel
? s1_AFHOB_src_afhob_5_bits_2
: s3_AFHOB_sel
? s3_AFHOB_src_afhob_5_bits_2
: redirect_AFHOB_sel
? redirect_AFHOB_src_afhob_5_bits_2
: stallAFHOB_src_afhob_5_bits_2;
assign out_res_afhob_5_bits_3 =
s2_AFHOB_sel
? s2_AFHOB_src_afhob_5_bits_3
: s1_AFHOB_sel
? s1_AFHOB_src_afhob_5_bits_3
: s3_AFHOB_sel
? s3_AFHOB_src_afhob_5_bits_3
: redirect_AFHOB_sel
? redirect_AFHOB_src_afhob_5_bits_3
: stallAFHOB_src_afhob_5_bits_3;
assign out_res_afhob_4_bits_0 =
s2_AFHOB_sel
? s2_AFHOB_src_afhob_4_bits_0
: s1_AFHOB_sel
? s1_AFHOB_src_afhob_4_bits_0
: s3_AFHOB_sel
? s3_AFHOB_src_afhob_4_bits_0
: redirect_AFHOB_sel
? redirect_AFHOB_src_afhob_4_bits_0
: stallAFHOB_src_afhob_4_bits_0;
assign out_res_afhob_4_bits_1 =
s2_AFHOB_sel
? s2_AFHOB_src_afhob_4_bits_1
: s1_AFHOB_sel
? s1_AFHOB_src_afhob_4_bits_1
: s3_AFHOB_sel
? s3_AFHOB_src_afhob_4_bits_1
: redirect_AFHOB_sel
? redirect_AFHOB_src_afhob_4_bits_1
: stallAFHOB_src_afhob_4_bits_1;
assign out_res_afhob_4_bits_2 =
s2_AFHOB_sel
? s2_AFHOB_src_afhob_4_bits_2
: s1_AFHOB_sel
? s1_AFHOB_src_afhob_4_bits_2
: s3_AFHOB_sel
? s3_AFHOB_src_afhob_4_bits_2
: redirect_AFHOB_sel
? redirect_AFHOB_src_afhob_4_bits_2
: stallAFHOB_src_afhob_4_bits_2;
assign out_res_afhob_4_bits_3 =
s2_AFHOB_sel
? s2_AFHOB_src_afhob_4_bits_3
: s1_AFHOB_sel
? s1_AFHOB_src_afhob_4_bits_3
: s3_AFHOB_sel
? s3_AFHOB_src_afhob_4_bits_3
: redirect_AFHOB_sel
? redirect_AFHOB_src_afhob_4_bits_3
: stallAFHOB_src_afhob_4_bits_3;
assign out_res_afhob_3_bits_0 =
s2_AFHOB_sel
? s2_AFHOB_src_afhob_3_bits_0
: s1_AFHOB_sel
? s1_AFHOB_src_afhob_3_bits_0
: s3_AFHOB_sel
? s3_AFHOB_src_afhob_3_bits_0
: redirect_AFHOB_sel
? redirect_AFHOB_src_afhob_3_bits_0
: stallAFHOB_src_afhob_3_bits_0;
assign out_res_afhob_3_bits_1 =
s2_AFHOB_sel
? s2_AFHOB_src_afhob_3_bits_1
: s1_AFHOB_sel
? s1_AFHOB_src_afhob_3_bits_1
: s3_AFHOB_sel
? s3_AFHOB_src_afhob_3_bits_1
: redirect_AFHOB_sel
? redirect_AFHOB_src_afhob_3_bits_1
: stallAFHOB_src_afhob_3_bits_1;
assign out_res_afhob_3_bits_2 =
s2_AFHOB_sel
? s2_AFHOB_src_afhob_3_bits_2
: s1_AFHOB_sel
? s1_AFHOB_src_afhob_3_bits_2
: s3_AFHOB_sel
? s3_AFHOB_src_afhob_3_bits_2
: redirect_AFHOB_sel
? redirect_AFHOB_src_afhob_3_bits_2
: stallAFHOB_src_afhob_3_bits_2;
assign out_res_afhob_3_bits_3 =
s2_AFHOB_sel
? s2_AFHOB_src_afhob_3_bits_3
: s1_AFHOB_sel
? s1_AFHOB_src_afhob_3_bits_3
: s3_AFHOB_sel
? s3_AFHOB_src_afhob_3_bits_3
: redirect_AFHOB_sel
? redirect_AFHOB_src_afhob_3_bits_3
: stallAFHOB_src_afhob_3_bits_3;
assign out_res_afhob_2_bits_0 =
s2_AFHOB_sel
? s2_AFHOB_src_afhob_2_bits_0
: s1_AFHOB_sel
? s1_AFHOB_src_afhob_2_bits_0
: s3_AFHOB_sel
? s3_AFHOB_src_afhob_2_bits_0
: redirect_AFHOB_sel
? redirect_AFHOB_src_afhob_2_bits_0
: stallAFHOB_src_afhob_2_bits_0;
assign out_res_afhob_2_bits_1 =
s2_AFHOB_sel
? s2_AFHOB_src_afhob_2_bits_1
: s1_AFHOB_sel
? s1_AFHOB_src_afhob_2_bits_1
: s3_AFHOB_sel
? s3_AFHOB_src_afhob_2_bits_1
: redirect_AFHOB_sel
? redirect_AFHOB_src_afhob_2_bits_1
: stallAFHOB_src_afhob_2_bits_1;
assign out_res_afhob_2_bits_2 =
s2_AFHOB_sel
? s2_AFHOB_src_afhob_2_bits_2
: s1_AFHOB_sel
? s1_AFHOB_src_afhob_2_bits_2
: s3_AFHOB_sel
? s3_AFHOB_src_afhob_2_bits_2
: redirect_AFHOB_sel
? redirect_AFHOB_src_afhob_2_bits_2
: stallAFHOB_src_afhob_2_bits_2;
assign out_res_afhob_2_bits_3 =
s2_AFHOB_sel
? s2_AFHOB_src_afhob_2_bits_3
: s1_AFHOB_sel
? s1_AFHOB_src_afhob_2_bits_3
: s3_AFHOB_sel
? s3_AFHOB_src_afhob_2_bits_3
: redirect_AFHOB_sel
? redirect_AFHOB_src_afhob_2_bits_3
: stallAFHOB_src_afhob_2_bits_3;
assign out_res_afhob_1_bits_0 =
s2_AFHOB_sel
? s2_AFHOB_src_afhob_1_bits_0
: s1_AFHOB_sel
? s1_AFHOB_src_afhob_1_bits_0
: s3_AFHOB_sel
? s3_AFHOB_src_afhob_1_bits_0
: redirect_AFHOB_sel
? redirect_AFHOB_src_afhob_1_bits_0
: stallAFHOB_src_afhob_1_bits_0;
assign out_res_afhob_1_bits_1 =
s2_AFHOB_sel
? s2_AFHOB_src_afhob_1_bits_1
: s1_AFHOB_sel
? s1_AFHOB_src_afhob_1_bits_1
: s3_AFHOB_sel
? s3_AFHOB_src_afhob_1_bits_1
: redirect_AFHOB_sel
? redirect_AFHOB_src_afhob_1_bits_1
: stallAFHOB_src_afhob_1_bits_1;
assign out_res_afhob_1_bits_2 =
s2_AFHOB_sel
? s2_AFHOB_src_afhob_1_bits_2
: s1_AFHOB_sel
? s1_AFHOB_src_afhob_1_bits_2
: s3_AFHOB_sel
? s3_AFHOB_src_afhob_1_bits_2
: redirect_AFHOB_sel
? redirect_AFHOB_src_afhob_1_bits_2
: stallAFHOB_src_afhob_1_bits_2;
assign out_res_afhob_1_bits_3 =
s2_AFHOB_sel
? s2_AFHOB_src_afhob_1_bits_3
: s1_AFHOB_sel
? s1_AFHOB_src_afhob_1_bits_3
: s3_AFHOB_sel
? s3_AFHOB_src_afhob_1_bits_3
: redirect_AFHOB_sel
? redirect_AFHOB_src_afhob_1_bits_3
: stallAFHOB_src_afhob_1_bits_3;
assign out_res_afhob_0_bits_0 =
s2_AFHOB_sel
? s2_AFHOB_src_afhob_0_bits_0
: s1_AFHOB_sel
? s1_AFHOB_src_afhob_0_bits_0
: s3_AFHOB_sel
? s3_AFHOB_src_afhob_0_bits_0
: redirect_AFHOB_sel
? redirect_AFHOB_src_afhob_0_bits_0
: stallAFHOB_src_afhob_0_bits_0;
assign out_res_afhob_0_bits_1 =
s2_AFHOB_sel
? s2_AFHOB_src_afhob_0_bits_1
: s1_AFHOB_sel
? s1_AFHOB_src_afhob_0_bits_1
: s3_AFHOB_sel
? s3_AFHOB_src_afhob_0_bits_1
: redirect_AFHOB_sel
? redirect_AFHOB_src_afhob_0_bits_1
: stallAFHOB_src_afhob_0_bits_1;
assign out_res_afhob_0_bits_2 =
s2_AFHOB_sel
? s2_AFHOB_src_afhob_0_bits_2
: s1_AFHOB_sel
? s1_AFHOB_src_afhob_0_bits_2
: s3_AFHOB_sel
? s3_AFHOB_src_afhob_0_bits_2
: redirect_AFHOB_sel
? redirect_AFHOB_src_afhob_0_bits_2
: stallAFHOB_src_afhob_0_bits_2;
assign out_res_afhob_0_bits_3 =
s2_AFHOB_sel
? s2_AFHOB_src_afhob_0_bits_3
: s1_AFHOB_sel
? s1_AFHOB_src_afhob_0_bits_3
: s3_AFHOB_sel
? s3_AFHOB_src_afhob_0_bits_3
: redirect_AFHOB_sel
? redirect_AFHOB_src_afhob_0_bits_3
: stallAFHOB_src_afhob_0_bits_3;
endmodule

80
rtl/BPUTop/PriorityMuxModule_16.sv
View File

@ -1,80 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module PriorityMuxModule_16(
input s2_BrNumOH_sel,
input [2:0] s2_BrNumOH_src,
input s1_BrNumOH_sel,
input [2:0] s1_BrNumOH_src,
input s3_BrNumOH_sel,
input [2:0] s3_BrNumOH_src,
input redirect_BrNumOH_sel,
input [2:0] redirect_BrNumOH_src,
input [2:0] stallBrNumOH_src,
output [2:0] out_res
);
assign out_res =
s2_BrNumOH_sel
? s2_BrNumOH_src
: s1_BrNumOH_sel
? s1_BrNumOH_src
: s3_BrNumOH_sel
? s3_BrNumOH_src
: redirect_BrNumOH_sel ? redirect_BrNumOH_src : stallBrNumOH_src;
endmodule

76
rtl/BPUTop/PriorityMuxModule_20.sv
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@ -1,76 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module PriorityMuxModule_20(
input s2_new_bit_0_sel,
input s2_new_bit_0_src,
input s1_new_bit_0_sel,
input s1_new_bit_0_src,
input s3_new_bit_0_sel,
input s3_new_bit_0_src,
input redirect_new_bit_0_src,
output out_res
);
assign out_res =
s2_new_bit_0_sel
? s2_new_bit_0_src
: s1_new_bit_0_sel
? s1_new_bit_0_src
: s3_new_bit_0_sel ? s3_new_bit_0_src : redirect_new_bit_0_src;
endmodule

354
rtl/BPUTop/PriorityMuxModule_4.sv
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@ -1,354 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module PriorityMuxModule_4(
input s2_FGH_sel,
input [10:0] s2_FGH_src_hist_17_folded_hist,
input [10:0] s2_FGH_src_hist_16_folded_hist,
input [6:0] s2_FGH_src_hist_15_folded_hist,
input [7:0] s2_FGH_src_hist_14_folded_hist,
input [8:0] s2_FGH_src_hist_13_folded_hist,
input [3:0] s2_FGH_src_hist_12_folded_hist,
input [7:0] s2_FGH_src_hist_11_folded_hist,
input [8:0] s2_FGH_src_hist_10_folded_hist,
input [6:0] s2_FGH_src_hist_9_folded_hist,
input [7:0] s2_FGH_src_hist_8_folded_hist,
input [6:0] s2_FGH_src_hist_7_folded_hist,
input [8:0] s2_FGH_src_hist_6_folded_hist,
input [6:0] s2_FGH_src_hist_5_folded_hist,
input [7:0] s2_FGH_src_hist_4_folded_hist,
input [7:0] s2_FGH_src_hist_3_folded_hist,
input [7:0] s2_FGH_src_hist_2_folded_hist,
input [10:0] s2_FGH_src_hist_1_folded_hist,
input [7:0] s2_FGH_src_hist_0_folded_hist,
input s1_FGH_sel,
input [10:0] s1_FGH_src_hist_17_folded_hist,
input [10:0] s1_FGH_src_hist_16_folded_hist,
input [6:0] s1_FGH_src_hist_15_folded_hist,
input [7:0] s1_FGH_src_hist_14_folded_hist,
input [8:0] s1_FGH_src_hist_13_folded_hist,
input [3:0] s1_FGH_src_hist_12_folded_hist,
input [7:0] s1_FGH_src_hist_11_folded_hist,
input [8:0] s1_FGH_src_hist_10_folded_hist,
input [6:0] s1_FGH_src_hist_9_folded_hist,
input [7:0] s1_FGH_src_hist_8_folded_hist,
input [6:0] s1_FGH_src_hist_7_folded_hist,
input [8:0] s1_FGH_src_hist_6_folded_hist,
input [6:0] s1_FGH_src_hist_5_folded_hist,
input [7:0] s1_FGH_src_hist_4_folded_hist,
input [7:0] s1_FGH_src_hist_3_folded_hist,
input [7:0] s1_FGH_src_hist_2_folded_hist,
input [10:0] s1_FGH_src_hist_1_folded_hist,
input [7:0] s1_FGH_src_hist_0_folded_hist,
input s3_FGH_sel,
input [10:0] s3_FGH_src_hist_17_folded_hist,
input [10:0] s3_FGH_src_hist_16_folded_hist,
input [6:0] s3_FGH_src_hist_15_folded_hist,
input [7:0] s3_FGH_src_hist_14_folded_hist,
input [8:0] s3_FGH_src_hist_13_folded_hist,
input [3:0] s3_FGH_src_hist_12_folded_hist,
input [7:0] s3_FGH_src_hist_11_folded_hist,
input [8:0] s3_FGH_src_hist_10_folded_hist,
input [6:0] s3_FGH_src_hist_9_folded_hist,
input [7:0] s3_FGH_src_hist_8_folded_hist,
input [6:0] s3_FGH_src_hist_7_folded_hist,
input [8:0] s3_FGH_src_hist_6_folded_hist,
input [6:0] s3_FGH_src_hist_5_folded_hist,
input [7:0] s3_FGH_src_hist_4_folded_hist,
input [7:0] s3_FGH_src_hist_3_folded_hist,
input [7:0] s3_FGH_src_hist_2_folded_hist,
input [10:0] s3_FGH_src_hist_1_folded_hist,
input [7:0] s3_FGH_src_hist_0_folded_hist,
input redirect_FGHT_sel,
input [10:0] redirect_FGHT_src_hist_17_folded_hist,
input [10:0] redirect_FGHT_src_hist_16_folded_hist,
input [6:0] redirect_FGHT_src_hist_15_folded_hist,
input [7:0] redirect_FGHT_src_hist_14_folded_hist,
input [8:0] redirect_FGHT_src_hist_13_folded_hist,
input [3:0] redirect_FGHT_src_hist_12_folded_hist,
input [7:0] redirect_FGHT_src_hist_11_folded_hist,
input [8:0] redirect_FGHT_src_hist_10_folded_hist,
input [6:0] redirect_FGHT_src_hist_9_folded_hist,
input [7:0] redirect_FGHT_src_hist_8_folded_hist,
input [6:0] redirect_FGHT_src_hist_7_folded_hist,
input [8:0] redirect_FGHT_src_hist_6_folded_hist,
input [6:0] redirect_FGHT_src_hist_5_folded_hist,
input [7:0] redirect_FGHT_src_hist_4_folded_hist,
input [7:0] redirect_FGHT_src_hist_3_folded_hist,
input [7:0] redirect_FGHT_src_hist_2_folded_hist,
input [10:0] redirect_FGHT_src_hist_1_folded_hist,
input [7:0] redirect_FGHT_src_hist_0_folded_hist,
input [10:0] stallFGH_src_hist_17_folded_hist,
input [10:0] stallFGH_src_hist_16_folded_hist,
input [6:0] stallFGH_src_hist_15_folded_hist,
input [7:0] stallFGH_src_hist_14_folded_hist,
input [8:0] stallFGH_src_hist_13_folded_hist,
input [3:0] stallFGH_src_hist_12_folded_hist,
input [7:0] stallFGH_src_hist_11_folded_hist,
input [8:0] stallFGH_src_hist_10_folded_hist,
input [6:0] stallFGH_src_hist_9_folded_hist,
input [7:0] stallFGH_src_hist_8_folded_hist,
input [6:0] stallFGH_src_hist_7_folded_hist,
input [8:0] stallFGH_src_hist_6_folded_hist,
input [6:0] stallFGH_src_hist_5_folded_hist,
input [7:0] stallFGH_src_hist_4_folded_hist,
input [7:0] stallFGH_src_hist_3_folded_hist,
input [7:0] stallFGH_src_hist_2_folded_hist,
input [10:0] stallFGH_src_hist_1_folded_hist,
input [7:0] stallFGH_src_hist_0_folded_hist,
output [10:0] out_res_hist_17_folded_hist,
output [10:0] out_res_hist_16_folded_hist,
output [6:0] out_res_hist_15_folded_hist,
output [7:0] out_res_hist_14_folded_hist,
output [8:0] out_res_hist_13_folded_hist,
output [3:0] out_res_hist_12_folded_hist,
output [7:0] out_res_hist_11_folded_hist,
output [8:0] out_res_hist_10_folded_hist,
output [6:0] out_res_hist_9_folded_hist,
output [7:0] out_res_hist_8_folded_hist,
output [6:0] out_res_hist_7_folded_hist,
output [8:0] out_res_hist_6_folded_hist,
output [6:0] out_res_hist_5_folded_hist,
output [7:0] out_res_hist_4_folded_hist,
output [7:0] out_res_hist_3_folded_hist,
output [7:0] out_res_hist_2_folded_hist,
output [10:0] out_res_hist_1_folded_hist,
output [7:0] out_res_hist_0_folded_hist
);
assign out_res_hist_17_folded_hist =
s2_FGH_sel
? s2_FGH_src_hist_17_folded_hist
: s1_FGH_sel
? s1_FGH_src_hist_17_folded_hist
: s3_FGH_sel
? s3_FGH_src_hist_17_folded_hist
: redirect_FGHT_sel
? redirect_FGHT_src_hist_17_folded_hist
: stallFGH_src_hist_17_folded_hist;
assign out_res_hist_16_folded_hist =
s2_FGH_sel
? s2_FGH_src_hist_16_folded_hist
: s1_FGH_sel
? s1_FGH_src_hist_16_folded_hist
: s3_FGH_sel
? s3_FGH_src_hist_16_folded_hist
: redirect_FGHT_sel
? redirect_FGHT_src_hist_16_folded_hist
: stallFGH_src_hist_16_folded_hist;
assign out_res_hist_15_folded_hist =
s2_FGH_sel
? s2_FGH_src_hist_15_folded_hist
: s1_FGH_sel
? s1_FGH_src_hist_15_folded_hist
: s3_FGH_sel
? s3_FGH_src_hist_15_folded_hist
: redirect_FGHT_sel
? redirect_FGHT_src_hist_15_folded_hist
: stallFGH_src_hist_15_folded_hist;
assign out_res_hist_14_folded_hist =
s2_FGH_sel
? s2_FGH_src_hist_14_folded_hist
: s1_FGH_sel
? s1_FGH_src_hist_14_folded_hist
: s3_FGH_sel
? s3_FGH_src_hist_14_folded_hist
: redirect_FGHT_sel
? redirect_FGHT_src_hist_14_folded_hist
: stallFGH_src_hist_14_folded_hist;
assign out_res_hist_13_folded_hist =
s2_FGH_sel
? s2_FGH_src_hist_13_folded_hist
: s1_FGH_sel
? s1_FGH_src_hist_13_folded_hist
: s3_FGH_sel
? s3_FGH_src_hist_13_folded_hist
: redirect_FGHT_sel
? redirect_FGHT_src_hist_13_folded_hist
: stallFGH_src_hist_13_folded_hist;
assign out_res_hist_12_folded_hist =
s2_FGH_sel
? s2_FGH_src_hist_12_folded_hist
: s1_FGH_sel
? s1_FGH_src_hist_12_folded_hist
: s3_FGH_sel
? s3_FGH_src_hist_12_folded_hist
: redirect_FGHT_sel
? redirect_FGHT_src_hist_12_folded_hist
: stallFGH_src_hist_12_folded_hist;
assign out_res_hist_11_folded_hist =
s2_FGH_sel
? s2_FGH_src_hist_11_folded_hist
: s1_FGH_sel
? s1_FGH_src_hist_11_folded_hist
: s3_FGH_sel
? s3_FGH_src_hist_11_folded_hist
: redirect_FGHT_sel
? redirect_FGHT_src_hist_11_folded_hist
: stallFGH_src_hist_11_folded_hist;
assign out_res_hist_10_folded_hist =
s2_FGH_sel
? s2_FGH_src_hist_10_folded_hist
: s1_FGH_sel
? s1_FGH_src_hist_10_folded_hist
: s3_FGH_sel
? s3_FGH_src_hist_10_folded_hist
: redirect_FGHT_sel
? redirect_FGHT_src_hist_10_folded_hist
: stallFGH_src_hist_10_folded_hist;
assign out_res_hist_9_folded_hist =
s2_FGH_sel
? s2_FGH_src_hist_9_folded_hist
: s1_FGH_sel
? s1_FGH_src_hist_9_folded_hist
: s3_FGH_sel
? s3_FGH_src_hist_9_folded_hist
: redirect_FGHT_sel
? redirect_FGHT_src_hist_9_folded_hist
: stallFGH_src_hist_9_folded_hist;
assign out_res_hist_8_folded_hist =
s2_FGH_sel
? s2_FGH_src_hist_8_folded_hist
: s1_FGH_sel
? s1_FGH_src_hist_8_folded_hist
: s3_FGH_sel
? s3_FGH_src_hist_8_folded_hist
: redirect_FGHT_sel
? redirect_FGHT_src_hist_8_folded_hist
: stallFGH_src_hist_8_folded_hist;
assign out_res_hist_7_folded_hist =
s2_FGH_sel
? s2_FGH_src_hist_7_folded_hist
: s1_FGH_sel
? s1_FGH_src_hist_7_folded_hist
: s3_FGH_sel
? s3_FGH_src_hist_7_folded_hist
: redirect_FGHT_sel
? redirect_FGHT_src_hist_7_folded_hist
: stallFGH_src_hist_7_folded_hist;
assign out_res_hist_6_folded_hist =
s2_FGH_sel
? s2_FGH_src_hist_6_folded_hist
: s1_FGH_sel
? s1_FGH_src_hist_6_folded_hist
: s3_FGH_sel
? s3_FGH_src_hist_6_folded_hist
: redirect_FGHT_sel
? redirect_FGHT_src_hist_6_folded_hist
: stallFGH_src_hist_6_folded_hist;
assign out_res_hist_5_folded_hist =
s2_FGH_sel
? s2_FGH_src_hist_5_folded_hist
: s1_FGH_sel
? s1_FGH_src_hist_5_folded_hist
: s3_FGH_sel
? s3_FGH_src_hist_5_folded_hist
: redirect_FGHT_sel
? redirect_FGHT_src_hist_5_folded_hist
: stallFGH_src_hist_5_folded_hist;
assign out_res_hist_4_folded_hist =
s2_FGH_sel
? s2_FGH_src_hist_4_folded_hist
: s1_FGH_sel
? s1_FGH_src_hist_4_folded_hist
: s3_FGH_sel
? s3_FGH_src_hist_4_folded_hist
: redirect_FGHT_sel
? redirect_FGHT_src_hist_4_folded_hist
: stallFGH_src_hist_4_folded_hist;
assign out_res_hist_3_folded_hist =
s2_FGH_sel
? s2_FGH_src_hist_3_folded_hist
: s1_FGH_sel
? s1_FGH_src_hist_3_folded_hist
: s3_FGH_sel
? s3_FGH_src_hist_3_folded_hist
: redirect_FGHT_sel
? redirect_FGHT_src_hist_3_folded_hist
: stallFGH_src_hist_3_folded_hist;
assign out_res_hist_2_folded_hist =
s2_FGH_sel
? s2_FGH_src_hist_2_folded_hist
: s1_FGH_sel
? s1_FGH_src_hist_2_folded_hist
: s3_FGH_sel
? s3_FGH_src_hist_2_folded_hist
: redirect_FGHT_sel
? redirect_FGHT_src_hist_2_folded_hist
: stallFGH_src_hist_2_folded_hist;
assign out_res_hist_1_folded_hist =
s2_FGH_sel
? s2_FGH_src_hist_1_folded_hist
: s1_FGH_sel
? s1_FGH_src_hist_1_folded_hist
: s3_FGH_sel
? s3_FGH_src_hist_1_folded_hist
: redirect_FGHT_sel
? redirect_FGHT_src_hist_1_folded_hist
: stallFGH_src_hist_1_folded_hist;
assign out_res_hist_0_folded_hist =
s2_FGH_sel
? s2_FGH_src_hist_0_folded_hist
: s1_FGH_sel
? s1_FGH_src_hist_0_folded_hist
: s3_FGH_sel
? s3_FGH_src_hist_0_folded_hist
: redirect_FGHT_sel
? redirect_FGHT_src_hist_0_folded_hist
: stallFGH_src_hist_0_folded_hist;
endmodule

94
rtl/BPUTop/PriorityMuxModule_8.sv
View File

@ -1,94 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module PriorityMuxModule_8(
input s2_GHPtr_sel,
input s2_GHPtr_src_flag,
input [7:0] s2_GHPtr_src_value,
input s1_GHPtr_sel,
input s1_GHPtr_src_flag,
input [7:0] s1_GHPtr_src_value,
input s3_GHPtr_sel,
input s3_GHPtr_src_flag,
input [7:0] s3_GHPtr_src_value,
input redirect_GHPtr_sel,
input redirect_GHPtr_src_flag,
input [7:0] redirect_GHPtr_src_value,
input stallGHPtr_src_flag,
input [7:0] stallGHPtr_src_value,
output out_res_flag,
output [7:0] out_res_value
);
assign out_res_flag =
s2_GHPtr_sel
? s2_GHPtr_src_flag
: s1_GHPtr_sel
? s1_GHPtr_src_flag
: s3_GHPtr_sel
? s3_GHPtr_src_flag
: redirect_GHPtr_sel ? redirect_GHPtr_src_flag : stallGHPtr_src_flag;
assign out_res_value =
s2_GHPtr_sel
? s2_GHPtr_src_value
: s1_GHPtr_sel
? s1_GHPtr_src_value
: s3_GHPtr_sel
? s3_GHPtr_src_value
: redirect_GHPtr_sel ? redirect_GHPtr_src_value : stallGHPtr_src_value;
endmodule

883
rtl/BPUTop/RAS.sv
View File

@ -1,883 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module RAS(
input clock,
input reset,
input [35:0] io_reset_vector,
input [40:0] io_in_bits_s0_pc_0,
input [40:0] io_in_bits_s0_pc_1,
input [40:0] io_in_bits_s0_pc_2,
input [40:0] io_in_bits_s0_pc_3,
input io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0,
input io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1,
input io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_0,
input io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_1,
input [40:0] io_in_bits_resp_in_0_s2_full_pred_0_targets_0,
input [40:0] io_in_bits_resp_in_0_s2_full_pred_0_targets_1,
input [40:0] io_in_bits_resp_in_0_s2_full_pred_0_jalr_target,
input [3:0] io_in_bits_resp_in_0_s2_full_pred_0_offsets_0,
input [3:0] io_in_bits_resp_in_0_s2_full_pred_0_offsets_1,
input [40:0] io_in_bits_resp_in_0_s2_full_pred_0_fallThroughAddr,
input io_in_bits_resp_in_0_s2_full_pred_0_is_br_sharing,
input io_in_bits_resp_in_0_s2_full_pred_0_hit,
input io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0,
input io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1,
input io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_0,
input io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_1,
input [40:0] io_in_bits_resp_in_0_s2_full_pred_1_targets_0,
input [40:0] io_in_bits_resp_in_0_s2_full_pred_1_targets_1,
input [40:0] io_in_bits_resp_in_0_s2_full_pred_1_jalr_target,
input [3:0] io_in_bits_resp_in_0_s2_full_pred_1_offsets_0,
input [3:0] io_in_bits_resp_in_0_s2_full_pred_1_offsets_1,
input [40:0] io_in_bits_resp_in_0_s2_full_pred_1_fallThroughAddr,
input io_in_bits_resp_in_0_s2_full_pred_1_is_br_sharing,
input io_in_bits_resp_in_0_s2_full_pred_1_hit,
input io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0,
input io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1,
input io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_0,
input io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1,
input [40:0] io_in_bits_resp_in_0_s2_full_pred_2_targets_0,
input [40:0] io_in_bits_resp_in_0_s2_full_pred_2_targets_1,
input [40:0] io_in_bits_resp_in_0_s2_full_pred_2_jalr_target,
input [3:0] io_in_bits_resp_in_0_s2_full_pred_2_offsets_0,
input [3:0] io_in_bits_resp_in_0_s2_full_pred_2_offsets_1,
input [40:0] io_in_bits_resp_in_0_s2_full_pred_2_fallThroughAddr,
input io_in_bits_resp_in_0_s2_full_pred_2_is_jalr,
input io_in_bits_resp_in_0_s2_full_pred_2_is_call,
input io_in_bits_resp_in_0_s2_full_pred_2_is_ret,
input io_in_bits_resp_in_0_s2_full_pred_2_last_may_be_rvi_call,
input io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing,
input io_in_bits_resp_in_0_s2_full_pred_2_hit,
input io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0,
input io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1,
input io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_0,
input io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_1,
input [40:0] io_in_bits_resp_in_0_s2_full_pred_3_targets_0,
input [40:0] io_in_bits_resp_in_0_s2_full_pred_3_targets_1,
input [40:0] io_in_bits_resp_in_0_s2_full_pred_3_jalr_target,
input [3:0] io_in_bits_resp_in_0_s2_full_pred_3_offsets_0,
input [3:0] io_in_bits_resp_in_0_s2_full_pred_3_offsets_1,
input [40:0] io_in_bits_resp_in_0_s2_full_pred_3_fallThroughAddr,
input io_in_bits_resp_in_0_s2_full_pred_3_fallThroughErr,
input io_in_bits_resp_in_0_s2_full_pred_3_is_br_sharing,
input io_in_bits_resp_in_0_s2_full_pred_3_hit,
input io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0,
input io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1,
input io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_0,
input io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_1,
input [40:0] io_in_bits_resp_in_0_s3_full_pred_0_targets_0,
input [40:0] io_in_bits_resp_in_0_s3_full_pred_0_targets_1,
input [40:0] io_in_bits_resp_in_0_s3_full_pred_0_jalr_target,
input [40:0] io_in_bits_resp_in_0_s3_full_pred_0_fallThroughAddr,
input io_in_bits_resp_in_0_s3_full_pred_0_fallThroughErr,
input io_in_bits_resp_in_0_s3_full_pred_0_is_br_sharing,
input io_in_bits_resp_in_0_s3_full_pred_0_hit,
input io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0,
input io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1,
input io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_0,
input io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_1,
input [40:0] io_in_bits_resp_in_0_s3_full_pred_1_targets_0,
input [40:0] io_in_bits_resp_in_0_s3_full_pred_1_targets_1,
input [40:0] io_in_bits_resp_in_0_s3_full_pred_1_jalr_target,
input [40:0] io_in_bits_resp_in_0_s3_full_pred_1_fallThroughAddr,
input io_in_bits_resp_in_0_s3_full_pred_1_fallThroughErr,
input io_in_bits_resp_in_0_s3_full_pred_1_is_br_sharing,
input io_in_bits_resp_in_0_s3_full_pred_1_hit,
input io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0,
input io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1,
input io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_0,
input io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1,
input [40:0] io_in_bits_resp_in_0_s3_full_pred_2_targets_0,
input [40:0] io_in_bits_resp_in_0_s3_full_pred_2_targets_1,
input [40:0] io_in_bits_resp_in_0_s3_full_pred_2_jalr_target,
input [40:0] io_in_bits_resp_in_0_s3_full_pred_2_fallThroughAddr,
input io_in_bits_resp_in_0_s3_full_pred_2_fallThroughErr,
input io_in_bits_resp_in_0_s3_full_pred_2_is_jalr,
input io_in_bits_resp_in_0_s3_full_pred_2_is_call,
input io_in_bits_resp_in_0_s3_full_pred_2_is_ret,
input io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing,
input io_in_bits_resp_in_0_s3_full_pred_2_hit,
input io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0,
input io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1,
input io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_0,
input io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_1,
input [40:0] io_in_bits_resp_in_0_s3_full_pred_3_targets_0,
input [40:0] io_in_bits_resp_in_0_s3_full_pred_3_targets_1,
input [40:0] io_in_bits_resp_in_0_s3_full_pred_3_jalr_target,
input [3:0] io_in_bits_resp_in_0_s3_full_pred_3_offsets_0,
input [3:0] io_in_bits_resp_in_0_s3_full_pred_3_offsets_1,
input [40:0] io_in_bits_resp_in_0_s3_full_pred_3_fallThroughAddr,
input io_in_bits_resp_in_0_s3_full_pred_3_fallThroughErr,
input io_in_bits_resp_in_0_s3_full_pred_3_is_br_sharing,
input io_in_bits_resp_in_0_s3_full_pred_3_hit,
input io_in_bits_resp_in_0_last_stage_ftb_entry_valid,
input [3:0] io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_offset,
input [11:0] io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_lower,
input [1:0] io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_tarStat,
input io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_sharing,
input io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_valid,
input [3:0] io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_offset,
input [19:0] io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_lower,
input [1:0] io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_tarStat,
input io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_sharing,
input io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_valid,
input [3:0] io_in_bits_resp_in_0_last_stage_ftb_entry_pftAddr,
input io_in_bits_resp_in_0_last_stage_ftb_entry_carry,
input io_in_bits_resp_in_0_last_stage_ftb_entry_isCall,
input io_in_bits_resp_in_0_last_stage_ftb_entry_isRet,
input io_in_bits_resp_in_0_last_stage_ftb_entry_isJalr,
input io_in_bits_resp_in_0_last_stage_ftb_entry_last_may_be_rvi_call,
input io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_0,
input io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_1,
output [40:0] io_out_s2_pc_0,
output [40:0] io_out_s2_pc_1,
output [40:0] io_out_s2_pc_2,
output [40:0] io_out_s2_pc_3,
output io_out_s2_full_pred_0_br_taken_mask_0,
output io_out_s2_full_pred_0_br_taken_mask_1,
output io_out_s2_full_pred_0_slot_valids_0,
output io_out_s2_full_pred_0_slot_valids_1,
output [40:0] io_out_s2_full_pred_0_targets_0,
output [40:0] io_out_s2_full_pred_0_targets_1,
output [3:0] io_out_s2_full_pred_0_offsets_0,
output [3:0] io_out_s2_full_pred_0_offsets_1,
output [40:0] io_out_s2_full_pred_0_fallThroughAddr,
output io_out_s2_full_pred_0_is_br_sharing,
output io_out_s2_full_pred_0_hit,
output io_out_s2_full_pred_1_br_taken_mask_0,
output io_out_s2_full_pred_1_br_taken_mask_1,
output io_out_s2_full_pred_1_slot_valids_0,
output io_out_s2_full_pred_1_slot_valids_1,
output [40:0] io_out_s2_full_pred_1_targets_0,
output [40:0] io_out_s2_full_pred_1_targets_1,
output [3:0] io_out_s2_full_pred_1_offsets_0,
output [3:0] io_out_s2_full_pred_1_offsets_1,
output [40:0] io_out_s2_full_pred_1_fallThroughAddr,
output io_out_s2_full_pred_1_is_br_sharing,
output io_out_s2_full_pred_1_hit,
output io_out_s2_full_pred_2_br_taken_mask_0,
output io_out_s2_full_pred_2_br_taken_mask_1,
output io_out_s2_full_pred_2_slot_valids_0,
output io_out_s2_full_pred_2_slot_valids_1,
output [40:0] io_out_s2_full_pred_2_targets_0,
output [40:0] io_out_s2_full_pred_2_targets_1,
output [3:0] io_out_s2_full_pred_2_offsets_0,
output [3:0] io_out_s2_full_pred_2_offsets_1,
output [40:0] io_out_s2_full_pred_2_fallThroughAddr,
output io_out_s2_full_pred_2_is_br_sharing,
output io_out_s2_full_pred_2_hit,
output io_out_s2_full_pred_3_br_taken_mask_0,
output io_out_s2_full_pred_3_br_taken_mask_1,
output io_out_s2_full_pred_3_slot_valids_0,
output io_out_s2_full_pred_3_slot_valids_1,
output [40:0] io_out_s2_full_pred_3_targets_0,
output [40:0] io_out_s2_full_pred_3_targets_1,
output [3:0] io_out_s2_full_pred_3_offsets_0,
output [3:0] io_out_s2_full_pred_3_offsets_1,
output [40:0] io_out_s2_full_pred_3_fallThroughAddr,
output io_out_s2_full_pred_3_fallThroughErr,
output io_out_s2_full_pred_3_is_br_sharing,
output io_out_s2_full_pred_3_hit,
output [40:0] io_out_s3_pc_0,
output [40:0] io_out_s3_pc_1,
output [40:0] io_out_s3_pc_2,
output [40:0] io_out_s3_pc_3,
output io_out_s3_full_pred_0_br_taken_mask_0,
output io_out_s3_full_pred_0_br_taken_mask_1,
output io_out_s3_full_pred_0_slot_valids_0,
output io_out_s3_full_pred_0_slot_valids_1,
output [40:0] io_out_s3_full_pred_0_targets_0,
output [40:0] io_out_s3_full_pred_0_targets_1,
output [40:0] io_out_s3_full_pred_0_fallThroughAddr,
output io_out_s3_full_pred_0_fallThroughErr,
output io_out_s3_full_pred_0_is_br_sharing,
output io_out_s3_full_pred_0_hit,
output io_out_s3_full_pred_1_br_taken_mask_0,
output io_out_s3_full_pred_1_br_taken_mask_1,
output io_out_s3_full_pred_1_slot_valids_0,
output io_out_s3_full_pred_1_slot_valids_1,
output [40:0] io_out_s3_full_pred_1_targets_0,
output [40:0] io_out_s3_full_pred_1_targets_1,
output [40:0] io_out_s3_full_pred_1_fallThroughAddr,
output io_out_s3_full_pred_1_fallThroughErr,
output io_out_s3_full_pred_1_is_br_sharing,
output io_out_s3_full_pred_1_hit,
output io_out_s3_full_pred_2_br_taken_mask_0,
output io_out_s3_full_pred_2_br_taken_mask_1,
output io_out_s3_full_pred_2_slot_valids_0,
output io_out_s3_full_pred_2_slot_valids_1,
output [40:0] io_out_s3_full_pred_2_targets_0,
output [40:0] io_out_s3_full_pred_2_targets_1,
output [40:0] io_out_s3_full_pred_2_fallThroughAddr,
output io_out_s3_full_pred_2_fallThroughErr,
output io_out_s3_full_pred_2_is_br_sharing,
output io_out_s3_full_pred_2_hit,
output io_out_s3_full_pred_3_br_taken_mask_0,
output io_out_s3_full_pred_3_br_taken_mask_1,
output io_out_s3_full_pred_3_slot_valids_0,
output io_out_s3_full_pred_3_slot_valids_1,
output [40:0] io_out_s3_full_pred_3_targets_0,
output [40:0] io_out_s3_full_pred_3_targets_1,
output [3:0] io_out_s3_full_pred_3_offsets_0,
output [3:0] io_out_s3_full_pred_3_offsets_1,
output [40:0] io_out_s3_full_pred_3_fallThroughAddr,
output io_out_s3_full_pred_3_fallThroughErr,
output io_out_s3_full_pred_3_is_br_sharing,
output io_out_s3_full_pred_3_hit,
output [222:0] io_out_last_stage_meta,
output [3:0] io_out_last_stage_spec_info_ssp,
output [1:0] io_out_last_stage_spec_info_sctr,
output io_out_last_stage_spec_info_TOSW_flag,
output [4:0] io_out_last_stage_spec_info_TOSW_value,
output io_out_last_stage_spec_info_TOSR_flag,
output [4:0] io_out_last_stage_spec_info_TOSR_value,
output io_out_last_stage_spec_info_NOS_flag,
output [4:0] io_out_last_stage_spec_info_NOS_value,
output [40:0] io_out_last_stage_spec_info_topAddr,
output io_out_last_stage_ftb_entry_valid,
output [3:0] io_out_last_stage_ftb_entry_brSlots_0_offset,
output [11:0] io_out_last_stage_ftb_entry_brSlots_0_lower,
output [1:0] io_out_last_stage_ftb_entry_brSlots_0_tarStat,
output io_out_last_stage_ftb_entry_brSlots_0_sharing,
output io_out_last_stage_ftb_entry_brSlots_0_valid,
output [3:0] io_out_last_stage_ftb_entry_tailSlot_offset,
output [19:0] io_out_last_stage_ftb_entry_tailSlot_lower,
output [1:0] io_out_last_stage_ftb_entry_tailSlot_tarStat,
output io_out_last_stage_ftb_entry_tailSlot_sharing,
output io_out_last_stage_ftb_entry_tailSlot_valid,
output [3:0] io_out_last_stage_ftb_entry_pftAddr,
output io_out_last_stage_ftb_entry_carry,
output io_out_last_stage_ftb_entry_isCall,
output io_out_last_stage_ftb_entry_isRet,
output io_out_last_stage_ftb_entry_isJalr,
output io_out_last_stage_ftb_entry_last_may_be_rvi_call,
output io_out_last_stage_ftb_entry_always_taken_0,
output io_out_last_stage_ftb_entry_always_taken_1,
input io_ctrl_ras_enable,
input io_s0_fire_0,
input io_s0_fire_1,
input io_s0_fire_2,
input io_s0_fire_3,
input io_s1_fire_0,
input io_s1_fire_1,
input io_s1_fire_2,
input io_s1_fire_3,
input io_s2_fire_0,
input io_s2_fire_1,
input io_s2_fire_2,
input io_s2_fire_3,
input io_s3_fire_2,
input io_s3_redirect_2,
input io_update_valid,
input [3:0] io_update_bits_ftb_entry_tailSlot_offset,
input io_update_bits_ftb_entry_tailSlot_valid,
input io_update_bits_ftb_entry_isCall,
input io_update_bits_ftb_entry_isRet,
input io_update_bits_cfi_idx_valid,
input [3:0] io_update_bits_cfi_idx_bits,
input io_update_bits_jmp_taken,
input [222:0] io_update_bits_meta,
input io_redirect_valid,
input io_redirect_bits_level,
input [40:0] io_redirect_bits_cfiUpdate_pc,
input io_redirect_bits_cfiUpdate_pd_isRVC,
input io_redirect_bits_cfiUpdate_pd_isCall,
input io_redirect_bits_cfiUpdate_pd_isRet,
input [3:0] io_redirect_bits_cfiUpdate_ssp,
input [1:0] io_redirect_bits_cfiUpdate_sctr,
input io_redirect_bits_cfiUpdate_TOSW_flag,
input [4:0] io_redirect_bits_cfiUpdate_TOSW_value,
input io_redirect_bits_cfiUpdate_TOSR_flag,
input [4:0] io_redirect_bits_cfiUpdate_TOSR_value,
input io_redirect_bits_cfiUpdate_NOS_flag,
input [4:0] io_redirect_bits_cfiUpdate_NOS_value
);
wire [40:0] _RASStack_io_spec_pop_addr;
wire [3:0] _RASStack_io_ssp;
wire [2:0] _RASStack_io_sctr;
wire _RASStack_io_TOSR_flag;
wire [4:0] _RASStack_io_TOSR_value;
wire _RASStack_io_TOSW_flag;
wire [4:0] _RASStack_io_TOSW_value;
wire _RASStack_io_NOS_flag;
wire [4:0] _RASStack_io_NOS_value;
wire [35:0] _reset_vector_delay_io_out;
reg [40:0] s1_pc_dup_0;
reg [40:0] s1_pc_dup_1;
reg [40:0] s1_pc_dup_2;
reg [40:0] s1_pc_dup_3;
reg [40:0] s2_pc_dup_0;
reg [40:0] s2_pc_dup_1;
reg [40:0] s2_pc_dup_2;
reg [40:0] s2_pc_dup_3;
reg [40:0] s3_pc_dup_0;
reg [40:0] s3_pc_dup_1;
reg [40:0] s3_pc_dup_2;
reg [40:0] s3_pc_dup_3;
reg REG;
reg REG_1;
wire [40:0] _s2_spec_new_addr_T_1 =
41'(io_in_bits_resp_in_0_s2_full_pred_2_fallThroughAddr
+ {39'h0, io_in_bits_resp_in_0_s2_full_pred_2_last_may_be_rvi_call, 1'h0});
wire _s2_spec_pop_T_8 =
io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_0
& io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0;
wire _s2_spec_pop_T_9 =
io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing
& io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1;
wire s2_spec_push =
io_s2_fire_2 & ~(_s2_spec_pop_T_8 & io_in_bits_resp_in_0_s2_full_pred_2_hit)
& io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1
& (_s2_spec_pop_T_9 | ~io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing)
& io_in_bits_resp_in_0_s2_full_pred_2_hit
& ~io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing
& io_in_bits_resp_in_0_s2_full_pred_2_is_call & ~io_s3_redirect_2;
wire s2_spec_pop =
io_s2_fire_2 & ~(_s2_spec_pop_T_8 & io_in_bits_resp_in_0_s2_full_pred_2_hit)
& io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1
& (_s2_spec_pop_T_9 | ~io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing)
& io_in_bits_resp_in_0_s2_full_pred_2_hit
& ~io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing
& io_in_bits_resp_in_0_s2_full_pred_2_is_ret & ~io_s3_redirect_2;
wire _GEN = io_in_bits_resp_in_0_s2_full_pred_2_is_ret & io_ctrl_ras_enable;
reg [40:0] s3_top;
reg [40:0] s3_spec_new_addr;
wire _GEN_0 = io_in_bits_resp_in_0_s3_full_pred_2_is_ret & io_ctrl_ras_enable;
reg s3_pushed_in_s2;
reg s3_popped_in_s2;
wire _s3_pop_T_8 =
io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_0
& io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0;
wire _s3_pop_T_9 =
io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing
& io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1;
wire s3_push =
~(_s3_pop_T_8 & io_in_bits_resp_in_0_s3_full_pred_2_hit)
& io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1
& (_s3_pop_T_9 | ~io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing)
& io_in_bits_resp_in_0_s3_full_pred_2_hit
& ~io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing
& io_in_bits_resp_in_0_s3_full_pred_2_is_call;
wire s3_pop =
~(_s3_pop_T_8 & io_in_bits_resp_in_0_s3_full_pred_2_hit)
& io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1
& (_s3_pop_T_9 | ~io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing)
& io_in_bits_resp_in_0_s3_full_pred_2_hit
& ~io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing
& io_in_bits_resp_in_0_s3_full_pred_2_is_ret;
reg [3:0] s3_meta_ssp;
reg [2:0] s3_meta_sctr;
reg s3_meta_TOSW_flag;
reg [4:0] s3_meta_TOSW_value;
reg s3_meta_TOSR_flag;
reg [4:0] s3_meta_TOSR_value;
reg s3_meta_NOS_flag;
reg [4:0] s3_meta_NOS_value;
reg redirect_next_valid_last_r;
reg redirect_next_bits_r_level;
reg [40:0] redirect_next_bits_r_cfiUpdate_pc;
reg redirect_next_bits_r_cfiUpdate_pd_isRVC;
reg redirect_next_bits_r_cfiUpdate_pd_isCall;
reg redirect_next_bits_r_cfiUpdate_pd_isRet;
reg [3:0] redirect_next_bits_r_cfiUpdate_ssp;
reg [1:0] redirect_next_bits_r_cfiUpdate_sctr;
reg redirect_next_bits_r_cfiUpdate_TOSW_flag;
reg [4:0] redirect_next_bits_r_cfiUpdate_TOSW_value;
reg redirect_next_bits_r_cfiUpdate_TOSR_flag;
reg [4:0] redirect_next_bits_r_cfiUpdate_TOSR_value;
reg redirect_next_bits_r_cfiUpdate_NOS_flag;
reg [4:0] redirect_next_bits_r_cfiUpdate_NOS_value;
wire _GEN_1 =
io_update_bits_cfi_idx_bits == io_update_bits_ftb_entry_tailSlot_offset;
wire [40:0] _GEN_2 = {5'h0, _reset_vector_delay_io_out};
always @(posedge clock) begin
if (REG_1) begin
s1_pc_dup_0 <= _GEN_2;
s1_pc_dup_1 <= _GEN_2;
s1_pc_dup_2 <= _GEN_2;
s1_pc_dup_3 <= _GEN_2;
end
else begin
if (io_s0_fire_0)
s1_pc_dup_0 <= io_in_bits_s0_pc_0;
if (io_s0_fire_1)
s1_pc_dup_1 <= io_in_bits_s0_pc_1;
if (io_s0_fire_2)
s1_pc_dup_2 <= io_in_bits_s0_pc_2;
if (io_s0_fire_3)
s1_pc_dup_3 <= io_in_bits_s0_pc_3;
end
if (io_s1_fire_0)
s2_pc_dup_0 <= s1_pc_dup_0;
if (io_s1_fire_1)
s2_pc_dup_1 <= s1_pc_dup_1;
if (io_s1_fire_2)
s2_pc_dup_2 <= s1_pc_dup_2;
if (io_s1_fire_3)
s2_pc_dup_3 <= s1_pc_dup_3;
if (io_s2_fire_0)
s3_pc_dup_0 <= s2_pc_dup_0;
if (io_s2_fire_1)
s3_pc_dup_1 <= s2_pc_dup_1;
if (io_s2_fire_2) begin
s3_pc_dup_2 <= s2_pc_dup_2;
s3_top <= _RASStack_io_spec_pop_addr;
s3_spec_new_addr <= _s2_spec_new_addr_T_1;
s3_pushed_in_s2 <= s2_spec_push;
s3_popped_in_s2 <= s2_spec_pop;
s3_meta_ssp <= _RASStack_io_ssp;
s3_meta_sctr <= _RASStack_io_sctr;
s3_meta_TOSW_flag <= _RASStack_io_TOSW_flag;
s3_meta_TOSW_value <= _RASStack_io_TOSW_value;
s3_meta_TOSR_flag <= _RASStack_io_TOSR_flag;
s3_meta_TOSR_value <= _RASStack_io_TOSR_value;
s3_meta_NOS_flag <= _RASStack_io_NOS_flag;
s3_meta_NOS_value <= _RASStack_io_NOS_value;
end
if (io_s2_fire_3)
s3_pc_dup_3 <= s2_pc_dup_3;
REG <= reset;
REG_1 <= REG & ~reset;
if (io_redirect_valid) begin
redirect_next_bits_r_level <= io_redirect_bits_level;
redirect_next_bits_r_cfiUpdate_pc <= io_redirect_bits_cfiUpdate_pc;
redirect_next_bits_r_cfiUpdate_pd_isRVC <= io_redirect_bits_cfiUpdate_pd_isRVC;
redirect_next_bits_r_cfiUpdate_pd_isCall <= io_redirect_bits_cfiUpdate_pd_isCall;
redirect_next_bits_r_cfiUpdate_pd_isRet <= io_redirect_bits_cfiUpdate_pd_isRet;
redirect_next_bits_r_cfiUpdate_ssp <= io_redirect_bits_cfiUpdate_ssp;
redirect_next_bits_r_cfiUpdate_sctr <= io_redirect_bits_cfiUpdate_sctr;
redirect_next_bits_r_cfiUpdate_TOSW_flag <= io_redirect_bits_cfiUpdate_TOSW_flag;
redirect_next_bits_r_cfiUpdate_TOSW_value <= io_redirect_bits_cfiUpdate_TOSW_value;
redirect_next_bits_r_cfiUpdate_TOSR_flag <= io_redirect_bits_cfiUpdate_TOSR_flag;
redirect_next_bits_r_cfiUpdate_TOSR_value <= io_redirect_bits_cfiUpdate_TOSR_value;
redirect_next_bits_r_cfiUpdate_NOS_flag <= io_redirect_bits_cfiUpdate_NOS_flag;
redirect_next_bits_r_cfiUpdate_NOS_value <= io_redirect_bits_cfiUpdate_NOS_value;
end
end // always @(posedge)
always @(posedge clock or posedge reset) begin
if (reset)
redirect_next_valid_last_r <= 1'h0;
else if (io_redirect_valid | redirect_next_valid_last_r)
redirect_next_valid_last_r <= io_redirect_valid;
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:21];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
for (logic [4:0] i = 5'h0; i < 5'h16; i += 5'h1) begin
_RANDOM[i] = `RANDOM;
end
s1_pc_dup_0 = {_RANDOM[5'h0], _RANDOM[5'h1][8:0]};
s1_pc_dup_1 = {_RANDOM[5'h1][31:9], _RANDOM[5'h2][17:0]};
s1_pc_dup_2 = {_RANDOM[5'h2][31:18], _RANDOM[5'h3][26:0]};
s1_pc_dup_3 = {_RANDOM[5'h3][31:27], _RANDOM[5'h4], _RANDOM[5'h5][3:0]};
s2_pc_dup_0 = {_RANDOM[5'h5][31:4], _RANDOM[5'h6][12:0]};
s2_pc_dup_1 = {_RANDOM[5'h6][31:13], _RANDOM[5'h7][21:0]};
s2_pc_dup_2 = {_RANDOM[5'h7][31:22], _RANDOM[5'h8][30:0]};
s2_pc_dup_3 = {_RANDOM[5'h8][31], _RANDOM[5'h9], _RANDOM[5'hA][7:0]};
s3_pc_dup_0 = {_RANDOM[5'hA][31:8], _RANDOM[5'hB][16:0]};
s3_pc_dup_1 = {_RANDOM[5'hB][31:17], _RANDOM[5'hC][25:0]};
s3_pc_dup_2 = {_RANDOM[5'hC][31:26], _RANDOM[5'hD], _RANDOM[5'hE][2:0]};
s3_pc_dup_3 = {_RANDOM[5'hE][31:3], _RANDOM[5'hF][11:0]};
REG = _RANDOM[5'hF][12];
REG_1 = _RANDOM[5'hF][13];
s3_top = {_RANDOM[5'hF][31:14], _RANDOM[5'h10][22:0]};
s3_spec_new_addr = {_RANDOM[5'h10][31:23], _RANDOM[5'h11]};
s3_pushed_in_s2 = _RANDOM[5'h12][0];
s3_popped_in_s2 = _RANDOM[5'h12][1];
s3_meta_ssp = _RANDOM[5'h12][5:2];
s3_meta_sctr = _RANDOM[5'h12][8:6];
s3_meta_TOSW_flag = _RANDOM[5'h12][9];
s3_meta_TOSW_value = _RANDOM[5'h12][14:10];
s3_meta_TOSR_flag = _RANDOM[5'h12][15];
s3_meta_TOSR_value = _RANDOM[5'h12][20:16];
s3_meta_NOS_flag = _RANDOM[5'h12][21];
s3_meta_NOS_value = _RANDOM[5'h12][26:22];
redirect_next_valid_last_r = _RANDOM[5'h12][27];
redirect_next_bits_r_level = _RANDOM[5'h13][17];
redirect_next_bits_r_cfiUpdate_pc = {_RANDOM[5'h13][31:19], _RANDOM[5'h14][27:0]};
redirect_next_bits_r_cfiUpdate_pd_isRVC = _RANDOM[5'h14][29];
redirect_next_bits_r_cfiUpdate_pd_isCall = _RANDOM[5'h15][0];
redirect_next_bits_r_cfiUpdate_pd_isRet = _RANDOM[5'h15][1];
redirect_next_bits_r_cfiUpdate_ssp = _RANDOM[5'h15][5:2];
redirect_next_bits_r_cfiUpdate_sctr = _RANDOM[5'h15][7:6];
redirect_next_bits_r_cfiUpdate_TOSW_flag = _RANDOM[5'h15][8];
redirect_next_bits_r_cfiUpdate_TOSW_value = _RANDOM[5'h15][13:9];
redirect_next_bits_r_cfiUpdate_TOSR_flag = _RANDOM[5'h15][14];
redirect_next_bits_r_cfiUpdate_TOSR_value = _RANDOM[5'h15][19:15];
redirect_next_bits_r_cfiUpdate_NOS_flag = _RANDOM[5'h15][20];
redirect_next_bits_r_cfiUpdate_NOS_value = _RANDOM[5'h15][25:21];
`endif // RANDOMIZE_REG_INIT
if (reset)
redirect_next_valid_last_r = 1'h0;
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
DelayN_2 reset_vector_delay (
.clock (clock),
.io_in (io_reset_vector),
.io_out (_reset_vector_delay_io_out)
);
RASStack RASStack (
.clock (clock),
.reset (reset),
.io_spec_push_valid (s2_spec_push),
.io_spec_pop_valid (s2_spec_pop),
.io_spec_push_addr (_s2_spec_new_addr_T_1),
.io_s2_fire (io_s2_fire_2),
.io_s3_fire (io_s3_fire_2),
.io_s3_cancel
(io_s3_fire_2 & (s3_pushed_in_s2 != s3_push | s3_popped_in_s2 != s3_pop)),
.io_s3_meta_ssp (s3_meta_ssp),
.io_s3_meta_sctr (s3_meta_sctr),
.io_s3_meta_TOSW_flag (s3_meta_TOSW_flag),
.io_s3_meta_TOSW_value (s3_meta_TOSW_value),
.io_s3_meta_TOSR_flag (s3_meta_TOSR_flag),
.io_s3_meta_TOSR_value (s3_meta_TOSR_value),
.io_s3_meta_NOS_flag (s3_meta_NOS_flag),
.io_s3_meta_NOS_value (s3_meta_NOS_value),
.io_s3_missed_pop (s3_pop & ~s3_popped_in_s2),
.io_s3_missed_push (s3_push & ~s3_pushed_in_s2),
.io_s3_pushAddr (s3_spec_new_addr),
.io_spec_pop_addr (_RASStack_io_spec_pop_addr),
.io_commit_push_valid
(io_update_valid & io_update_bits_ftb_entry_tailSlot_valid
& io_update_bits_ftb_entry_isCall & io_update_bits_jmp_taken
& io_update_bits_cfi_idx_valid & _GEN_1),
.io_commit_pop_valid
(io_update_valid & io_update_bits_ftb_entry_tailSlot_valid
& io_update_bits_ftb_entry_isRet & io_update_bits_jmp_taken
& io_update_bits_cfi_idx_valid & _GEN_1),
.io_commit_meta_TOSW_flag (io_update_bits_meta[17]),
.io_commit_meta_TOSW_value (io_update_bits_meta[16:12]),
.io_commit_meta_ssp (io_update_bits_meta[24:21]),
.io_redirect_valid (redirect_next_valid_last_r),
.io_redirect_isCall
(redirect_next_valid_last_r & ~redirect_next_bits_r_level
& redirect_next_bits_r_cfiUpdate_pd_isCall),
.io_redirect_isRet
(redirect_next_valid_last_r & ~redirect_next_bits_r_level
& redirect_next_bits_r_cfiUpdate_pd_isRet),
.io_redirect_meta_ssp (redirect_next_bits_r_cfiUpdate_ssp),
.io_redirect_meta_sctr ({1'h0, redirect_next_bits_r_cfiUpdate_sctr}),
.io_redirect_meta_TOSW_flag (redirect_next_bits_r_cfiUpdate_TOSW_flag),
.io_redirect_meta_TOSW_value (redirect_next_bits_r_cfiUpdate_TOSW_value),
.io_redirect_meta_TOSR_flag (redirect_next_bits_r_cfiUpdate_TOSR_flag),
.io_redirect_meta_TOSR_value (redirect_next_bits_r_cfiUpdate_TOSR_value),
.io_redirect_meta_NOS_flag (redirect_next_bits_r_cfiUpdate_NOS_flag),
.io_redirect_meta_NOS_value (redirect_next_bits_r_cfiUpdate_NOS_value),
.io_redirect_callAddr
(41'(redirect_next_bits_r_cfiUpdate_pc
+ {38'h0, redirect_next_bits_r_cfiUpdate_pd_isRVC ? 3'h2 : 3'h4})),
.io_ssp (_RASStack_io_ssp),
.io_sctr (_RASStack_io_sctr),
.io_TOSR_flag (_RASStack_io_TOSR_flag),
.io_TOSR_value (_RASStack_io_TOSR_value),
.io_TOSW_flag (_RASStack_io_TOSW_flag),
.io_TOSW_value (_RASStack_io_TOSW_value),
.io_NOS_flag (_RASStack_io_NOS_flag),
.io_NOS_value (_RASStack_io_NOS_value)
);
assign io_out_s2_pc_0 = s2_pc_dup_0;
assign io_out_s2_pc_1 = s2_pc_dup_1;
assign io_out_s2_pc_2 = s2_pc_dup_2;
assign io_out_s2_pc_3 = s2_pc_dup_3;
assign io_out_s2_full_pred_0_br_taken_mask_0 =
io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0;
assign io_out_s2_full_pred_0_br_taken_mask_1 =
io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1;
assign io_out_s2_full_pred_0_slot_valids_0 =
io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_0;
assign io_out_s2_full_pred_0_slot_valids_1 =
io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_1;
assign io_out_s2_full_pred_0_targets_0 = io_in_bits_resp_in_0_s2_full_pred_0_targets_0;
assign io_out_s2_full_pred_0_targets_1 =
io_in_bits_resp_in_0_s2_full_pred_2_is_jalr
? (_GEN
? _RASStack_io_spec_pop_addr
: io_in_bits_resp_in_0_s2_full_pred_0_jalr_target)
: io_in_bits_resp_in_0_s2_full_pred_0_targets_1;
assign io_out_s2_full_pred_0_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_0_offsets_0;
assign io_out_s2_full_pred_0_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_0_offsets_1;
assign io_out_s2_full_pred_0_fallThroughAddr =
io_in_bits_resp_in_0_s2_full_pred_0_fallThroughAddr;
assign io_out_s2_full_pred_0_is_br_sharing =
io_in_bits_resp_in_0_s2_full_pred_0_is_br_sharing;
assign io_out_s2_full_pred_0_hit = io_in_bits_resp_in_0_s2_full_pred_0_hit;
assign io_out_s2_full_pred_1_br_taken_mask_0 =
io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0;
assign io_out_s2_full_pred_1_br_taken_mask_1 =
io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1;
assign io_out_s2_full_pred_1_slot_valids_0 =
io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_0;
assign io_out_s2_full_pred_1_slot_valids_1 =
io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_1;
assign io_out_s2_full_pred_1_targets_0 = io_in_bits_resp_in_0_s2_full_pred_1_targets_0;
assign io_out_s2_full_pred_1_targets_1 =
io_in_bits_resp_in_0_s2_full_pred_2_is_jalr
? (_GEN
? _RASStack_io_spec_pop_addr
: io_in_bits_resp_in_0_s2_full_pred_1_jalr_target)
: io_in_bits_resp_in_0_s2_full_pred_1_targets_1;
assign io_out_s2_full_pred_1_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_1_offsets_0;
assign io_out_s2_full_pred_1_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_1_offsets_1;
assign io_out_s2_full_pred_1_fallThroughAddr =
io_in_bits_resp_in_0_s2_full_pred_1_fallThroughAddr;
assign io_out_s2_full_pred_1_is_br_sharing =
io_in_bits_resp_in_0_s2_full_pred_1_is_br_sharing;
assign io_out_s2_full_pred_1_hit = io_in_bits_resp_in_0_s2_full_pred_1_hit;
assign io_out_s2_full_pred_2_br_taken_mask_0 =
io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0;
assign io_out_s2_full_pred_2_br_taken_mask_1 =
io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1;
assign io_out_s2_full_pred_2_slot_valids_0 =
io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_0;
assign io_out_s2_full_pred_2_slot_valids_1 =
io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1;
assign io_out_s2_full_pred_2_targets_0 = io_in_bits_resp_in_0_s2_full_pred_2_targets_0;
assign io_out_s2_full_pred_2_targets_1 =
io_in_bits_resp_in_0_s2_full_pred_2_is_jalr
? (_GEN
? _RASStack_io_spec_pop_addr
: io_in_bits_resp_in_0_s2_full_pred_2_jalr_target)
: io_in_bits_resp_in_0_s2_full_pred_2_targets_1;
assign io_out_s2_full_pred_2_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_2_offsets_0;
assign io_out_s2_full_pred_2_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_2_offsets_1;
assign io_out_s2_full_pred_2_fallThroughAddr =
io_in_bits_resp_in_0_s2_full_pred_2_fallThroughAddr;
assign io_out_s2_full_pred_2_is_br_sharing =
io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing;
assign io_out_s2_full_pred_2_hit = io_in_bits_resp_in_0_s2_full_pred_2_hit;
assign io_out_s2_full_pred_3_br_taken_mask_0 =
io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0;
assign io_out_s2_full_pred_3_br_taken_mask_1 =
io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1;
assign io_out_s2_full_pred_3_slot_valids_0 =
io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_0;
assign io_out_s2_full_pred_3_slot_valids_1 =
io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_1;
assign io_out_s2_full_pred_3_targets_0 = io_in_bits_resp_in_0_s2_full_pred_3_targets_0;
assign io_out_s2_full_pred_3_targets_1 =
io_in_bits_resp_in_0_s2_full_pred_2_is_jalr
? (_GEN
? _RASStack_io_spec_pop_addr
: io_in_bits_resp_in_0_s2_full_pred_3_jalr_target)
: io_in_bits_resp_in_0_s2_full_pred_3_targets_1;
assign io_out_s2_full_pred_3_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_3_offsets_0;
assign io_out_s2_full_pred_3_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_3_offsets_1;
assign io_out_s2_full_pred_3_fallThroughAddr =
io_in_bits_resp_in_0_s2_full_pred_3_fallThroughAddr;
assign io_out_s2_full_pred_3_fallThroughErr =
io_in_bits_resp_in_0_s2_full_pred_3_fallThroughErr;
assign io_out_s2_full_pred_3_is_br_sharing =
io_in_bits_resp_in_0_s2_full_pred_3_is_br_sharing;
assign io_out_s2_full_pred_3_hit = io_in_bits_resp_in_0_s2_full_pred_3_hit;
assign io_out_s3_pc_0 = s3_pc_dup_0;
assign io_out_s3_pc_1 = s3_pc_dup_1;
assign io_out_s3_pc_2 = s3_pc_dup_2;
assign io_out_s3_pc_3 = s3_pc_dup_3;
assign io_out_s3_full_pred_0_br_taken_mask_0 =
io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0;
assign io_out_s3_full_pred_0_br_taken_mask_1 =
io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1;
assign io_out_s3_full_pred_0_slot_valids_0 =
io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_0;
assign io_out_s3_full_pred_0_slot_valids_1 =
io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_1;
assign io_out_s3_full_pred_0_targets_0 = io_in_bits_resp_in_0_s3_full_pred_0_targets_0;
assign io_out_s3_full_pred_0_targets_1 =
io_in_bits_resp_in_0_s3_full_pred_2_is_jalr
? (_GEN_0 ? s3_top : io_in_bits_resp_in_0_s3_full_pred_0_jalr_target)
: io_in_bits_resp_in_0_s3_full_pred_0_targets_1;
assign io_out_s3_full_pred_0_fallThroughAddr =
io_in_bits_resp_in_0_s3_full_pred_0_fallThroughAddr;
assign io_out_s3_full_pred_0_fallThroughErr =
io_in_bits_resp_in_0_s3_full_pred_0_fallThroughErr;
assign io_out_s3_full_pred_0_is_br_sharing =
io_in_bits_resp_in_0_s3_full_pred_0_is_br_sharing;
assign io_out_s3_full_pred_0_hit = io_in_bits_resp_in_0_s3_full_pred_0_hit;
assign io_out_s3_full_pred_1_br_taken_mask_0 =
io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0;
assign io_out_s3_full_pred_1_br_taken_mask_1 =
io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1;
assign io_out_s3_full_pred_1_slot_valids_0 =
io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_0;
assign io_out_s3_full_pred_1_slot_valids_1 =
io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_1;
assign io_out_s3_full_pred_1_targets_0 = io_in_bits_resp_in_0_s3_full_pred_1_targets_0;
assign io_out_s3_full_pred_1_targets_1 =
io_in_bits_resp_in_0_s3_full_pred_2_is_jalr
? (_GEN_0 ? s3_top : io_in_bits_resp_in_0_s3_full_pred_1_jalr_target)
: io_in_bits_resp_in_0_s3_full_pred_1_targets_1;
assign io_out_s3_full_pred_1_fallThroughAddr =
io_in_bits_resp_in_0_s3_full_pred_1_fallThroughAddr;
assign io_out_s3_full_pred_1_fallThroughErr =
io_in_bits_resp_in_0_s3_full_pred_1_fallThroughErr;
assign io_out_s3_full_pred_1_is_br_sharing =
io_in_bits_resp_in_0_s3_full_pred_1_is_br_sharing;
assign io_out_s3_full_pred_1_hit = io_in_bits_resp_in_0_s3_full_pred_1_hit;
assign io_out_s3_full_pred_2_br_taken_mask_0 =
io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0;
assign io_out_s3_full_pred_2_br_taken_mask_1 =
io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1;
assign io_out_s3_full_pred_2_slot_valids_0 =
io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_0;
assign io_out_s3_full_pred_2_slot_valids_1 =
io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1;
assign io_out_s3_full_pred_2_targets_0 = io_in_bits_resp_in_0_s3_full_pred_2_targets_0;
assign io_out_s3_full_pred_2_targets_1 =
io_in_bits_resp_in_0_s3_full_pred_2_is_jalr
? (_GEN_0 ? s3_top : io_in_bits_resp_in_0_s3_full_pred_2_jalr_target)
: io_in_bits_resp_in_0_s3_full_pred_2_targets_1;
assign io_out_s3_full_pred_2_fallThroughAddr =
io_in_bits_resp_in_0_s3_full_pred_2_fallThroughAddr;
assign io_out_s3_full_pred_2_fallThroughErr =
io_in_bits_resp_in_0_s3_full_pred_2_fallThroughErr;
assign io_out_s3_full_pred_2_is_br_sharing =
io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing;
assign io_out_s3_full_pred_2_hit = io_in_bits_resp_in_0_s3_full_pred_2_hit;
assign io_out_s3_full_pred_3_br_taken_mask_0 =
io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0;
assign io_out_s3_full_pred_3_br_taken_mask_1 =
io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1;
assign io_out_s3_full_pred_3_slot_valids_0 =
io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_0;
assign io_out_s3_full_pred_3_slot_valids_1 =
io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_1;
assign io_out_s3_full_pred_3_targets_0 = io_in_bits_resp_in_0_s3_full_pred_3_targets_0;
assign io_out_s3_full_pred_3_targets_1 =
io_in_bits_resp_in_0_s3_full_pred_2_is_jalr
? (_GEN_0 ? s3_top : io_in_bits_resp_in_0_s3_full_pred_3_jalr_target)
: io_in_bits_resp_in_0_s3_full_pred_3_targets_1;
assign io_out_s3_full_pred_3_offsets_0 = io_in_bits_resp_in_0_s3_full_pred_3_offsets_0;
assign io_out_s3_full_pred_3_offsets_1 = io_in_bits_resp_in_0_s3_full_pred_3_offsets_1;
assign io_out_s3_full_pred_3_fallThroughAddr =
io_in_bits_resp_in_0_s3_full_pred_3_fallThroughAddr;
assign io_out_s3_full_pred_3_fallThroughErr =
io_in_bits_resp_in_0_s3_full_pred_3_fallThroughErr;
assign io_out_s3_full_pred_3_is_br_sharing =
io_in_bits_resp_in_0_s3_full_pred_3_is_br_sharing;
assign io_out_s3_full_pred_3_hit = io_in_bits_resp_in_0_s3_full_pred_3_hit;
assign io_out_last_stage_meta =
{198'h0,
s3_meta_ssp,
s3_meta_sctr,
s3_meta_TOSW_flag,
s3_meta_TOSW_value,
s3_meta_TOSR_flag,
s3_meta_TOSR_value,
s3_meta_NOS_flag,
s3_meta_NOS_value};
assign io_out_last_stage_spec_info_ssp = s3_meta_ssp;
assign io_out_last_stage_spec_info_sctr = s3_meta_sctr[1:0];
assign io_out_last_stage_spec_info_TOSW_flag = s3_meta_TOSW_flag;
assign io_out_last_stage_spec_info_TOSW_value = s3_meta_TOSW_value;
assign io_out_last_stage_spec_info_TOSR_flag = s3_meta_TOSR_flag;
assign io_out_last_stage_spec_info_TOSR_value = s3_meta_TOSR_value;
assign io_out_last_stage_spec_info_NOS_flag = s3_meta_NOS_flag;
assign io_out_last_stage_spec_info_NOS_value = s3_meta_NOS_value;
assign io_out_last_stage_spec_info_topAddr = s3_top;
assign io_out_last_stage_ftb_entry_valid =
io_in_bits_resp_in_0_last_stage_ftb_entry_valid;
assign io_out_last_stage_ftb_entry_brSlots_0_offset =
io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_offset;
assign io_out_last_stage_ftb_entry_brSlots_0_lower =
io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_lower;
assign io_out_last_stage_ftb_entry_brSlots_0_tarStat =
io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_tarStat;
assign io_out_last_stage_ftb_entry_brSlots_0_sharing =
io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_sharing;
assign io_out_last_stage_ftb_entry_brSlots_0_valid =
io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_valid;
assign io_out_last_stage_ftb_entry_tailSlot_offset =
io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_offset;
assign io_out_last_stage_ftb_entry_tailSlot_lower =
io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_lower;
assign io_out_last_stage_ftb_entry_tailSlot_tarStat =
io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_tarStat;
assign io_out_last_stage_ftb_entry_tailSlot_sharing =
io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_sharing;
assign io_out_last_stage_ftb_entry_tailSlot_valid =
io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_valid;
assign io_out_last_stage_ftb_entry_pftAddr =
io_in_bits_resp_in_0_last_stage_ftb_entry_pftAddr;
assign io_out_last_stage_ftb_entry_carry =
io_in_bits_resp_in_0_last_stage_ftb_entry_carry;
assign io_out_last_stage_ftb_entry_isCall =
io_in_bits_resp_in_0_last_stage_ftb_entry_isCall;
assign io_out_last_stage_ftb_entry_isRet =
io_in_bits_resp_in_0_last_stage_ftb_entry_isRet;
assign io_out_last_stage_ftb_entry_isJalr =
io_in_bits_resp_in_0_last_stage_ftb_entry_isJalr;
assign io_out_last_stage_ftb_entry_last_may_be_rvi_call =
io_in_bits_resp_in_0_last_stage_ftb_entry_last_may_be_rvi_call;
assign io_out_last_stage_ftb_entry_always_taken_0 =
io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_0;
assign io_out_last_stage_ftb_entry_always_taken_1 =
io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_1;
endmodule

1934
rtl/BPUTop/RASStack.sv
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244
rtl/BPUTop/SCTable.sv
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@ -1,244 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module SCTable(
input clock,
input reset,
input io_req_valid,
input [40:0] io_req_bits_pc,
output [5:0] io_resp_ctrs_0_0,
output [5:0] io_resp_ctrs_0_1,
output [5:0] io_resp_ctrs_1_0,
output [5:0] io_resp_ctrs_1_1,
input [40:0] io_update_pc,
input io_update_mask_0,
input io_update_mask_1,
input [5:0] io_update_oldCtrs_0,
input [5:0] io_update_oldCtrs_1,
input io_update_tagePreds_0,
input io_update_tagePreds_1,
input io_update_takens_0,
input io_update_takens_1
);
wire _wrbypasses_1_io_hit;
wire _wrbypasses_1_io_hit_data_0_valid;
wire [5:0] _wrbypasses_1_io_hit_data_0_bits;
wire _wrbypasses_1_io_hit_data_1_valid;
wire [5:0] _wrbypasses_1_io_hit_data_1_bits;
wire _wrbypasses_0_io_hit;
wire _wrbypasses_0_io_hit_data_0_valid;
wire [5:0] _wrbypasses_0_io_hit_data_0_bits;
wire _wrbypasses_0_io_hit_data_1_valid;
wire [5:0] _wrbypasses_0_io_hit_data_1_bits;
wire [5:0] _table_io_r_resp_data_0;
wire [5:0] _table_io_r_resp_data_1;
wire [5:0] _table_io_r_resp_data_2;
wire [5:0] _table_io_r_resp_data_3;
reg [40:0] s1_pc;
wire updateWayMask_0 =
io_update_mask_0 & ~(io_update_pc[1]) & ~io_update_tagePreds_0 | io_update_mask_1
& io_update_pc[1] & ~io_update_tagePreds_1;
wire updateWayMask_1 =
io_update_mask_0 & ~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_mask_1
& io_update_pc[1] & io_update_tagePreds_1;
wire updateWayMask_2 =
io_update_mask_0 & io_update_pc[1] & ~io_update_tagePreds_0 | io_update_mask_1
& ~(io_update_pc[1]) & ~io_update_tagePreds_1;
wire updateWayMask_3 =
io_update_mask_0 & io_update_pc[1] & io_update_tagePreds_0 | io_update_mask_1
& ~(io_update_pc[1]) & io_update_tagePreds_1;
wire ctrPos =
~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_pc[1] & io_update_tagePreds_1;
wire [5:0] oldCtr =
(~(io_update_pc[1]) & _wrbypasses_0_io_hit | io_update_pc[1] & _wrbypasses_1_io_hit)
& (ctrPos
? ~(io_update_pc[1]) & _wrbypasses_0_io_hit_data_1_valid | io_update_pc[1]
& _wrbypasses_1_io_hit_data_1_valid
: ~(io_update_pc[1]) & _wrbypasses_0_io_hit_data_0_valid | io_update_pc[1]
& _wrbypasses_1_io_hit_data_0_valid)
? (ctrPos
? (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_1_bits)
| (io_update_pc[1] ? _wrbypasses_1_io_hit_data_1_bits : 6'h0)
: (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _wrbypasses_1_io_hit_data_0_bits : 6'h0))
: (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_0)
| (io_update_pc[1] ? io_update_oldCtrs_1 : 6'h0);
wire taken =
~(io_update_pc[1]) & io_update_takens_0 | io_update_pc[1] & io_update_takens_1;
wire [5:0] update_wdata_0 =
oldCtr == 6'h1F & taken
? 6'h1F
: oldCtr == 6'h20 & ~taken ? 6'h20 : taken ? 6'(oldCtr + 6'h1) : 6'(oldCtr - 6'h1);
wire ctrPos_1 =
io_update_pc[1] & io_update_tagePreds_0 | ~(io_update_pc[1]) & io_update_tagePreds_1;
wire [5:0] oldCtr_1 =
(io_update_pc[1] & _wrbypasses_0_io_hit | ~(io_update_pc[1]) & _wrbypasses_1_io_hit)
& (ctrPos_1
? io_update_pc[1] & _wrbypasses_0_io_hit_data_1_valid | ~(io_update_pc[1])
& _wrbypasses_1_io_hit_data_1_valid
: io_update_pc[1] & _wrbypasses_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _wrbypasses_1_io_hit_data_0_valid)
? (ctrPos_1
? (io_update_pc[1] ? _wrbypasses_0_io_hit_data_1_bits : 6'h0)
| (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_1_bits)
: (io_update_pc[1] ? _wrbypasses_0_io_hit_data_0_bits : 6'h0)
| (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_0_bits))
: (io_update_pc[1] ? io_update_oldCtrs_0 : 6'h0)
| (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_1);
wire taken_1 =
io_update_pc[1] & io_update_takens_0 | ~(io_update_pc[1]) & io_update_takens_1;
wire [5:0] update_wdata_1 =
oldCtr_1 == 6'h1F & taken_1
? 6'h1F
: oldCtr_1 == 6'h20 & ~taken_1
? 6'h20
: taken_1 ? 6'(oldCtr_1 + 6'h1) : 6'(oldCtr_1 - 6'h1);
wire [5:0] _GEN = io_update_pc[1] ? 6'h0 : update_wdata_0;
wire [5:0] _GEN_0 = io_update_pc[1] ? update_wdata_1 : 6'h0;
wire [5:0] _GEN_1 = io_update_pc[1] ? update_wdata_0 : 6'h0;
wire [5:0] _GEN_2 = io_update_pc[1] ? 6'h0 : update_wdata_1;
always @(posedge clock) begin
if (io_req_valid)
s1_pc <= io_req_bits_pc;
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:1];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin
_RANDOM[i[0]] = `RANDOM;
end
s1_pc = {_RANDOM[1'h0][31:8], _RANDOM[1'h1][16:0]};
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
SRAMTemplate_35 table_0 (
.clock (clock),
.reset (reset),
.io_r_req_valid (io_req_valid),
.io_r_req_bits_setIdx (io_req_bits_pc[8:1]),
.io_r_resp_data_0 (_table_io_r_resp_data_0),
.io_r_resp_data_1 (_table_io_r_resp_data_1),
.io_r_resp_data_2 (_table_io_r_resp_data_2),
.io_r_resp_data_3 (_table_io_r_resp_data_3),
.io_w_req_valid (io_update_mask_0 | io_update_mask_1),
.io_w_req_bits_setIdx (io_update_pc[8:1]),
.io_w_req_bits_data_0 (update_wdata_0),
.io_w_req_bits_data_1 (update_wdata_0),
.io_w_req_bits_data_2 (update_wdata_1),
.io_w_req_bits_data_3 (update_wdata_1),
.io_w_req_bits_waymask
({updateWayMask_3, updateWayMask_2, updateWayMask_1, updateWayMask_0})
);
WrBypass_33 wrbypasses_0 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0),
.io_write_idx (io_update_pc[8:1]),
.io_write_data_0 (_GEN | _GEN_0),
.io_write_data_1 (_GEN | _GEN_0),
.io_write_way_mask_0
(~(io_update_pc[1]) & updateWayMask_0 | io_update_pc[1] & updateWayMask_2),
.io_write_way_mask_1
(~(io_update_pc[1]) & updateWayMask_1 | io_update_pc[1] & updateWayMask_3),
.io_hit (_wrbypasses_0_io_hit),
.io_hit_data_0_valid (_wrbypasses_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_wrbypasses_0_io_hit_data_0_bits),
.io_hit_data_1_valid (_wrbypasses_0_io_hit_data_1_valid),
.io_hit_data_1_bits (_wrbypasses_0_io_hit_data_1_bits)
);
WrBypass_33 wrbypasses_1 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1),
.io_write_idx (io_update_pc[8:1]),
.io_write_data_0 (_GEN_1 | _GEN_2),
.io_write_data_1 (_GEN_1 | _GEN_2),
.io_write_way_mask_0
(io_update_pc[1] & updateWayMask_0 | ~(io_update_pc[1]) & updateWayMask_2),
.io_write_way_mask_1
(io_update_pc[1] & updateWayMask_1 | ~(io_update_pc[1]) & updateWayMask_3),
.io_hit (_wrbypasses_1_io_hit),
.io_hit_data_0_valid (_wrbypasses_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_wrbypasses_1_io_hit_data_0_bits),
.io_hit_data_1_valid (_wrbypasses_1_io_hit_data_1_valid),
.io_hit_data_1_bits (_wrbypasses_1_io_hit_data_1_bits)
);
assign io_resp_ctrs_0_0 =
(s1_pc[1] ? 6'h0 : _table_io_r_resp_data_0)
| (s1_pc[1] ? _table_io_r_resp_data_2 : 6'h0);
assign io_resp_ctrs_0_1 =
(s1_pc[1] ? 6'h0 : _table_io_r_resp_data_1)
| (s1_pc[1] ? _table_io_r_resp_data_3 : 6'h0);
assign io_resp_ctrs_1_0 =
(s1_pc[1] ? _table_io_r_resp_data_0 : 6'h0)
| (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_2);
assign io_resp_ctrs_1_1 =
(s1_pc[1] ? _table_io_r_resp_data_1 : 6'h0)
| (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_3);
endmodule

250
rtl/BPUTop/SCTable_1.sv
View File

@ -1,250 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module SCTable_1(
input clock,
input reset,
input io_req_valid,
input [40:0] io_req_bits_pc,
input [3:0] io_req_bits_folded_hist_hist_12_folded_hist,
output [5:0] io_resp_ctrs_0_0,
output [5:0] io_resp_ctrs_0_1,
output [5:0] io_resp_ctrs_1_0,
output [5:0] io_resp_ctrs_1_1,
input [40:0] io_update_pc,
input [3:0] io_update_folded_hist_hist_12_folded_hist,
input io_update_mask_0,
input io_update_mask_1,
input [5:0] io_update_oldCtrs_0,
input [5:0] io_update_oldCtrs_1,
input io_update_tagePreds_0,
input io_update_tagePreds_1,
input io_update_takens_0,
input io_update_takens_1
);
wire _wrbypasses_1_io_hit;
wire _wrbypasses_1_io_hit_data_0_valid;
wire [5:0] _wrbypasses_1_io_hit_data_0_bits;
wire _wrbypasses_1_io_hit_data_1_valid;
wire [5:0] _wrbypasses_1_io_hit_data_1_bits;
wire _wrbypasses_0_io_hit;
wire _wrbypasses_0_io_hit_data_0_valid;
wire [5:0] _wrbypasses_0_io_hit_data_0_bits;
wire _wrbypasses_0_io_hit_data_1_valid;
wire [5:0] _wrbypasses_0_io_hit_data_1_bits;
wire [5:0] _table_io_r_resp_data_0;
wire [5:0] _table_io_r_resp_data_1;
wire [5:0] _table_io_r_resp_data_2;
wire [5:0] _table_io_r_resp_data_3;
reg [40:0] s1_pc;
wire updateWayMask_0 =
io_update_mask_0 & ~(io_update_pc[1]) & ~io_update_tagePreds_0 | io_update_mask_1
& io_update_pc[1] & ~io_update_tagePreds_1;
wire updateWayMask_1 =
io_update_mask_0 & ~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_mask_1
& io_update_pc[1] & io_update_tagePreds_1;
wire updateWayMask_2 =
io_update_mask_0 & io_update_pc[1] & ~io_update_tagePreds_0 | io_update_mask_1
& ~(io_update_pc[1]) & ~io_update_tagePreds_1;
wire updateWayMask_3 =
io_update_mask_0 & io_update_pc[1] & io_update_tagePreds_0 | io_update_mask_1
& ~(io_update_pc[1]) & io_update_tagePreds_1;
wire [7:0] update_idx =
{io_update_pc[8:5], io_update_pc[4:1] ^ io_update_folded_hist_hist_12_folded_hist};
wire ctrPos =
~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_pc[1] & io_update_tagePreds_1;
wire [5:0] oldCtr =
(~(io_update_pc[1]) & _wrbypasses_0_io_hit | io_update_pc[1] & _wrbypasses_1_io_hit)
& (ctrPos
? ~(io_update_pc[1]) & _wrbypasses_0_io_hit_data_1_valid | io_update_pc[1]
& _wrbypasses_1_io_hit_data_1_valid
: ~(io_update_pc[1]) & _wrbypasses_0_io_hit_data_0_valid | io_update_pc[1]
& _wrbypasses_1_io_hit_data_0_valid)
? (ctrPos
? (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_1_bits)
| (io_update_pc[1] ? _wrbypasses_1_io_hit_data_1_bits : 6'h0)
: (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _wrbypasses_1_io_hit_data_0_bits : 6'h0))
: (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_0)
| (io_update_pc[1] ? io_update_oldCtrs_1 : 6'h0);
wire taken =
~(io_update_pc[1]) & io_update_takens_0 | io_update_pc[1] & io_update_takens_1;
wire [5:0] update_wdata_0 =
oldCtr == 6'h1F & taken
? 6'h1F
: oldCtr == 6'h20 & ~taken ? 6'h20 : taken ? 6'(oldCtr + 6'h1) : 6'(oldCtr - 6'h1);
wire ctrPos_1 =
io_update_pc[1] & io_update_tagePreds_0 | ~(io_update_pc[1]) & io_update_tagePreds_1;
wire [5:0] oldCtr_1 =
(io_update_pc[1] & _wrbypasses_0_io_hit | ~(io_update_pc[1]) & _wrbypasses_1_io_hit)
& (ctrPos_1
? io_update_pc[1] & _wrbypasses_0_io_hit_data_1_valid | ~(io_update_pc[1])
& _wrbypasses_1_io_hit_data_1_valid
: io_update_pc[1] & _wrbypasses_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _wrbypasses_1_io_hit_data_0_valid)
? (ctrPos_1
? (io_update_pc[1] ? _wrbypasses_0_io_hit_data_1_bits : 6'h0)
| (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_1_bits)
: (io_update_pc[1] ? _wrbypasses_0_io_hit_data_0_bits : 6'h0)
| (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_0_bits))
: (io_update_pc[1] ? io_update_oldCtrs_0 : 6'h0)
| (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_1);
wire taken_1 =
io_update_pc[1] & io_update_takens_0 | ~(io_update_pc[1]) & io_update_takens_1;
wire [5:0] update_wdata_1 =
oldCtr_1 == 6'h1F & taken_1
? 6'h1F
: oldCtr_1 == 6'h20 & ~taken_1
? 6'h20
: taken_1 ? 6'(oldCtr_1 + 6'h1) : 6'(oldCtr_1 - 6'h1);
wire [5:0] _GEN = io_update_pc[1] ? 6'h0 : update_wdata_0;
wire [5:0] _GEN_0 = io_update_pc[1] ? update_wdata_1 : 6'h0;
wire [5:0] _GEN_1 = io_update_pc[1] ? update_wdata_0 : 6'h0;
wire [5:0] _GEN_2 = io_update_pc[1] ? 6'h0 : update_wdata_1;
always @(posedge clock) begin
if (io_req_valid)
s1_pc <= io_req_bits_pc;
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:1];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin
_RANDOM[i[0]] = `RANDOM;
end
s1_pc = {_RANDOM[1'h0][31:8], _RANDOM[1'h1][16:0]};
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
SRAMTemplate_35 table_0 (
.clock (clock),
.reset (reset),
.io_r_req_valid (io_req_valid),
.io_r_req_bits_setIdx
({io_req_bits_pc[8:5],
io_req_bits_pc[4:1] ^ io_req_bits_folded_hist_hist_12_folded_hist}),
.io_r_resp_data_0 (_table_io_r_resp_data_0),
.io_r_resp_data_1 (_table_io_r_resp_data_1),
.io_r_resp_data_2 (_table_io_r_resp_data_2),
.io_r_resp_data_3 (_table_io_r_resp_data_3),
.io_w_req_valid (io_update_mask_0 | io_update_mask_1),
.io_w_req_bits_setIdx (update_idx),
.io_w_req_bits_data_0 (update_wdata_0),
.io_w_req_bits_data_1 (update_wdata_0),
.io_w_req_bits_data_2 (update_wdata_1),
.io_w_req_bits_data_3 (update_wdata_1),
.io_w_req_bits_waymask
({updateWayMask_3, updateWayMask_2, updateWayMask_1, updateWayMask_0})
);
WrBypass_33 wrbypasses_0 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0),
.io_write_idx (update_idx),
.io_write_data_0 (_GEN | _GEN_0),
.io_write_data_1 (_GEN | _GEN_0),
.io_write_way_mask_0
(~(io_update_pc[1]) & updateWayMask_0 | io_update_pc[1] & updateWayMask_2),
.io_write_way_mask_1
(~(io_update_pc[1]) & updateWayMask_1 | io_update_pc[1] & updateWayMask_3),
.io_hit (_wrbypasses_0_io_hit),
.io_hit_data_0_valid (_wrbypasses_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_wrbypasses_0_io_hit_data_0_bits),
.io_hit_data_1_valid (_wrbypasses_0_io_hit_data_1_valid),
.io_hit_data_1_bits (_wrbypasses_0_io_hit_data_1_bits)
);
WrBypass_33 wrbypasses_1 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1),
.io_write_idx (update_idx),
.io_write_data_0 (_GEN_1 | _GEN_2),
.io_write_data_1 (_GEN_1 | _GEN_2),
.io_write_way_mask_0
(io_update_pc[1] & updateWayMask_0 | ~(io_update_pc[1]) & updateWayMask_2),
.io_write_way_mask_1
(io_update_pc[1] & updateWayMask_1 | ~(io_update_pc[1]) & updateWayMask_3),
.io_hit (_wrbypasses_1_io_hit),
.io_hit_data_0_valid (_wrbypasses_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_wrbypasses_1_io_hit_data_0_bits),
.io_hit_data_1_valid (_wrbypasses_1_io_hit_data_1_valid),
.io_hit_data_1_bits (_wrbypasses_1_io_hit_data_1_bits)
);
assign io_resp_ctrs_0_0 =
(s1_pc[1] ? 6'h0 : _table_io_r_resp_data_0)
| (s1_pc[1] ? _table_io_r_resp_data_2 : 6'h0);
assign io_resp_ctrs_0_1 =
(s1_pc[1] ? 6'h0 : _table_io_r_resp_data_1)
| (s1_pc[1] ? _table_io_r_resp_data_3 : 6'h0);
assign io_resp_ctrs_1_0 =
(s1_pc[1] ? _table_io_r_resp_data_0 : 6'h0)
| (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_2);
assign io_resp_ctrs_1_1 =
(s1_pc[1] ? _table_io_r_resp_data_1 : 6'h0)
| (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_3);
endmodule

248
rtl/BPUTop/SCTable_2.sv
View File

@ -1,248 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module SCTable_2(
input clock,
input reset,
input io_req_valid,
input [40:0] io_req_bits_pc,
input [7:0] io_req_bits_folded_hist_hist_11_folded_hist,
output [5:0] io_resp_ctrs_0_0,
output [5:0] io_resp_ctrs_0_1,
output [5:0] io_resp_ctrs_1_0,
output [5:0] io_resp_ctrs_1_1,
input [40:0] io_update_pc,
input [7:0] io_update_folded_hist_hist_11_folded_hist,
input io_update_mask_0,
input io_update_mask_1,
input [5:0] io_update_oldCtrs_0,
input [5:0] io_update_oldCtrs_1,
input io_update_tagePreds_0,
input io_update_tagePreds_1,
input io_update_takens_0,
input io_update_takens_1
);
wire _wrbypasses_1_io_hit;
wire _wrbypasses_1_io_hit_data_0_valid;
wire [5:0] _wrbypasses_1_io_hit_data_0_bits;
wire _wrbypasses_1_io_hit_data_1_valid;
wire [5:0] _wrbypasses_1_io_hit_data_1_bits;
wire _wrbypasses_0_io_hit;
wire _wrbypasses_0_io_hit_data_0_valid;
wire [5:0] _wrbypasses_0_io_hit_data_0_bits;
wire _wrbypasses_0_io_hit_data_1_valid;
wire [5:0] _wrbypasses_0_io_hit_data_1_bits;
wire [5:0] _table_io_r_resp_data_0;
wire [5:0] _table_io_r_resp_data_1;
wire [5:0] _table_io_r_resp_data_2;
wire [5:0] _table_io_r_resp_data_3;
reg [40:0] s1_pc;
wire updateWayMask_0 =
io_update_mask_0 & ~(io_update_pc[1]) & ~io_update_tagePreds_0 | io_update_mask_1
& io_update_pc[1] & ~io_update_tagePreds_1;
wire updateWayMask_1 =
io_update_mask_0 & ~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_mask_1
& io_update_pc[1] & io_update_tagePreds_1;
wire updateWayMask_2 =
io_update_mask_0 & io_update_pc[1] & ~io_update_tagePreds_0 | io_update_mask_1
& ~(io_update_pc[1]) & ~io_update_tagePreds_1;
wire updateWayMask_3 =
io_update_mask_0 & io_update_pc[1] & io_update_tagePreds_0 | io_update_mask_1
& ~(io_update_pc[1]) & io_update_tagePreds_1;
wire [7:0] update_idx = io_update_pc[8:1] ^ io_update_folded_hist_hist_11_folded_hist;
wire ctrPos =
~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_pc[1] & io_update_tagePreds_1;
wire [5:0] oldCtr =
(~(io_update_pc[1]) & _wrbypasses_0_io_hit | io_update_pc[1] & _wrbypasses_1_io_hit)
& (ctrPos
? ~(io_update_pc[1]) & _wrbypasses_0_io_hit_data_1_valid | io_update_pc[1]
& _wrbypasses_1_io_hit_data_1_valid
: ~(io_update_pc[1]) & _wrbypasses_0_io_hit_data_0_valid | io_update_pc[1]
& _wrbypasses_1_io_hit_data_0_valid)
? (ctrPos
? (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_1_bits)
| (io_update_pc[1] ? _wrbypasses_1_io_hit_data_1_bits : 6'h0)
: (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _wrbypasses_1_io_hit_data_0_bits : 6'h0))
: (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_0)
| (io_update_pc[1] ? io_update_oldCtrs_1 : 6'h0);
wire taken =
~(io_update_pc[1]) & io_update_takens_0 | io_update_pc[1] & io_update_takens_1;
wire [5:0] update_wdata_0 =
oldCtr == 6'h1F & taken
? 6'h1F
: oldCtr == 6'h20 & ~taken ? 6'h20 : taken ? 6'(oldCtr + 6'h1) : 6'(oldCtr - 6'h1);
wire ctrPos_1 =
io_update_pc[1] & io_update_tagePreds_0 | ~(io_update_pc[1]) & io_update_tagePreds_1;
wire [5:0] oldCtr_1 =
(io_update_pc[1] & _wrbypasses_0_io_hit | ~(io_update_pc[1]) & _wrbypasses_1_io_hit)
& (ctrPos_1
? io_update_pc[1] & _wrbypasses_0_io_hit_data_1_valid | ~(io_update_pc[1])
& _wrbypasses_1_io_hit_data_1_valid
: io_update_pc[1] & _wrbypasses_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _wrbypasses_1_io_hit_data_0_valid)
? (ctrPos_1
? (io_update_pc[1] ? _wrbypasses_0_io_hit_data_1_bits : 6'h0)
| (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_1_bits)
: (io_update_pc[1] ? _wrbypasses_0_io_hit_data_0_bits : 6'h0)
| (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_0_bits))
: (io_update_pc[1] ? io_update_oldCtrs_0 : 6'h0)
| (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_1);
wire taken_1 =
io_update_pc[1] & io_update_takens_0 | ~(io_update_pc[1]) & io_update_takens_1;
wire [5:0] update_wdata_1 =
oldCtr_1 == 6'h1F & taken_1
? 6'h1F
: oldCtr_1 == 6'h20 & ~taken_1
? 6'h20
: taken_1 ? 6'(oldCtr_1 + 6'h1) : 6'(oldCtr_1 - 6'h1);
wire [5:0] _GEN = io_update_pc[1] ? 6'h0 : update_wdata_0;
wire [5:0] _GEN_0 = io_update_pc[1] ? update_wdata_1 : 6'h0;
wire [5:0] _GEN_1 = io_update_pc[1] ? update_wdata_0 : 6'h0;
wire [5:0] _GEN_2 = io_update_pc[1] ? 6'h0 : update_wdata_1;
always @(posedge clock) begin
if (io_req_valid)
s1_pc <= io_req_bits_pc;
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:1];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin
_RANDOM[i[0]] = `RANDOM;
end
s1_pc = {_RANDOM[1'h0][31:8], _RANDOM[1'h1][16:0]};
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
SRAMTemplate_35 table_0 (
.clock (clock),
.reset (reset),
.io_r_req_valid (io_req_valid),
.io_r_req_bits_setIdx
(io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_11_folded_hist),
.io_r_resp_data_0 (_table_io_r_resp_data_0),
.io_r_resp_data_1 (_table_io_r_resp_data_1),
.io_r_resp_data_2 (_table_io_r_resp_data_2),
.io_r_resp_data_3 (_table_io_r_resp_data_3),
.io_w_req_valid (io_update_mask_0 | io_update_mask_1),
.io_w_req_bits_setIdx (update_idx),
.io_w_req_bits_data_0 (update_wdata_0),
.io_w_req_bits_data_1 (update_wdata_0),
.io_w_req_bits_data_2 (update_wdata_1),
.io_w_req_bits_data_3 (update_wdata_1),
.io_w_req_bits_waymask
({updateWayMask_3, updateWayMask_2, updateWayMask_1, updateWayMask_0})
);
WrBypass_33 wrbypasses_0 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0),
.io_write_idx (update_idx),
.io_write_data_0 (_GEN | _GEN_0),
.io_write_data_1 (_GEN | _GEN_0),
.io_write_way_mask_0
(~(io_update_pc[1]) & updateWayMask_0 | io_update_pc[1] & updateWayMask_2),
.io_write_way_mask_1
(~(io_update_pc[1]) & updateWayMask_1 | io_update_pc[1] & updateWayMask_3),
.io_hit (_wrbypasses_0_io_hit),
.io_hit_data_0_valid (_wrbypasses_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_wrbypasses_0_io_hit_data_0_bits),
.io_hit_data_1_valid (_wrbypasses_0_io_hit_data_1_valid),
.io_hit_data_1_bits (_wrbypasses_0_io_hit_data_1_bits)
);
WrBypass_33 wrbypasses_1 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1),
.io_write_idx (update_idx),
.io_write_data_0 (_GEN_1 | _GEN_2),
.io_write_data_1 (_GEN_1 | _GEN_2),
.io_write_way_mask_0
(io_update_pc[1] & updateWayMask_0 | ~(io_update_pc[1]) & updateWayMask_2),
.io_write_way_mask_1
(io_update_pc[1] & updateWayMask_1 | ~(io_update_pc[1]) & updateWayMask_3),
.io_hit (_wrbypasses_1_io_hit),
.io_hit_data_0_valid (_wrbypasses_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_wrbypasses_1_io_hit_data_0_bits),
.io_hit_data_1_valid (_wrbypasses_1_io_hit_data_1_valid),
.io_hit_data_1_bits (_wrbypasses_1_io_hit_data_1_bits)
);
assign io_resp_ctrs_0_0 =
(s1_pc[1] ? 6'h0 : _table_io_r_resp_data_0)
| (s1_pc[1] ? _table_io_r_resp_data_2 : 6'h0);
assign io_resp_ctrs_0_1 =
(s1_pc[1] ? 6'h0 : _table_io_r_resp_data_1)
| (s1_pc[1] ? _table_io_r_resp_data_3 : 6'h0);
assign io_resp_ctrs_1_0 =
(s1_pc[1] ? _table_io_r_resp_data_0 : 6'h0)
| (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_2);
assign io_resp_ctrs_1_1 =
(s1_pc[1] ? _table_io_r_resp_data_1 : 6'h0)
| (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_3);
endmodule

248
rtl/BPUTop/SCTable_3.sv
View File

@ -1,248 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module SCTable_3(
input clock,
input reset,
input io_req_valid,
input [40:0] io_req_bits_pc,
input [7:0] io_req_bits_folded_hist_hist_2_folded_hist,
output [5:0] io_resp_ctrs_0_0,
output [5:0] io_resp_ctrs_0_1,
output [5:0] io_resp_ctrs_1_0,
output [5:0] io_resp_ctrs_1_1,
input [40:0] io_update_pc,
input [7:0] io_update_folded_hist_hist_2_folded_hist,
input io_update_mask_0,
input io_update_mask_1,
input [5:0] io_update_oldCtrs_0,
input [5:0] io_update_oldCtrs_1,
input io_update_tagePreds_0,
input io_update_tagePreds_1,
input io_update_takens_0,
input io_update_takens_1
);
wire _wrbypasses_1_io_hit;
wire _wrbypasses_1_io_hit_data_0_valid;
wire [5:0] _wrbypasses_1_io_hit_data_0_bits;
wire _wrbypasses_1_io_hit_data_1_valid;
wire [5:0] _wrbypasses_1_io_hit_data_1_bits;
wire _wrbypasses_0_io_hit;
wire _wrbypasses_0_io_hit_data_0_valid;
wire [5:0] _wrbypasses_0_io_hit_data_0_bits;
wire _wrbypasses_0_io_hit_data_1_valid;
wire [5:0] _wrbypasses_0_io_hit_data_1_bits;
wire [5:0] _table_io_r_resp_data_0;
wire [5:0] _table_io_r_resp_data_1;
wire [5:0] _table_io_r_resp_data_2;
wire [5:0] _table_io_r_resp_data_3;
reg [40:0] s1_pc;
wire updateWayMask_0 =
io_update_mask_0 & ~(io_update_pc[1]) & ~io_update_tagePreds_0 | io_update_mask_1
& io_update_pc[1] & ~io_update_tagePreds_1;
wire updateWayMask_1 =
io_update_mask_0 & ~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_mask_1
& io_update_pc[1] & io_update_tagePreds_1;
wire updateWayMask_2 =
io_update_mask_0 & io_update_pc[1] & ~io_update_tagePreds_0 | io_update_mask_1
& ~(io_update_pc[1]) & ~io_update_tagePreds_1;
wire updateWayMask_3 =
io_update_mask_0 & io_update_pc[1] & io_update_tagePreds_0 | io_update_mask_1
& ~(io_update_pc[1]) & io_update_tagePreds_1;
wire [7:0] update_idx = io_update_pc[8:1] ^ io_update_folded_hist_hist_2_folded_hist;
wire ctrPos =
~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_pc[1] & io_update_tagePreds_1;
wire [5:0] oldCtr =
(~(io_update_pc[1]) & _wrbypasses_0_io_hit | io_update_pc[1] & _wrbypasses_1_io_hit)
& (ctrPos
? ~(io_update_pc[1]) & _wrbypasses_0_io_hit_data_1_valid | io_update_pc[1]
& _wrbypasses_1_io_hit_data_1_valid
: ~(io_update_pc[1]) & _wrbypasses_0_io_hit_data_0_valid | io_update_pc[1]
& _wrbypasses_1_io_hit_data_0_valid)
? (ctrPos
? (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_1_bits)
| (io_update_pc[1] ? _wrbypasses_1_io_hit_data_1_bits : 6'h0)
: (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _wrbypasses_1_io_hit_data_0_bits : 6'h0))
: (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_0)
| (io_update_pc[1] ? io_update_oldCtrs_1 : 6'h0);
wire taken =
~(io_update_pc[1]) & io_update_takens_0 | io_update_pc[1] & io_update_takens_1;
wire [5:0] update_wdata_0 =
oldCtr == 6'h1F & taken
? 6'h1F
: oldCtr == 6'h20 & ~taken ? 6'h20 : taken ? 6'(oldCtr + 6'h1) : 6'(oldCtr - 6'h1);
wire ctrPos_1 =
io_update_pc[1] & io_update_tagePreds_0 | ~(io_update_pc[1]) & io_update_tagePreds_1;
wire [5:0] oldCtr_1 =
(io_update_pc[1] & _wrbypasses_0_io_hit | ~(io_update_pc[1]) & _wrbypasses_1_io_hit)
& (ctrPos_1
? io_update_pc[1] & _wrbypasses_0_io_hit_data_1_valid | ~(io_update_pc[1])
& _wrbypasses_1_io_hit_data_1_valid
: io_update_pc[1] & _wrbypasses_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _wrbypasses_1_io_hit_data_0_valid)
? (ctrPos_1
? (io_update_pc[1] ? _wrbypasses_0_io_hit_data_1_bits : 6'h0)
| (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_1_bits)
: (io_update_pc[1] ? _wrbypasses_0_io_hit_data_0_bits : 6'h0)
| (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_0_bits))
: (io_update_pc[1] ? io_update_oldCtrs_0 : 6'h0)
| (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_1);
wire taken_1 =
io_update_pc[1] & io_update_takens_0 | ~(io_update_pc[1]) & io_update_takens_1;
wire [5:0] update_wdata_1 =
oldCtr_1 == 6'h1F & taken_1
? 6'h1F
: oldCtr_1 == 6'h20 & ~taken_1
? 6'h20
: taken_1 ? 6'(oldCtr_1 + 6'h1) : 6'(oldCtr_1 - 6'h1);
wire [5:0] _GEN = io_update_pc[1] ? 6'h0 : update_wdata_0;
wire [5:0] _GEN_0 = io_update_pc[1] ? update_wdata_1 : 6'h0;
wire [5:0] _GEN_1 = io_update_pc[1] ? update_wdata_0 : 6'h0;
wire [5:0] _GEN_2 = io_update_pc[1] ? 6'h0 : update_wdata_1;
always @(posedge clock) begin
if (io_req_valid)
s1_pc <= io_req_bits_pc;
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:1];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin
_RANDOM[i[0]] = `RANDOM;
end
s1_pc = {_RANDOM[1'h0][31:8], _RANDOM[1'h1][16:0]};
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
SRAMTemplate_35 table_0 (
.clock (clock),
.reset (reset),
.io_r_req_valid (io_req_valid),
.io_r_req_bits_setIdx
(io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_2_folded_hist),
.io_r_resp_data_0 (_table_io_r_resp_data_0),
.io_r_resp_data_1 (_table_io_r_resp_data_1),
.io_r_resp_data_2 (_table_io_r_resp_data_2),
.io_r_resp_data_3 (_table_io_r_resp_data_3),
.io_w_req_valid (io_update_mask_0 | io_update_mask_1),
.io_w_req_bits_setIdx (update_idx),
.io_w_req_bits_data_0 (update_wdata_0),
.io_w_req_bits_data_1 (update_wdata_0),
.io_w_req_bits_data_2 (update_wdata_1),
.io_w_req_bits_data_3 (update_wdata_1),
.io_w_req_bits_waymask
({updateWayMask_3, updateWayMask_2, updateWayMask_1, updateWayMask_0})
);
WrBypass_33 wrbypasses_0 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0),
.io_write_idx (update_idx),
.io_write_data_0 (_GEN | _GEN_0),
.io_write_data_1 (_GEN | _GEN_0),
.io_write_way_mask_0
(~(io_update_pc[1]) & updateWayMask_0 | io_update_pc[1] & updateWayMask_2),
.io_write_way_mask_1
(~(io_update_pc[1]) & updateWayMask_1 | io_update_pc[1] & updateWayMask_3),
.io_hit (_wrbypasses_0_io_hit),
.io_hit_data_0_valid (_wrbypasses_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_wrbypasses_0_io_hit_data_0_bits),
.io_hit_data_1_valid (_wrbypasses_0_io_hit_data_1_valid),
.io_hit_data_1_bits (_wrbypasses_0_io_hit_data_1_bits)
);
WrBypass_33 wrbypasses_1 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1),
.io_write_idx (update_idx),
.io_write_data_0 (_GEN_1 | _GEN_2),
.io_write_data_1 (_GEN_1 | _GEN_2),
.io_write_way_mask_0
(io_update_pc[1] & updateWayMask_0 | ~(io_update_pc[1]) & updateWayMask_2),
.io_write_way_mask_1
(io_update_pc[1] & updateWayMask_1 | ~(io_update_pc[1]) & updateWayMask_3),
.io_hit (_wrbypasses_1_io_hit),
.io_hit_data_0_valid (_wrbypasses_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_wrbypasses_1_io_hit_data_0_bits),
.io_hit_data_1_valid (_wrbypasses_1_io_hit_data_1_valid),
.io_hit_data_1_bits (_wrbypasses_1_io_hit_data_1_bits)
);
assign io_resp_ctrs_0_0 =
(s1_pc[1] ? 6'h0 : _table_io_r_resp_data_0)
| (s1_pc[1] ? _table_io_r_resp_data_2 : 6'h0);
assign io_resp_ctrs_0_1 =
(s1_pc[1] ? 6'h0 : _table_io_r_resp_data_1)
| (s1_pc[1] ? _table_io_r_resp_data_3 : 6'h0);
assign io_resp_ctrs_1_0 =
(s1_pc[1] ? _table_io_r_resp_data_0 : 6'h0)
| (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_2);
assign io_resp_ctrs_1_1 =
(s1_pc[1] ? _table_io_r_resp_data_1 : 6'h0)
| (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_3);
endmodule

443
rtl/BPUTop/SRAMTemplate_13.sv
View File

@ -1,443 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module SRAMTemplate_13(
input clock,
input reset,
output io_r_req_ready,
input io_r_req_valid,
input [8:0] io_r_req_bits_setIdx,
output io_r_resp_data_0_entry_valid,
output [3:0] io_r_resp_data_0_entry_brSlots_0_offset,
output [11:0] io_r_resp_data_0_entry_brSlots_0_lower,
output [1:0] io_r_resp_data_0_entry_brSlots_0_tarStat,
output io_r_resp_data_0_entry_brSlots_0_sharing,
output io_r_resp_data_0_entry_brSlots_0_valid,
output [3:0] io_r_resp_data_0_entry_tailSlot_offset,
output [19:0] io_r_resp_data_0_entry_tailSlot_lower,
output [1:0] io_r_resp_data_0_entry_tailSlot_tarStat,
output io_r_resp_data_0_entry_tailSlot_sharing,
output io_r_resp_data_0_entry_tailSlot_valid,
output [3:0] io_r_resp_data_0_entry_pftAddr,
output io_r_resp_data_0_entry_carry,
output io_r_resp_data_0_entry_isCall,
output io_r_resp_data_0_entry_isRet,
output io_r_resp_data_0_entry_isJalr,
output io_r_resp_data_0_entry_last_may_be_rvi_call,
output io_r_resp_data_0_entry_always_taken_0,
output io_r_resp_data_0_entry_always_taken_1,
output [19:0] io_r_resp_data_0_tag,
output io_r_resp_data_1_entry_valid,
output [3:0] io_r_resp_data_1_entry_brSlots_0_offset,
output [11:0] io_r_resp_data_1_entry_brSlots_0_lower,
output [1:0] io_r_resp_data_1_entry_brSlots_0_tarStat,
output io_r_resp_data_1_entry_brSlots_0_sharing,
output io_r_resp_data_1_entry_brSlots_0_valid,
output [3:0] io_r_resp_data_1_entry_tailSlot_offset,
output [19:0] io_r_resp_data_1_entry_tailSlot_lower,
output [1:0] io_r_resp_data_1_entry_tailSlot_tarStat,
output io_r_resp_data_1_entry_tailSlot_sharing,
output io_r_resp_data_1_entry_tailSlot_valid,
output [3:0] io_r_resp_data_1_entry_pftAddr,
output io_r_resp_data_1_entry_carry,
output io_r_resp_data_1_entry_isCall,
output io_r_resp_data_1_entry_isRet,
output io_r_resp_data_1_entry_isJalr,
output io_r_resp_data_1_entry_last_may_be_rvi_call,
output io_r_resp_data_1_entry_always_taken_0,
output io_r_resp_data_1_entry_always_taken_1,
output [19:0] io_r_resp_data_1_tag,
output io_r_resp_data_2_entry_valid,
output [3:0] io_r_resp_data_2_entry_brSlots_0_offset,
output [11:0] io_r_resp_data_2_entry_brSlots_0_lower,
output [1:0] io_r_resp_data_2_entry_brSlots_0_tarStat,
output io_r_resp_data_2_entry_brSlots_0_sharing,
output io_r_resp_data_2_entry_brSlots_0_valid,
output [3:0] io_r_resp_data_2_entry_tailSlot_offset,
output [19:0] io_r_resp_data_2_entry_tailSlot_lower,
output [1:0] io_r_resp_data_2_entry_tailSlot_tarStat,
output io_r_resp_data_2_entry_tailSlot_sharing,
output io_r_resp_data_2_entry_tailSlot_valid,
output [3:0] io_r_resp_data_2_entry_pftAddr,
output io_r_resp_data_2_entry_carry,
output io_r_resp_data_2_entry_isCall,
output io_r_resp_data_2_entry_isRet,
output io_r_resp_data_2_entry_isJalr,
output io_r_resp_data_2_entry_last_may_be_rvi_call,
output io_r_resp_data_2_entry_always_taken_0,
output io_r_resp_data_2_entry_always_taken_1,
output [19:0] io_r_resp_data_2_tag,
output io_r_resp_data_3_entry_valid,
output [3:0] io_r_resp_data_3_entry_brSlots_0_offset,
output [11:0] io_r_resp_data_3_entry_brSlots_0_lower,
output [1:0] io_r_resp_data_3_entry_brSlots_0_tarStat,
output io_r_resp_data_3_entry_brSlots_0_sharing,
output io_r_resp_data_3_entry_brSlots_0_valid,
output [3:0] io_r_resp_data_3_entry_tailSlot_offset,
output [19:0] io_r_resp_data_3_entry_tailSlot_lower,
output [1:0] io_r_resp_data_3_entry_tailSlot_tarStat,
output io_r_resp_data_3_entry_tailSlot_sharing,
output io_r_resp_data_3_entry_tailSlot_valid,
output [3:0] io_r_resp_data_3_entry_pftAddr,
output io_r_resp_data_3_entry_carry,
output io_r_resp_data_3_entry_isCall,
output io_r_resp_data_3_entry_isRet,
output io_r_resp_data_3_entry_isJalr,
output io_r_resp_data_3_entry_last_may_be_rvi_call,
output io_r_resp_data_3_entry_always_taken_0,
output io_r_resp_data_3_entry_always_taken_1,
output [19:0] io_r_resp_data_3_tag,
input io_w_req_valid,
input [8:0] io_w_req_bits_setIdx,
input io_w_req_bits_data_0_entry_valid,
input [3:0] io_w_req_bits_data_0_entry_brSlots_0_offset,
input [11:0] io_w_req_bits_data_0_entry_brSlots_0_lower,
input [1:0] io_w_req_bits_data_0_entry_brSlots_0_tarStat,
input io_w_req_bits_data_0_entry_brSlots_0_sharing,
input io_w_req_bits_data_0_entry_brSlots_0_valid,
input [3:0] io_w_req_bits_data_0_entry_tailSlot_offset,
input [19:0] io_w_req_bits_data_0_entry_tailSlot_lower,
input [1:0] io_w_req_bits_data_0_entry_tailSlot_tarStat,
input io_w_req_bits_data_0_entry_tailSlot_sharing,
input io_w_req_bits_data_0_entry_tailSlot_valid,
input [3:0] io_w_req_bits_data_0_entry_pftAddr,
input io_w_req_bits_data_0_entry_carry,
input io_w_req_bits_data_0_entry_isCall,
input io_w_req_bits_data_0_entry_isRet,
input io_w_req_bits_data_0_entry_isJalr,
input io_w_req_bits_data_0_entry_last_may_be_rvi_call,
input io_w_req_bits_data_0_entry_always_taken_0,
input io_w_req_bits_data_0_entry_always_taken_1,
input [19:0] io_w_req_bits_data_0_tag,
input io_w_req_bits_data_1_entry_valid,
input [3:0] io_w_req_bits_data_1_entry_brSlots_0_offset,
input [11:0] io_w_req_bits_data_1_entry_brSlots_0_lower,
input [1:0] io_w_req_bits_data_1_entry_brSlots_0_tarStat,
input io_w_req_bits_data_1_entry_brSlots_0_sharing,
input io_w_req_bits_data_1_entry_brSlots_0_valid,
input [3:0] io_w_req_bits_data_1_entry_tailSlot_offset,
input [19:0] io_w_req_bits_data_1_entry_tailSlot_lower,
input [1:0] io_w_req_bits_data_1_entry_tailSlot_tarStat,
input io_w_req_bits_data_1_entry_tailSlot_sharing,
input io_w_req_bits_data_1_entry_tailSlot_valid,
input [3:0] io_w_req_bits_data_1_entry_pftAddr,
input io_w_req_bits_data_1_entry_carry,
input io_w_req_bits_data_1_entry_isCall,
input io_w_req_bits_data_1_entry_isRet,
input io_w_req_bits_data_1_entry_isJalr,
input io_w_req_bits_data_1_entry_last_may_be_rvi_call,
input io_w_req_bits_data_1_entry_always_taken_0,
input io_w_req_bits_data_1_entry_always_taken_1,
input [19:0] io_w_req_bits_data_1_tag,
input io_w_req_bits_data_2_entry_valid,
input [3:0] io_w_req_bits_data_2_entry_brSlots_0_offset,
input [11:0] io_w_req_bits_data_2_entry_brSlots_0_lower,
input [1:0] io_w_req_bits_data_2_entry_brSlots_0_tarStat,
input io_w_req_bits_data_2_entry_brSlots_0_sharing,
input io_w_req_bits_data_2_entry_brSlots_0_valid,
input [3:0] io_w_req_bits_data_2_entry_tailSlot_offset,
input [19:0] io_w_req_bits_data_2_entry_tailSlot_lower,
input [1:0] io_w_req_bits_data_2_entry_tailSlot_tarStat,
input io_w_req_bits_data_2_entry_tailSlot_sharing,
input io_w_req_bits_data_2_entry_tailSlot_valid,
input [3:0] io_w_req_bits_data_2_entry_pftAddr,
input io_w_req_bits_data_2_entry_carry,
input io_w_req_bits_data_2_entry_isCall,
input io_w_req_bits_data_2_entry_isRet,
input io_w_req_bits_data_2_entry_isJalr,
input io_w_req_bits_data_2_entry_last_may_be_rvi_call,
input io_w_req_bits_data_2_entry_always_taken_0,
input io_w_req_bits_data_2_entry_always_taken_1,
input [19:0] io_w_req_bits_data_2_tag,
input io_w_req_bits_data_3_entry_valid,
input [3:0] io_w_req_bits_data_3_entry_brSlots_0_offset,
input [11:0] io_w_req_bits_data_3_entry_brSlots_0_lower,
input [1:0] io_w_req_bits_data_3_entry_brSlots_0_tarStat,
input io_w_req_bits_data_3_entry_brSlots_0_sharing,
input io_w_req_bits_data_3_entry_brSlots_0_valid,
input [3:0] io_w_req_bits_data_3_entry_tailSlot_offset,
input [19:0] io_w_req_bits_data_3_entry_tailSlot_lower,
input [1:0] io_w_req_bits_data_3_entry_tailSlot_tarStat,
input io_w_req_bits_data_3_entry_tailSlot_sharing,
input io_w_req_bits_data_3_entry_tailSlot_valid,
input [3:0] io_w_req_bits_data_3_entry_pftAddr,
input io_w_req_bits_data_3_entry_carry,
input io_w_req_bits_data_3_entry_isCall,
input io_w_req_bits_data_3_entry_isRet,
input io_w_req_bits_data_3_entry_isJalr,
input io_w_req_bits_data_3_entry_last_may_be_rvi_call,
input io_w_req_bits_data_3_entry_always_taken_0,
input io_w_req_bits_data_3_entry_always_taken_1,
input [19:0] io_w_req_bits_data_3_tag,
input [3:0] io_w_req_bits_waymask
);
wire [8:0] setIdx;
wire realRen;
wire wen;
wire [319:0] _array_RW0_rdata;
reg _resetState;
reg [8:0] _resetSet;
assign wen = io_w_req_valid | _resetState;
assign realRen = io_r_req_valid & ~wen;
assign setIdx = _resetState ? _resetSet : io_w_req_bits_setIdx;
always @(posedge clock or posedge reset) begin
if (reset) begin
_resetState <= 1'h1;
_resetSet <= 9'h0;
end
else begin
_resetState <= ~(_resetState & (&_resetSet)) & _resetState;
if (_resetState)
_resetSet <= 9'(_resetSet + 9'h1);
end
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
_resetState = _RANDOM[/*Zero width*/ 1'b0][0];
_resetSet = _RANDOM[/*Zero width*/ 1'b0][9:1];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
_resetState = 1'h1;
_resetSet = 9'h0;
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
array_3 array (
.RW0_addr (wen ? setIdx : io_r_req_bits_setIdx),
.RW0_en (realRen | wen),
.RW0_clk (clock),
.RW0_wmode (wen),
.RW0_wdata
({~_resetState & io_w_req_bits_data_3_entry_valid,
_resetState ? 4'h0 : io_w_req_bits_data_3_entry_brSlots_0_offset,
_resetState ? 12'h0 : io_w_req_bits_data_3_entry_brSlots_0_lower,
_resetState ? 2'h0 : io_w_req_bits_data_3_entry_brSlots_0_tarStat,
~_resetState & io_w_req_bits_data_3_entry_brSlots_0_sharing,
~_resetState & io_w_req_bits_data_3_entry_brSlots_0_valid,
_resetState ? 4'h0 : io_w_req_bits_data_3_entry_tailSlot_offset,
_resetState ? 20'h0 : io_w_req_bits_data_3_entry_tailSlot_lower,
_resetState ? 2'h0 : io_w_req_bits_data_3_entry_tailSlot_tarStat,
~_resetState & io_w_req_bits_data_3_entry_tailSlot_sharing,
~_resetState & io_w_req_bits_data_3_entry_tailSlot_valid,
_resetState ? 4'h0 : io_w_req_bits_data_3_entry_pftAddr,
~_resetState & io_w_req_bits_data_3_entry_carry,
~_resetState & io_w_req_bits_data_3_entry_isCall,
~_resetState & io_w_req_bits_data_3_entry_isRet,
~_resetState & io_w_req_bits_data_3_entry_isJalr,
~_resetState & io_w_req_bits_data_3_entry_last_may_be_rvi_call,
~_resetState & io_w_req_bits_data_3_entry_always_taken_1,
~_resetState & io_w_req_bits_data_3_entry_always_taken_0,
_resetState ? 20'h0 : io_w_req_bits_data_3_tag,
~_resetState & io_w_req_bits_data_2_entry_valid,
_resetState ? 4'h0 : io_w_req_bits_data_2_entry_brSlots_0_offset,
_resetState ? 12'h0 : io_w_req_bits_data_2_entry_brSlots_0_lower,
_resetState ? 2'h0 : io_w_req_bits_data_2_entry_brSlots_0_tarStat,
~_resetState & io_w_req_bits_data_2_entry_brSlots_0_sharing,
~_resetState & io_w_req_bits_data_2_entry_brSlots_0_valid,
_resetState ? 4'h0 : io_w_req_bits_data_2_entry_tailSlot_offset,
_resetState ? 20'h0 : io_w_req_bits_data_2_entry_tailSlot_lower,
_resetState ? 2'h0 : io_w_req_bits_data_2_entry_tailSlot_tarStat,
~_resetState & io_w_req_bits_data_2_entry_tailSlot_sharing,
~_resetState & io_w_req_bits_data_2_entry_tailSlot_valid,
_resetState ? 4'h0 : io_w_req_bits_data_2_entry_pftAddr,
~_resetState & io_w_req_bits_data_2_entry_carry,
~_resetState & io_w_req_bits_data_2_entry_isCall,
~_resetState & io_w_req_bits_data_2_entry_isRet,
~_resetState & io_w_req_bits_data_2_entry_isJalr,
~_resetState & io_w_req_bits_data_2_entry_last_may_be_rvi_call,
~_resetState & io_w_req_bits_data_2_entry_always_taken_1,
~_resetState & io_w_req_bits_data_2_entry_always_taken_0,
_resetState ? 20'h0 : io_w_req_bits_data_2_tag,
~_resetState & io_w_req_bits_data_1_entry_valid,
_resetState ? 4'h0 : io_w_req_bits_data_1_entry_brSlots_0_offset,
_resetState ? 12'h0 : io_w_req_bits_data_1_entry_brSlots_0_lower,
_resetState ? 2'h0 : io_w_req_bits_data_1_entry_brSlots_0_tarStat,
~_resetState & io_w_req_bits_data_1_entry_brSlots_0_sharing,
~_resetState & io_w_req_bits_data_1_entry_brSlots_0_valid,
_resetState ? 4'h0 : io_w_req_bits_data_1_entry_tailSlot_offset,
_resetState ? 20'h0 : io_w_req_bits_data_1_entry_tailSlot_lower,
_resetState ? 2'h0 : io_w_req_bits_data_1_entry_tailSlot_tarStat,
~_resetState & io_w_req_bits_data_1_entry_tailSlot_sharing,
~_resetState & io_w_req_bits_data_1_entry_tailSlot_valid,
_resetState ? 4'h0 : io_w_req_bits_data_1_entry_pftAddr,
~_resetState & io_w_req_bits_data_1_entry_carry,
~_resetState & io_w_req_bits_data_1_entry_isCall,
~_resetState & io_w_req_bits_data_1_entry_isRet,
~_resetState & io_w_req_bits_data_1_entry_isJalr,
~_resetState & io_w_req_bits_data_1_entry_last_may_be_rvi_call,
~_resetState & io_w_req_bits_data_1_entry_always_taken_1,
~_resetState & io_w_req_bits_data_1_entry_always_taken_0,
_resetState ? 20'h0 : io_w_req_bits_data_1_tag,
~_resetState & io_w_req_bits_data_0_entry_valid,
_resetState ? 4'h0 : io_w_req_bits_data_0_entry_brSlots_0_offset,
_resetState ? 12'h0 : io_w_req_bits_data_0_entry_brSlots_0_lower,
_resetState ? 2'h0 : io_w_req_bits_data_0_entry_brSlots_0_tarStat,
~_resetState & io_w_req_bits_data_0_entry_brSlots_0_sharing,
~_resetState & io_w_req_bits_data_0_entry_brSlots_0_valid,
_resetState ? 4'h0 : io_w_req_bits_data_0_entry_tailSlot_offset,
_resetState ? 20'h0 : io_w_req_bits_data_0_entry_tailSlot_lower,
_resetState ? 2'h0 : io_w_req_bits_data_0_entry_tailSlot_tarStat,
~_resetState & io_w_req_bits_data_0_entry_tailSlot_sharing,
~_resetState & io_w_req_bits_data_0_entry_tailSlot_valid,
_resetState ? 4'h0 : io_w_req_bits_data_0_entry_pftAddr,
~_resetState & io_w_req_bits_data_0_entry_carry,
~_resetState & io_w_req_bits_data_0_entry_isCall,
~_resetState & io_w_req_bits_data_0_entry_isRet,
~_resetState & io_w_req_bits_data_0_entry_isJalr,
~_resetState & io_w_req_bits_data_0_entry_last_may_be_rvi_call,
~_resetState & io_w_req_bits_data_0_entry_always_taken_1,
~_resetState & io_w_req_bits_data_0_entry_always_taken_0,
_resetState ? 20'h0 : io_w_req_bits_data_0_tag}),
.RW0_rdata (_array_RW0_rdata),
.RW0_wmask (_resetState ? 4'hF : io_w_req_bits_waymask)
);
assign io_r_req_ready = ~_resetState & ~wen;
assign io_r_resp_data_0_entry_valid = _array_RW0_rdata[79];
assign io_r_resp_data_0_entry_brSlots_0_offset = _array_RW0_rdata[78:75];
assign io_r_resp_data_0_entry_brSlots_0_lower = _array_RW0_rdata[74:63];
assign io_r_resp_data_0_entry_brSlots_0_tarStat = _array_RW0_rdata[62:61];
assign io_r_resp_data_0_entry_brSlots_0_sharing = _array_RW0_rdata[60];
assign io_r_resp_data_0_entry_brSlots_0_valid = _array_RW0_rdata[59];
assign io_r_resp_data_0_entry_tailSlot_offset = _array_RW0_rdata[58:55];
assign io_r_resp_data_0_entry_tailSlot_lower = _array_RW0_rdata[54:35];
assign io_r_resp_data_0_entry_tailSlot_tarStat = _array_RW0_rdata[34:33];
assign io_r_resp_data_0_entry_tailSlot_sharing = _array_RW0_rdata[32];
assign io_r_resp_data_0_entry_tailSlot_valid = _array_RW0_rdata[31];
assign io_r_resp_data_0_entry_pftAddr = _array_RW0_rdata[30:27];
assign io_r_resp_data_0_entry_carry = _array_RW0_rdata[26];
assign io_r_resp_data_0_entry_isCall = _array_RW0_rdata[25];
assign io_r_resp_data_0_entry_isRet = _array_RW0_rdata[24];
assign io_r_resp_data_0_entry_isJalr = _array_RW0_rdata[23];
assign io_r_resp_data_0_entry_last_may_be_rvi_call = _array_RW0_rdata[22];
assign io_r_resp_data_0_entry_always_taken_0 = _array_RW0_rdata[20];
assign io_r_resp_data_0_entry_always_taken_1 = _array_RW0_rdata[21];
assign io_r_resp_data_0_tag = _array_RW0_rdata[19:0];
assign io_r_resp_data_1_entry_valid = _array_RW0_rdata[159];
assign io_r_resp_data_1_entry_brSlots_0_offset = _array_RW0_rdata[158:155];
assign io_r_resp_data_1_entry_brSlots_0_lower = _array_RW0_rdata[154:143];
assign io_r_resp_data_1_entry_brSlots_0_tarStat = _array_RW0_rdata[142:141];
assign io_r_resp_data_1_entry_brSlots_0_sharing = _array_RW0_rdata[140];
assign io_r_resp_data_1_entry_brSlots_0_valid = _array_RW0_rdata[139];
assign io_r_resp_data_1_entry_tailSlot_offset = _array_RW0_rdata[138:135];
assign io_r_resp_data_1_entry_tailSlot_lower = _array_RW0_rdata[134:115];
assign io_r_resp_data_1_entry_tailSlot_tarStat = _array_RW0_rdata[114:113];
assign io_r_resp_data_1_entry_tailSlot_sharing = _array_RW0_rdata[112];
assign io_r_resp_data_1_entry_tailSlot_valid = _array_RW0_rdata[111];
assign io_r_resp_data_1_entry_pftAddr = _array_RW0_rdata[110:107];
assign io_r_resp_data_1_entry_carry = _array_RW0_rdata[106];
assign io_r_resp_data_1_entry_isCall = _array_RW0_rdata[105];
assign io_r_resp_data_1_entry_isRet = _array_RW0_rdata[104];
assign io_r_resp_data_1_entry_isJalr = _array_RW0_rdata[103];
assign io_r_resp_data_1_entry_last_may_be_rvi_call = _array_RW0_rdata[102];
assign io_r_resp_data_1_entry_always_taken_0 = _array_RW0_rdata[100];
assign io_r_resp_data_1_entry_always_taken_1 = _array_RW0_rdata[101];
assign io_r_resp_data_1_tag = _array_RW0_rdata[99:80];
assign io_r_resp_data_2_entry_valid = _array_RW0_rdata[239];
assign io_r_resp_data_2_entry_brSlots_0_offset = _array_RW0_rdata[238:235];
assign io_r_resp_data_2_entry_brSlots_0_lower = _array_RW0_rdata[234:223];
assign io_r_resp_data_2_entry_brSlots_0_tarStat = _array_RW0_rdata[222:221];
assign io_r_resp_data_2_entry_brSlots_0_sharing = _array_RW0_rdata[220];
assign io_r_resp_data_2_entry_brSlots_0_valid = _array_RW0_rdata[219];
assign io_r_resp_data_2_entry_tailSlot_offset = _array_RW0_rdata[218:215];
assign io_r_resp_data_2_entry_tailSlot_lower = _array_RW0_rdata[214:195];
assign io_r_resp_data_2_entry_tailSlot_tarStat = _array_RW0_rdata[194:193];
assign io_r_resp_data_2_entry_tailSlot_sharing = _array_RW0_rdata[192];
assign io_r_resp_data_2_entry_tailSlot_valid = _array_RW0_rdata[191];
assign io_r_resp_data_2_entry_pftAddr = _array_RW0_rdata[190:187];
assign io_r_resp_data_2_entry_carry = _array_RW0_rdata[186];
assign io_r_resp_data_2_entry_isCall = _array_RW0_rdata[185];
assign io_r_resp_data_2_entry_isRet = _array_RW0_rdata[184];
assign io_r_resp_data_2_entry_isJalr = _array_RW0_rdata[183];
assign io_r_resp_data_2_entry_last_may_be_rvi_call = _array_RW0_rdata[182];
assign io_r_resp_data_2_entry_always_taken_0 = _array_RW0_rdata[180];
assign io_r_resp_data_2_entry_always_taken_1 = _array_RW0_rdata[181];
assign io_r_resp_data_2_tag = _array_RW0_rdata[179:160];
assign io_r_resp_data_3_entry_valid = _array_RW0_rdata[319];
assign io_r_resp_data_3_entry_brSlots_0_offset = _array_RW0_rdata[318:315];
assign io_r_resp_data_3_entry_brSlots_0_lower = _array_RW0_rdata[314:303];
assign io_r_resp_data_3_entry_brSlots_0_tarStat = _array_RW0_rdata[302:301];
assign io_r_resp_data_3_entry_brSlots_0_sharing = _array_RW0_rdata[300];
assign io_r_resp_data_3_entry_brSlots_0_valid = _array_RW0_rdata[299];
assign io_r_resp_data_3_entry_tailSlot_offset = _array_RW0_rdata[298:295];
assign io_r_resp_data_3_entry_tailSlot_lower = _array_RW0_rdata[294:275];
assign io_r_resp_data_3_entry_tailSlot_tarStat = _array_RW0_rdata[274:273];
assign io_r_resp_data_3_entry_tailSlot_sharing = _array_RW0_rdata[272];
assign io_r_resp_data_3_entry_tailSlot_valid = _array_RW0_rdata[271];
assign io_r_resp_data_3_entry_pftAddr = _array_RW0_rdata[270:267];
assign io_r_resp_data_3_entry_carry = _array_RW0_rdata[266];
assign io_r_resp_data_3_entry_isCall = _array_RW0_rdata[265];
assign io_r_resp_data_3_entry_isRet = _array_RW0_rdata[264];
assign io_r_resp_data_3_entry_isJalr = _array_RW0_rdata[263];
assign io_r_resp_data_3_entry_last_may_be_rvi_call = _array_RW0_rdata[262];
assign io_r_resp_data_3_entry_always_taken_0 = _array_RW0_rdata[260];
assign io_r_resp_data_3_entry_always_taken_1 = _array_RW0_rdata[261];
assign io_r_resp_data_3_tag = _array_RW0_rdata[259:240];
endmodule

248
rtl/BPUTop/SRAMTemplate_14.sv
View File

@ -1,248 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module SRAMTemplate_14(
input clock,
input reset,
output io_r_req_ready,
input io_r_req_valid,
input [7:0] io_r_req_bits_setIdx,
output io_r_resp_data_0,
output io_r_resp_data_1,
output io_r_resp_data_2,
output io_r_resp_data_3,
output io_r_resp_data_4,
output io_r_resp_data_5,
output io_r_resp_data_6,
output io_r_resp_data_7,
output io_r_resp_data_8,
output io_r_resp_data_9,
output io_r_resp_data_10,
output io_r_resp_data_11,
output io_r_resp_data_12,
output io_r_resp_data_13,
output io_r_resp_data_14,
output io_r_resp_data_15,
input io_w_req_valid,
input [7:0] io_w_req_bits_setIdx,
input io_w_req_bits_data_0,
input io_w_req_bits_data_1,
input io_w_req_bits_data_2,
input io_w_req_bits_data_3,
input io_w_req_bits_data_4,
input io_w_req_bits_data_5,
input io_w_req_bits_data_6,
input io_w_req_bits_data_7,
input io_w_req_bits_data_8,
input io_w_req_bits_data_9,
input io_w_req_bits_data_10,
input io_w_req_bits_data_11,
input io_w_req_bits_data_12,
input io_w_req_bits_data_13,
input io_w_req_bits_data_14,
input io_w_req_bits_data_15,
input [15:0] io_w_req_bits_waymask,
input extra_reset
);
wire [7:0] setIdx;
wire realRen;
wire wen;
wire [15:0] _array_RW0_rdata;
reg _resetState;
reg [7:0] _resetSet;
assign wen = io_w_req_valid | _resetState;
assign realRen = io_r_req_valid & ~wen;
assign setIdx = _resetState ? _resetSet : io_w_req_bits_setIdx;
reg rdata_last_r;
reg rdata_hold_data_0;
reg rdata_hold_data_1;
reg rdata_hold_data_2;
reg rdata_hold_data_3;
reg rdata_hold_data_4;
reg rdata_hold_data_5;
reg rdata_hold_data_6;
reg rdata_hold_data_7;
reg rdata_hold_data_8;
reg rdata_hold_data_9;
reg rdata_hold_data_10;
reg rdata_hold_data_11;
reg rdata_hold_data_12;
reg rdata_hold_data_13;
reg rdata_hold_data_14;
reg rdata_hold_data_15;
always @(posedge clock or posedge reset) begin
if (reset) begin
_resetState <= 1'h1;
_resetSet <= 8'h0;
rdata_last_r <= 1'h0;
end
else begin
_resetState <= extra_reset | ~(_resetState & (&_resetSet)) & _resetState;
if (_resetState)
_resetSet <= 8'(_resetSet + 8'h1);
if (realRen | rdata_last_r)
rdata_last_r <= realRen;
end
end // always @(posedge, posedge)
always @(posedge clock) begin
if (rdata_last_r) begin
rdata_hold_data_0 <= _array_RW0_rdata[0];
rdata_hold_data_1 <= _array_RW0_rdata[1];
rdata_hold_data_2 <= _array_RW0_rdata[2];
rdata_hold_data_3 <= _array_RW0_rdata[3];
rdata_hold_data_4 <= _array_RW0_rdata[4];
rdata_hold_data_5 <= _array_RW0_rdata[5];
rdata_hold_data_6 <= _array_RW0_rdata[6];
rdata_hold_data_7 <= _array_RW0_rdata[7];
rdata_hold_data_8 <= _array_RW0_rdata[8];
rdata_hold_data_9 <= _array_RW0_rdata[9];
rdata_hold_data_10 <= _array_RW0_rdata[10];
rdata_hold_data_11 <= _array_RW0_rdata[11];
rdata_hold_data_12 <= _array_RW0_rdata[12];
rdata_hold_data_13 <= _array_RW0_rdata[13];
rdata_hold_data_14 <= _array_RW0_rdata[14];
rdata_hold_data_15 <= _array_RW0_rdata[15];
end
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:33];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
for (logic [5:0] i = 6'h0; i < 6'h22; i += 6'h1) begin
_RANDOM[i] = `RANDOM;
end
_resetState = _RANDOM[6'h0][0];
_resetSet = _RANDOM[6'h0][8:1];
rdata_last_r = _RANDOM[6'h21][10];
rdata_hold_data_0 = _RANDOM[6'h21][11];
rdata_hold_data_1 = _RANDOM[6'h21][12];
rdata_hold_data_2 = _RANDOM[6'h21][13];
rdata_hold_data_3 = _RANDOM[6'h21][14];
rdata_hold_data_4 = _RANDOM[6'h21][15];
rdata_hold_data_5 = _RANDOM[6'h21][16];
rdata_hold_data_6 = _RANDOM[6'h21][17];
rdata_hold_data_7 = _RANDOM[6'h21][18];
rdata_hold_data_8 = _RANDOM[6'h21][19];
rdata_hold_data_9 = _RANDOM[6'h21][20];
rdata_hold_data_10 = _RANDOM[6'h21][21];
rdata_hold_data_11 = _RANDOM[6'h21][22];
rdata_hold_data_12 = _RANDOM[6'h21][23];
rdata_hold_data_13 = _RANDOM[6'h21][24];
rdata_hold_data_14 = _RANDOM[6'h21][25];
rdata_hold_data_15 = _RANDOM[6'h21][26];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
_resetState = 1'h1;
_resetSet = 8'h0;
rdata_last_r = 1'h0;
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
array_4 array (
.RW0_addr (wen ? setIdx : io_r_req_bits_setIdx),
.RW0_en (realRen | wen),
.RW0_clk (clock),
.RW0_wmode (wen),
.RW0_wdata
({~_resetState & io_w_req_bits_data_15,
~_resetState & io_w_req_bits_data_14,
~_resetState & io_w_req_bits_data_13,
~_resetState & io_w_req_bits_data_12,
~_resetState & io_w_req_bits_data_11,
~_resetState & io_w_req_bits_data_10,
~_resetState & io_w_req_bits_data_9,
~_resetState & io_w_req_bits_data_8,
~_resetState & io_w_req_bits_data_7,
~_resetState & io_w_req_bits_data_6,
~_resetState & io_w_req_bits_data_5,
~_resetState & io_w_req_bits_data_4,
~_resetState & io_w_req_bits_data_3,
~_resetState & io_w_req_bits_data_2,
~_resetState & io_w_req_bits_data_1,
~_resetState & io_w_req_bits_data_0}),
.RW0_rdata (_array_RW0_rdata),
.RW0_wmask (_resetState ? 16'hFFFF : io_w_req_bits_waymask)
);
assign io_r_req_ready = ~_resetState & ~wen;
assign io_r_resp_data_0 = rdata_last_r ? _array_RW0_rdata[0] : rdata_hold_data_0;
assign io_r_resp_data_1 = rdata_last_r ? _array_RW0_rdata[1] : rdata_hold_data_1;
assign io_r_resp_data_2 = rdata_last_r ? _array_RW0_rdata[2] : rdata_hold_data_2;
assign io_r_resp_data_3 = rdata_last_r ? _array_RW0_rdata[3] : rdata_hold_data_3;
assign io_r_resp_data_4 = rdata_last_r ? _array_RW0_rdata[4] : rdata_hold_data_4;
assign io_r_resp_data_5 = rdata_last_r ? _array_RW0_rdata[5] : rdata_hold_data_5;
assign io_r_resp_data_6 = rdata_last_r ? _array_RW0_rdata[6] : rdata_hold_data_6;
assign io_r_resp_data_7 = rdata_last_r ? _array_RW0_rdata[7] : rdata_hold_data_7;
assign io_r_resp_data_8 = rdata_last_r ? _array_RW0_rdata[8] : rdata_hold_data_8;
assign io_r_resp_data_9 = rdata_last_r ? _array_RW0_rdata[9] : rdata_hold_data_9;
assign io_r_resp_data_10 = rdata_last_r ? _array_RW0_rdata[10] : rdata_hold_data_10;
assign io_r_resp_data_11 = rdata_last_r ? _array_RW0_rdata[11] : rdata_hold_data_11;
assign io_r_resp_data_12 = rdata_last_r ? _array_RW0_rdata[12] : rdata_hold_data_12;
assign io_r_resp_data_13 = rdata_last_r ? _array_RW0_rdata[13] : rdata_hold_data_13;
assign io_r_resp_data_14 = rdata_last_r ? _array_RW0_rdata[14] : rdata_hold_data_14;
assign io_r_resp_data_15 = rdata_last_r ? _array_RW0_rdata[15] : rdata_hold_data_15;
endmodule

165
rtl/BPUTop/SRAMTemplate_15.sv
View File

@ -1,165 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module SRAMTemplate_15(
input clock,
input reset,
output io_r_req_ready,
input io_r_req_valid,
input [8:0] io_r_req_bits_setIdx,
output io_r_resp_data_0_valid,
output [7:0] io_r_resp_data_0_tag,
output [2:0] io_r_resp_data_0_ctr,
output io_r_resp_data_1_valid,
output [7:0] io_r_resp_data_1_tag,
output [2:0] io_r_resp_data_1_ctr,
input io_w_req_valid,
input [8:0] io_w_req_bits_setIdx,
input [7:0] io_w_req_bits_data_0_tag,
input [2:0] io_w_req_bits_data_0_ctr,
input [7:0] io_w_req_bits_data_1_tag,
input [2:0] io_w_req_bits_data_1_ctr,
input [1:0] io_w_req_bits_waymask
);
wire [8:0] setIdx;
wire realRen;
wire wen;
wire [23:0] _array_RW0_rdata;
reg _resetState;
reg [8:0] _resetSet;
assign wen = io_w_req_valid | _resetState;
assign realRen = io_r_req_valid & ~wen;
assign setIdx = _resetState ? _resetSet : io_w_req_bits_setIdx;
reg rdata_last_r;
reg [11:0] rdata_hold_data_0;
reg [11:0] rdata_hold_data_1;
wire [11:0] _rdata_T_0 = rdata_last_r ? _array_RW0_rdata[11:0] : rdata_hold_data_0;
wire [11:0] _rdata_T_1 = rdata_last_r ? _array_RW0_rdata[23:12] : rdata_hold_data_1;
always @(posedge clock or posedge reset) begin
if (reset) begin
_resetState <= 1'h1;
_resetSet <= 9'h0;
rdata_last_r <= 1'h0;
end
else begin
_resetState <= ~(_resetState & (&_resetSet)) & _resetState;
if (_resetState)
_resetSet <= 9'(_resetSet + 9'h1);
if (realRen | rdata_last_r)
rdata_last_r <= realRen;
end
end // always @(posedge, posedge)
always @(posedge clock) begin
if (rdata_last_r) begin
rdata_hold_data_0 <= _array_RW0_rdata[11:0];
rdata_hold_data_1 <= _array_RW0_rdata[23:12];
end
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:5];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
for (logic [2:0] i = 3'h0; i < 3'h6; i += 3'h1) begin
_RANDOM[i] = `RANDOM;
end
_resetState = _RANDOM[3'h0][0];
_resetSet = _RANDOM[3'h0][9:1];
rdata_last_r = _RANDOM[3'h4][31];
rdata_hold_data_0 = _RANDOM[3'h5][11:0];
rdata_hold_data_1 = _RANDOM[3'h5][23:12];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
_resetState = 1'h1;
_resetSet = 9'h0;
rdata_last_r = 1'h0;
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
array_5 array (
.RW0_addr (wen ? setIdx : io_r_req_bits_setIdx),
.RW0_en (realRen | wen),
.RW0_clk (clock),
.RW0_wmode (wen),
.RW0_wdata
({~_resetState,
_resetState ? 8'h0 : io_w_req_bits_data_1_tag,
_resetState ? 3'h0 : io_w_req_bits_data_1_ctr,
~_resetState,
_resetState ? 8'h0 : io_w_req_bits_data_0_tag,
_resetState ? 3'h0 : io_w_req_bits_data_0_ctr}),
.RW0_rdata (_array_RW0_rdata),
.RW0_wmask (_resetState ? 2'h3 : io_w_req_bits_waymask)
);
assign io_r_req_ready = ~_resetState & ~wen;
assign io_r_resp_data_0_valid = _rdata_T_0[11];
assign io_r_resp_data_0_tag = _rdata_T_0[10:3];
assign io_r_resp_data_0_ctr = _rdata_T_0[2:0];
assign io_r_resp_data_1_valid = _rdata_T_1[11];
assign io_r_resp_data_1_tag = _rdata_T_1[10:3];
assign io_r_resp_data_1_ctr = _rdata_T_1[2:0];
endmodule

229
rtl/BPUTop/SRAMTemplate_34.sv
View File

@ -1,229 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module SRAMTemplate_34(
input clock,
input reset,
input io_r_req_valid,
input [8:0] io_r_req_bits_setIdx,
output [1:0] io_r_resp_data_0,
output [1:0] io_r_resp_data_1,
output [1:0] io_r_resp_data_2,
output [1:0] io_r_resp_data_3,
output [1:0] io_r_resp_data_4,
output [1:0] io_r_resp_data_5,
output [1:0] io_r_resp_data_6,
output [1:0] io_r_resp_data_7,
input io_w_req_valid,
input [8:0] io_w_req_bits_setIdx,
input [1:0] io_w_req_bits_data_0,
input [1:0] io_w_req_bits_data_1,
input [1:0] io_w_req_bits_data_2,
input [1:0] io_w_req_bits_data_3,
input [1:0] io_w_req_bits_data_4,
input [1:0] io_w_req_bits_data_5,
input [1:0] io_w_req_bits_data_6,
input [1:0] io_w_req_bits_data_7,
input [7:0] io_w_req_bits_waymask
);
wire [15:0] _array_R0_data;
reg [1:0] bypass_wdata_r_0;
reg [1:0] bypass_wdata_r_1;
reg [1:0] bypass_wdata_r_2;
reg [1:0] bypass_wdata_r_3;
reg [1:0] bypass_wdata_r_4;
reg [1:0] bypass_wdata_r_5;
reg [1:0] bypass_wdata_r_6;
reg [1:0] bypass_wdata_r_7;
wire bypass_mask_need_check = io_r_req_valid & io_w_req_valid;
reg bypass_mask_need_check_reg_last_r;
reg [8:0] bypass_mask_waddr_reg;
reg [8:0] bypass_mask_raddr_reg;
reg [7:0] bypass_mask_wmask_reg;
wire [7:0] bypass_mask =
{8{bypass_mask_need_check_reg_last_r
& bypass_mask_waddr_reg == bypass_mask_raddr_reg}} & bypass_mask_wmask_reg;
wire [1:0] mem_rdata_0 = bypass_mask[0] ? bypass_wdata_r_0 : _array_R0_data[1:0];
wire [1:0] mem_rdata_1 = bypass_mask[1] ? bypass_wdata_r_1 : _array_R0_data[3:2];
wire [1:0] mem_rdata_2 = bypass_mask[2] ? bypass_wdata_r_2 : _array_R0_data[5:4];
wire [1:0] mem_rdata_3 = bypass_mask[3] ? bypass_wdata_r_3 : _array_R0_data[7:6];
wire [1:0] mem_rdata_4 = bypass_mask[4] ? bypass_wdata_r_4 : _array_R0_data[9:8];
wire [1:0] mem_rdata_5 = bypass_mask[5] ? bypass_wdata_r_5 : _array_R0_data[11:10];
wire [1:0] mem_rdata_6 = bypass_mask[6] ? bypass_wdata_r_6 : _array_R0_data[13:12];
wire [1:0] mem_rdata_7 = bypass_mask[7] ? bypass_wdata_r_7 : _array_R0_data[15:14];
reg rdata_last_r;
reg [1:0] rdata_hold_data_0;
reg [1:0] rdata_hold_data_1;
reg [1:0] rdata_hold_data_2;
reg [1:0] rdata_hold_data_3;
reg [1:0] rdata_hold_data_4;
reg [1:0] rdata_hold_data_5;
reg [1:0] rdata_hold_data_6;
reg [1:0] rdata_hold_data_7;
always @(posedge clock) begin
if (io_w_req_valid & io_r_req_valid) begin
bypass_wdata_r_0 <= io_w_req_bits_data_0;
bypass_wdata_r_1 <= io_w_req_bits_data_1;
bypass_wdata_r_2 <= io_w_req_bits_data_2;
bypass_wdata_r_3 <= io_w_req_bits_data_3;
bypass_wdata_r_4 <= io_w_req_bits_data_4;
bypass_wdata_r_5 <= io_w_req_bits_data_5;
bypass_wdata_r_6 <= io_w_req_bits_data_6;
bypass_wdata_r_7 <= io_w_req_bits_data_7;
end
if (bypass_mask_need_check) begin
bypass_mask_waddr_reg <= io_w_req_bits_setIdx;
bypass_mask_raddr_reg <= io_r_req_bits_setIdx;
bypass_mask_wmask_reg <= io_w_req_bits_waymask;
end
if (rdata_last_r) begin
rdata_hold_data_0 <= mem_rdata_0;
rdata_hold_data_1 <= mem_rdata_1;
rdata_hold_data_2 <= mem_rdata_2;
rdata_hold_data_3 <= mem_rdata_3;
rdata_hold_data_4 <= mem_rdata_4;
rdata_hold_data_5 <= mem_rdata_5;
rdata_hold_data_6 <= mem_rdata_6;
rdata_hold_data_7 <= mem_rdata_7;
end
end // always @(posedge)
always @(posedge clock or posedge reset) begin
if (reset) begin
bypass_mask_need_check_reg_last_r <= 1'h0;
rdata_last_r <= 1'h0;
end
else begin
if (bypass_mask_need_check | bypass_mask_need_check_reg_last_r)
bypass_mask_need_check_reg_last_r <= bypass_mask_need_check;
if (io_r_req_valid | rdata_last_r)
rdata_last_r <= io_r_req_valid;
end
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:1];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin
_RANDOM[i[0]] = `RANDOM;
end
bypass_wdata_r_0 = _RANDOM[1'h0][1:0];
bypass_wdata_r_1 = _RANDOM[1'h0][3:2];
bypass_wdata_r_2 = _RANDOM[1'h0][5:4];
bypass_wdata_r_3 = _RANDOM[1'h0][7:6];
bypass_wdata_r_4 = _RANDOM[1'h0][9:8];
bypass_wdata_r_5 = _RANDOM[1'h0][11:10];
bypass_wdata_r_6 = _RANDOM[1'h0][13:12];
bypass_wdata_r_7 = _RANDOM[1'h0][15:14];
bypass_mask_need_check_reg_last_r = _RANDOM[1'h0][16];
bypass_mask_waddr_reg = _RANDOM[1'h0][25:17];
bypass_mask_raddr_reg = {_RANDOM[1'h0][31:26], _RANDOM[1'h1][2:0]};
bypass_mask_wmask_reg = _RANDOM[1'h1][10:3];
rdata_last_r = _RANDOM[1'h1][11];
rdata_hold_data_0 = _RANDOM[1'h1][13:12];
rdata_hold_data_1 = _RANDOM[1'h1][15:14];
rdata_hold_data_2 = _RANDOM[1'h1][17:16];
rdata_hold_data_3 = _RANDOM[1'h1][19:18];
rdata_hold_data_4 = _RANDOM[1'h1][21:20];
rdata_hold_data_5 = _RANDOM[1'h1][23:22];
rdata_hold_data_6 = _RANDOM[1'h1][25:24];
rdata_hold_data_7 = _RANDOM[1'h1][27:26];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
bypass_mask_need_check_reg_last_r = 1'h0;
rdata_last_r = 1'h0;
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
array_6 array (
.R0_addr (io_r_req_bits_setIdx),
.R0_en (io_r_req_valid),
.R0_clk (clock),
.R0_data (_array_R0_data),
.W0_addr (io_w_req_bits_setIdx),
.W0_en (io_w_req_valid),
.W0_clk (clock),
.W0_data
({io_w_req_bits_data_7,
io_w_req_bits_data_6,
io_w_req_bits_data_5,
io_w_req_bits_data_4,
io_w_req_bits_data_3,
io_w_req_bits_data_2,
io_w_req_bits_data_1,
io_w_req_bits_data_0}),
.W0_mask (io_w_req_bits_waymask)
);
assign io_r_resp_data_0 = rdata_last_r ? mem_rdata_0 : rdata_hold_data_0;
assign io_r_resp_data_1 = rdata_last_r ? mem_rdata_1 : rdata_hold_data_1;
assign io_r_resp_data_2 = rdata_last_r ? mem_rdata_2 : rdata_hold_data_2;
assign io_r_resp_data_3 = rdata_last_r ? mem_rdata_3 : rdata_hold_data_3;
assign io_r_resp_data_4 = rdata_last_r ? mem_rdata_4 : rdata_hold_data_4;
assign io_r_resp_data_5 = rdata_last_r ? mem_rdata_5 : rdata_hold_data_5;
assign io_r_resp_data_6 = rdata_last_r ? mem_rdata_6 : rdata_hold_data_6;
assign io_r_resp_data_7 = rdata_last_r ? mem_rdata_7 : rdata_hold_data_7;
endmodule

196
rtl/BPUTop/SRAMTemplate_35.sv
View File

@ -1,196 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module SRAMTemplate_35(
input clock,
input reset,
input io_r_req_valid,
input [7:0] io_r_req_bits_setIdx,
output [5:0] io_r_resp_data_0,
output [5:0] io_r_resp_data_1,
output [5:0] io_r_resp_data_2,
output [5:0] io_r_resp_data_3,
input io_w_req_valid,
input [7:0] io_w_req_bits_setIdx,
input [5:0] io_w_req_bits_data_0,
input [5:0] io_w_req_bits_data_1,
input [5:0] io_w_req_bits_data_2,
input [5:0] io_w_req_bits_data_3,
input [3:0] io_w_req_bits_waymask
);
wire [23:0] _array_R0_data;
reg _resetState;
reg [7:0] _resetSet;
reg [5:0] bypass_wdata_r_0;
reg [5:0] bypass_wdata_r_1;
reg [5:0] bypass_wdata_r_2;
reg [5:0] bypass_wdata_r_3;
wire bypass_mask_need_check = io_r_req_valid & io_w_req_valid;
reg bypass_mask_need_check_reg_last_r;
reg [7:0] bypass_mask_waddr_reg;
reg [7:0] bypass_mask_raddr_reg;
reg [3:0] bypass_mask_wmask_reg;
wire [3:0] bypass_mask =
{4{bypass_mask_need_check_reg_last_r
& bypass_mask_waddr_reg == bypass_mask_raddr_reg}} & bypass_mask_wmask_reg;
wire [5:0] mem_rdata_0 = bypass_mask[0] ? bypass_wdata_r_0 : _array_R0_data[5:0];
wire [5:0] mem_rdata_1 = bypass_mask[1] ? bypass_wdata_r_1 : _array_R0_data[11:6];
wire [5:0] mem_rdata_2 = bypass_mask[2] ? bypass_wdata_r_2 : _array_R0_data[17:12];
wire [5:0] mem_rdata_3 = bypass_mask[3] ? bypass_wdata_r_3 : _array_R0_data[23:18];
reg rdata_last_r;
reg [5:0] rdata_hold_data_0;
reg [5:0] rdata_hold_data_1;
reg [5:0] rdata_hold_data_2;
reg [5:0] rdata_hold_data_3;
always @(posedge clock or posedge reset) begin
if (reset) begin
_resetState <= 1'h1;
_resetSet <= 8'h0;
bypass_mask_need_check_reg_last_r <= 1'h0;
rdata_last_r <= 1'h0;
end
else begin
_resetState <= ~(_resetState & (&_resetSet)) & _resetState;
if (_resetState)
_resetSet <= 8'(_resetSet + 8'h1);
if (bypass_mask_need_check | bypass_mask_need_check_reg_last_r)
bypass_mask_need_check_reg_last_r <= bypass_mask_need_check;
if (io_r_req_valid | rdata_last_r)
rdata_last_r <= io_r_req_valid;
end
end // always @(posedge, posedge)
always @(posedge clock) begin
if (io_w_req_valid & io_r_req_valid) begin
bypass_wdata_r_0 <= io_w_req_bits_data_0;
bypass_wdata_r_1 <= io_w_req_bits_data_1;
bypass_wdata_r_2 <= io_w_req_bits_data_2;
bypass_wdata_r_3 <= io_w_req_bits_data_3;
end
if (bypass_mask_need_check) begin
bypass_mask_waddr_reg <= io_w_req_bits_setIdx;
bypass_mask_raddr_reg <= io_r_req_bits_setIdx;
bypass_mask_wmask_reg <= io_w_req_bits_waymask;
end
if (rdata_last_r) begin
rdata_hold_data_0 <= mem_rdata_0;
rdata_hold_data_1 <= mem_rdata_1;
rdata_hold_data_2 <= mem_rdata_2;
rdata_hold_data_3 <= mem_rdata_3;
end
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:2];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
for (logic [1:0] i = 2'h0; i < 2'h3; i += 2'h1) begin
_RANDOM[i] = `RANDOM;
end
_resetState = _RANDOM[2'h0][0];
_resetSet = _RANDOM[2'h0][8:1];
bypass_wdata_r_0 = _RANDOM[2'h0][14:9];
bypass_wdata_r_1 = _RANDOM[2'h0][20:15];
bypass_wdata_r_2 = _RANDOM[2'h0][26:21];
bypass_wdata_r_3 = {_RANDOM[2'h0][31:27], _RANDOM[2'h1][0]};
bypass_mask_need_check_reg_last_r = _RANDOM[2'h1][1];
bypass_mask_waddr_reg = _RANDOM[2'h1][9:2];
bypass_mask_raddr_reg = _RANDOM[2'h1][17:10];
bypass_mask_wmask_reg = _RANDOM[2'h1][21:18];
rdata_last_r = _RANDOM[2'h1][22];
rdata_hold_data_0 = _RANDOM[2'h1][28:23];
rdata_hold_data_1 = {_RANDOM[2'h1][31:29], _RANDOM[2'h2][2:0]};
rdata_hold_data_2 = _RANDOM[2'h2][8:3];
rdata_hold_data_3 = _RANDOM[2'h2][14:9];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
_resetState = 1'h1;
_resetSet = 8'h0;
bypass_mask_need_check_reg_last_r = 1'h0;
rdata_last_r = 1'h0;
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
array_7 array (
.R0_addr (io_r_req_bits_setIdx),
.R0_en (io_r_req_valid),
.R0_clk (clock),
.R0_data (_array_R0_data),
.W0_addr (_resetState ? _resetSet : io_w_req_bits_setIdx),
.W0_en (io_w_req_valid | _resetState),
.W0_clk (clock),
.W0_data
({_resetState ? 6'h0 : io_w_req_bits_data_3,
_resetState ? 6'h0 : io_w_req_bits_data_2,
_resetState ? 6'h0 : io_w_req_bits_data_1,
_resetState ? 6'h0 : io_w_req_bits_data_0}),
.W0_mask (_resetState ? 4'hF : io_w_req_bits_waymask)
);
assign io_r_resp_data_0 = rdata_last_r ? mem_rdata_0 : rdata_hold_data_0;
assign io_r_resp_data_1 = rdata_last_r ? mem_rdata_1 : rdata_hold_data_1;
assign io_r_resp_data_2 = rdata_last_r ? mem_rdata_2 : rdata_hold_data_2;
assign io_r_resp_data_3 = rdata_last_r ? mem_rdata_3 : rdata_hold_data_3;
endmodule

149
rtl/BPUTop/SRAMTemplate_39.sv
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@ -1,149 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module SRAMTemplate_39(
input clock,
input reset,
input io_r_req_valid,
input [6:0] io_r_req_bits_setIdx,
output io_r_resp_data_0_valid,
output [8:0] io_r_resp_data_0_tag,
output [1:0] io_r_resp_data_0_ctr,
output [40:0] io_r_resp_data_0_target,
input io_w_req_valid,
input [6:0] io_w_req_bits_setIdx,
input [8:0] io_w_req_bits_data_0_tag,
input [1:0] io_w_req_bits_data_0_ctr,
input [40:0] io_w_req_bits_data_0_target
);
wire [6:0] setIdx;
wire realRen;
wire wen;
wire [52:0] _array_0_RW0_rdata;
reg _resetState;
reg [6:0] _resetSet;
assign wen = io_w_req_valid | _resetState;
assign realRen = io_r_req_valid & ~wen;
assign setIdx = _resetState ? _resetSet : io_w_req_bits_setIdx;
reg rdata_last_r;
reg [52:0] rdata_hold_data_0;
wire [52:0] _rdata_T_0 = rdata_last_r ? _array_0_RW0_rdata : rdata_hold_data_0;
always @(posedge clock or posedge reset) begin
if (reset) begin
_resetState <= 1'h1;
_resetSet <= 7'h0;
rdata_last_r <= 1'h0;
end
else begin
_resetState <= ~(_resetState & (&_resetSet)) & _resetState;
if (_resetState)
_resetSet <= 7'(_resetSet + 7'h1);
if (realRen | rdata_last_r)
rdata_last_r <= realRen;
end
end // always @(posedge, posedge)
always @(posedge clock) begin
if (rdata_last_r)
rdata_hold_data_0 <= _array_0_RW0_rdata;
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:4];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
for (logic [2:0] i = 3'h0; i < 3'h5; i += 3'h1) begin
_RANDOM[i] = `RANDOM;
end
_resetState = _RANDOM[3'h0][0];
_resetSet = _RANDOM[3'h0][7:1];
rdata_last_r = _RANDOM[3'h2][24];
rdata_hold_data_0 = {_RANDOM[3'h2][31:25], _RANDOM[3'h3], _RANDOM[3'h4][13:0]};
`endif // RANDOMIZE_REG_INIT
if (reset) begin
_resetState = 1'h1;
_resetSet = 7'h0;
rdata_last_r = 1'h0;
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
array_0_0 array_0 (
.RW0_addr (wen ? setIdx : io_r_req_bits_setIdx),
.RW0_en (realRen | wen),
.RW0_clk (clock),
.RW0_wmode (wen),
.RW0_wdata
({~_resetState,
_resetState ? 9'h0 : io_w_req_bits_data_0_tag,
_resetState ? 2'h0 : io_w_req_bits_data_0_ctr,
_resetState ? 41'h0 : io_w_req_bits_data_0_target}),
.RW0_rdata (_array_0_RW0_rdata)
);
assign io_r_resp_data_0_valid = _rdata_T_0[52];
assign io_r_resp_data_0_tag = _rdata_T_0[51:43];
assign io_r_resp_data_0_ctr = _rdata_T_0[42:41];
assign io_r_resp_data_0_target = _rdata_T_0[40:0];
endmodule

171
rtl/BPUTop/SRAMTemplate_43.sv
View File

@ -1,171 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module SRAMTemplate_43(
input clock,
input reset,
input io_r_req_valid,
input [6:0] io_r_req_bits_setIdx,
output io_r_resp_data_0_valid,
output [8:0] io_r_resp_data_0_tag,
output [1:0] io_r_resp_data_0_ctr,
output [40:0] io_r_resp_data_0_target,
output io_r_resp_data_1_valid,
output [8:0] io_r_resp_data_1_tag,
output [1:0] io_r_resp_data_1_ctr,
output [40:0] io_r_resp_data_1_target,
input io_w_req_valid,
input [6:0] io_w_req_bits_setIdx,
input [8:0] io_w_req_bits_data_0_tag,
input [1:0] io_w_req_bits_data_0_ctr,
input [40:0] io_w_req_bits_data_0_target,
input [8:0] io_w_req_bits_data_1_tag,
input [1:0] io_w_req_bits_data_1_ctr,
input [40:0] io_w_req_bits_data_1_target,
input [1:0] io_w_req_bits_waymask
);
wire [6:0] setIdx;
wire realRen;
wire wen;
wire [105:0] _array_RW0_rdata;
reg _resetState;
reg [6:0] _resetSet;
assign wen = io_w_req_valid | _resetState;
assign realRen = io_r_req_valid & ~wen;
assign setIdx = _resetState ? _resetSet : io_w_req_bits_setIdx;
reg rdata_last_r;
reg [52:0] rdata_hold_data_0;
reg [52:0] rdata_hold_data_1;
wire [52:0] _rdata_T_0 = rdata_last_r ? _array_RW0_rdata[52:0] : rdata_hold_data_0;
wire [52:0] _rdata_T_1 = rdata_last_r ? _array_RW0_rdata[105:53] : rdata_hold_data_1;
always @(posedge clock or posedge reset) begin
if (reset) begin
_resetState <= 1'h1;
_resetSet <= 7'h0;
rdata_last_r <= 1'h0;
end
else begin
_resetState <= ~(_resetState & (&_resetSet)) & _resetState;
if (_resetState)
_resetSet <= 7'(_resetSet + 7'h1);
if (realRen | rdata_last_r)
rdata_last_r <= realRen;
end
end // always @(posedge, posedge)
always @(posedge clock) begin
if (rdata_last_r) begin
rdata_hold_data_0 <= _array_RW0_rdata[52:0];
rdata_hold_data_1 <= _array_RW0_rdata[105:53];
end
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:8];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
for (logic [3:0] i = 4'h0; i < 4'h9; i += 4'h1) begin
_RANDOM[i] = `RANDOM;
end
_resetState = _RANDOM[4'h0][0];
_resetSet = _RANDOM[4'h0][7:1];
rdata_last_r = _RANDOM[4'h4][25];
rdata_hold_data_0 = {_RANDOM[4'h4][31:26], _RANDOM[4'h5], _RANDOM[4'h6][14:0]};
rdata_hold_data_1 = {_RANDOM[4'h6][31:15], _RANDOM[4'h7], _RANDOM[4'h8][3:0]};
`endif // RANDOMIZE_REG_INIT
if (reset) begin
_resetState = 1'h1;
_resetSet = 7'h0;
rdata_last_r = 1'h0;
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
array_8 array (
.RW0_addr (wen ? setIdx : io_r_req_bits_setIdx),
.RW0_en (realRen | wen),
.RW0_clk (clock),
.RW0_wmode (wen),
.RW0_wdata
({~_resetState,
_resetState ? 9'h0 : io_w_req_bits_data_1_tag,
_resetState ? 2'h0 : io_w_req_bits_data_1_ctr,
_resetState ? 41'h0 : io_w_req_bits_data_1_target,
~_resetState,
_resetState ? 9'h0 : io_w_req_bits_data_0_tag,
_resetState ? 2'h0 : io_w_req_bits_data_0_ctr,
_resetState ? 41'h0 : io_w_req_bits_data_0_target}),
.RW0_rdata (_array_RW0_rdata),
.RW0_wmask (_resetState ? 2'h3 : io_w_req_bits_waymask)
);
assign io_r_resp_data_0_valid = _rdata_T_0[52];
assign io_r_resp_data_0_tag = _rdata_T_0[51:43];
assign io_r_resp_data_0_ctr = _rdata_T_0[42:41];
assign io_r_resp_data_0_target = _rdata_T_0[40:0];
assign io_r_resp_data_1_valid = _rdata_T_1[52];
assign io_r_resp_data_1_tag = _rdata_T_1[51:43];
assign io_r_resp_data_1_ctr = _rdata_T_1[42:41];
assign io_r_resp_data_1_target = _rdata_T_1[40:0];
endmodule

188
rtl/BPUTop/TageBTable.sv
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@ -1,188 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module TageBTable(
input clock,
input reset,
output io_req_ready,
input io_req_valid,
input [40:0] io_req_bits,
output [1:0] io_s1_cnt_0,
output [1:0] io_s1_cnt_1,
input io_update_mask_0,
input io_update_mask_1,
input [40:0] io_update_pc,
input [1:0] io_update_cnt_0,
input [1:0] io_update_cnt_1,
input io_update_takens_0,
input io_update_takens_1
);
wire [1:0] newCtrs_1;
wire [1:0] newCtrs_0;
wire _wrbypass_io_hit;
wire _wrbypass_io_hit_data_0_valid;
wire [1:0] _wrbypass_io_hit_data_0_bits;
wire _wrbypass_io_hit_data_1_valid;
wire [1:0] _wrbypass_io_hit_data_1_bits;
wire [1:0] _bt_io_r_resp_data_0;
wire [1:0] _bt_io_r_resp_data_1;
reg doing_reset;
reg [10:0] resetRow;
reg [10:0] s1_idx;
wire _wrbypass_io_wen_T = io_update_mask_0 | io_update_mask_1;
wire [1:0] oldCtrs_0 =
_wrbypass_io_hit
& (io_update_pc[1] ? _wrbypass_io_hit_data_1_valid : _wrbypass_io_hit_data_0_valid)
? (io_update_pc[1] ? _wrbypass_io_hit_data_1_bits : _wrbypass_io_hit_data_0_bits)
: io_update_pc[1] ? io_update_cnt_1 : io_update_cnt_0;
wire [1:0] oldCtrs_1 =
_wrbypass_io_hit
& (io_update_pc[1] ? _wrbypass_io_hit_data_0_valid : _wrbypass_io_hit_data_1_valid)
? (io_update_pc[1] ? _wrbypass_io_hit_data_0_bits : _wrbypass_io_hit_data_1_bits)
: io_update_pc[1] ? io_update_cnt_0 : io_update_cnt_1;
wire _GEN = io_update_pc[1] ? io_update_takens_1 : io_update_takens_0;
assign newCtrs_0 =
(&oldCtrs_0) & _GEN
? 2'h3
: oldCtrs_0 == 2'h0 & ~_GEN
? 2'h0
: _GEN ? 2'(oldCtrs_0 + 2'h1) : 2'(oldCtrs_0 - 2'h1);
wire _GEN_0 = io_update_pc[1] ? io_update_takens_0 : io_update_takens_1;
assign newCtrs_1 =
(&oldCtrs_1) & _GEN_0
? 2'h3
: oldCtrs_1 == 2'h0 & ~_GEN_0
? 2'h0
: _GEN_0 ? 2'(oldCtrs_1 + 2'h1) : 2'(oldCtrs_1 - 2'h1);
always @(posedge clock or posedge reset) begin
if (reset) begin
doing_reset <= 1'h1;
resetRow <= 11'h0;
end
else begin
doing_reset <= resetRow != 11'h7FF & doing_reset;
resetRow <= 11'(resetRow + {10'h0, doing_reset});
end
end // always @(posedge, posedge)
always @(posedge clock) begin
if (io_req_valid)
s1_idx <= io_req_bits[11:1];
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
doing_reset = _RANDOM[/*Zero width*/ 1'b0][0];
resetRow = _RANDOM[/*Zero width*/ 1'b0][11:1];
s1_idx = _RANDOM[/*Zero width*/ 1'b0][22:12];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
doing_reset = 1'h1;
resetRow = 11'h0;
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
FoldedSRAMTemplate_20 bt (
.clock (clock),
.reset (reset),
.io_r_req_valid (io_req_valid),
.io_r_req_bits_setIdx (io_req_bits[11:1]),
.io_r_resp_data_0 (_bt_io_r_resp_data_0),
.io_r_resp_data_1 (_bt_io_r_resp_data_1),
.io_w_req_valid (_wrbypass_io_wen_T | doing_reset),
.io_w_req_bits_setIdx (doing_reset ? resetRow : io_update_pc[11:1]),
.io_w_req_bits_data_0 (doing_reset ? 2'h2 : newCtrs_0),
.io_w_req_bits_data_1 (doing_reset ? 2'h2 : newCtrs_1),
.io_w_req_bits_waymask
(doing_reset
? 2'h3
: {io_update_mask_0 & io_update_pc[1] | io_update_mask_1 & ~(io_update_pc[1]),
io_update_mask_0 & ~(io_update_pc[1]) | io_update_mask_1 & io_update_pc[1]})
);
WrBypass_32 wrbypass (
.clock (clock),
.reset (reset),
.io_wen (_wrbypass_io_wen_T),
.io_write_idx (io_update_pc[11:1]),
.io_write_data_0 (io_update_pc[1] ? newCtrs_1 : newCtrs_0),
.io_write_data_1 (io_update_pc[1] ? newCtrs_0 : newCtrs_1),
.io_write_way_mask_0 (io_update_mask_0),
.io_write_way_mask_1 (io_update_mask_1),
.io_hit (_wrbypass_io_hit),
.io_hit_data_0_valid (_wrbypass_io_hit_data_0_valid),
.io_hit_data_0_bits (_wrbypass_io_hit_data_0_bits),
.io_hit_data_1_valid (_wrbypass_io_hit_data_1_valid),
.io_hit_data_1_bits (_wrbypass_io_hit_data_1_bits)
);
assign io_req_ready = ~doing_reset;
assign io_s1_cnt_0 =
(s1_idx[0] ? 2'h0 : _bt_io_r_resp_data_0) | (s1_idx[0] ? _bt_io_r_resp_data_1 : 2'h0);
assign io_s1_cnt_1 =
(s1_idx[0] ? _bt_io_r_resp_data_0 : 2'h0) | (s1_idx[0] ? 2'h0 : _bt_io_r_resp_data_1);
endmodule

752
rtl/BPUTop/TageTable.sv
View File

@ -1,752 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module TageTable(
input clock,
input reset,
output io_req_ready,
input io_req_valid,
input [40:0] io_req_bits_pc,
input [7:0] io_req_bits_folded_hist_hist_14_folded_hist,
input [6:0] io_req_bits_folded_hist_hist_7_folded_hist,
output io_resps_0_valid,
output [2:0] io_resps_0_bits_ctr,
output io_resps_0_bits_u,
output io_resps_0_bits_unconf,
output io_resps_1_valid,
output [2:0] io_resps_1_bits_ctr,
output io_resps_1_bits_u,
output io_resps_1_bits_unconf,
input [40:0] io_update_pc,
input [7:0] io_update_folded_hist_hist_14_folded_hist,
input [6:0] io_update_folded_hist_hist_7_folded_hist,
input io_update_mask_0,
input io_update_mask_1,
input io_update_takens_0,
input io_update_takens_1,
input io_update_alloc_0,
input io_update_alloc_1,
input [2:0] io_update_oldCtrs_0,
input [2:0] io_update_oldCtrs_1,
input io_update_uMask_0,
input io_update_uMask_1,
input io_update_us_0,
input io_update_us_1,
input io_update_reset_u_0,
input io_update_reset_u_1
);
wire per_bank_not_silent_update_3_1;
wire per_bank_not_silent_update_3_0;
wire per_bank_not_silent_update_2_1;
wire per_bank_not_silent_update_2_0;
wire per_bank_not_silent_update_1_1;
wire per_bank_not_silent_update_1_0;
wire per_bank_not_silent_update_0_1;
wire per_bank_not_silent_update_0_0;
reg powerOnResetState;
wire _resp_invalid_by_write_T_6;
wire _bank_wrbypasses_3_1_io_hit;
wire _bank_wrbypasses_3_1_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_3_1_io_hit_data_0_bits;
wire _bank_wrbypasses_3_0_io_hit;
wire _bank_wrbypasses_3_0_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_3_0_io_hit_data_0_bits;
wire _bank_wrbypasses_2_1_io_hit;
wire _bank_wrbypasses_2_1_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_2_1_io_hit_data_0_bits;
wire _bank_wrbypasses_2_0_io_hit;
wire _bank_wrbypasses_2_0_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_2_0_io_hit_data_0_bits;
wire _bank_wrbypasses_1_1_io_hit;
wire _bank_wrbypasses_1_1_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_1_1_io_hit_data_0_bits;
wire _bank_wrbypasses_1_0_io_hit;
wire _bank_wrbypasses_1_0_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_1_0_io_hit_data_0_bits;
wire _bank_wrbypasses_0_1_io_hit;
wire _bank_wrbypasses_0_1_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_0_1_io_hit_data_0_bits;
wire _bank_wrbypasses_0_0_io_hit;
wire _bank_wrbypasses_0_0_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_0_0_io_hit_data_0_bits;
wire _table_banks_3_io_r_req_ready;
wire _table_banks_3_io_r_resp_data_0_valid;
wire [7:0] _table_banks_3_io_r_resp_data_0_tag;
wire [2:0] _table_banks_3_io_r_resp_data_0_ctr;
wire _table_banks_3_io_r_resp_data_1_valid;
wire [7:0] _table_banks_3_io_r_resp_data_1_tag;
wire [2:0] _table_banks_3_io_r_resp_data_1_ctr;
wire _table_banks_2_io_r_req_ready;
wire _table_banks_2_io_r_resp_data_0_valid;
wire [7:0] _table_banks_2_io_r_resp_data_0_tag;
wire [2:0] _table_banks_2_io_r_resp_data_0_ctr;
wire _table_banks_2_io_r_resp_data_1_valid;
wire [7:0] _table_banks_2_io_r_resp_data_1_tag;
wire [2:0] _table_banks_2_io_r_resp_data_1_ctr;
wire _table_banks_1_io_r_req_ready;
wire _table_banks_1_io_r_resp_data_0_valid;
wire [7:0] _table_banks_1_io_r_resp_data_0_tag;
wire [2:0] _table_banks_1_io_r_resp_data_0_ctr;
wire _table_banks_1_io_r_resp_data_1_valid;
wire [7:0] _table_banks_1_io_r_resp_data_1_tag;
wire [2:0] _table_banks_1_io_r_resp_data_1_ctr;
wire _table_banks_0_io_r_req_ready;
wire _table_banks_0_io_r_resp_data_0_valid;
wire [7:0] _table_banks_0_io_r_resp_data_0_tag;
wire [2:0] _table_banks_0_io_r_resp_data_0_ctr;
wire _table_banks_0_io_r_resp_data_1_valid;
wire [7:0] _table_banks_0_io_r_resp_data_1_tag;
wire [2:0] _table_banks_0_io_r_resp_data_1_ctr;
wire _us_io_r_req_ready;
wire _us_io_r_resp_data_0;
wire _us_io_r_resp_data_1;
wire _us_extra_reset_T_1 = io_update_mask_0 | io_update_mask_1;
wire [7:0] _GEN = io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_14_folded_hist;
wire s0_bank_req_1h_0 = _GEN[1:0] == 2'h0;
wire s0_bank_req_1h_1 = _GEN[1:0] == 2'h1;
wire s0_bank_req_1h_2 = _GEN[1:0] == 2'h2;
wire _s1_bank_req_1h_T = ~powerOnResetState & io_req_valid;
wire [8:0] _table_banks_3_io_r_req_bits_setIdx_T = {io_req_bits_pc[11:9], _GEN[7:2]};
reg [39:0] s1_unhashed_idx;
reg [7:0] s1_tag;
reg s1_bank_req_1h_0;
reg s1_bank_req_1h_1;
reg s1_bank_req_1h_2;
reg s1_bank_req_1h_3;
reg s1_bank_has_write_on_this_req_0;
reg s1_bank_has_write_on_this_req_1;
reg s1_bank_has_write_on_this_req_2;
reg s1_bank_has_write_on_this_req_3;
wire [2:0] _resp_selected_T_6 =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 3'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 3'h0)
| (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_0_ctr : 3'h0)
| (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_0_ctr : 3'h0);
wire [2:0] _resp_selected_T_27 =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_1_ctr : 3'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_1_ctr : 3'h0)
| (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_1_ctr : 3'h0)
| (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_1_ctr : 3'h0);
wire _unconf_selected_T_6 =
s1_bank_req_1h_0
& (_table_banks_0_io_r_resp_data_0_ctr == 3'h4
| _table_banks_0_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_1
& (_table_banks_1_io_r_resp_data_0_ctr == 3'h4
| _table_banks_1_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_2
& (_table_banks_2_io_r_resp_data_0_ctr == 3'h4
| _table_banks_2_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_3
& (_table_banks_3_io_r_resp_data_0_ctr == 3'h4
| _table_banks_3_io_r_resp_data_0_ctr == 3'h3);
wire _unconf_selected_T_13 =
s1_bank_req_1h_0
& (_table_banks_0_io_r_resp_data_1_ctr == 3'h4
| _table_banks_0_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_1
& (_table_banks_1_io_r_resp_data_1_ctr == 3'h4
| _table_banks_1_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_2
& (_table_banks_2_io_r_resp_data_1_ctr == 3'h4
| _table_banks_2_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_3
& (_table_banks_3_io_r_resp_data_1_ctr == 3'h4
| _table_banks_3_io_r_resp_data_1_ctr == 3'h3);
wire _hit_selected_T_6 =
s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_0_tag == s1_tag
& _table_banks_0_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6
| s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_0_tag == s1_tag
& _table_banks_1_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6
| s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_0_tag == s1_tag
& _table_banks_2_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6
| s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_0_tag == s1_tag
& _table_banks_3_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6;
wire _hit_selected_T_13 =
s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_1_tag == s1_tag
& _table_banks_0_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6
| s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_1_tag == s1_tag
& _table_banks_1_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6
| s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_1_tag == s1_tag
& _table_banks_2_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6
| s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_1_tag == s1_tag
& _table_banks_3_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6;
assign _resp_invalid_by_write_T_6 =
s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1
& s1_bank_has_write_on_this_req_1 | s1_bank_req_1h_2 & s1_bank_has_write_on_this_req_2
| s1_bank_req_1h_3 & s1_bank_has_write_on_this_req_3;
wire [7:0] _GEN_0 = io_update_pc[8:1] ^ io_update_folded_hist_hist_14_folded_hist;
wire [7:0] update_tag = _GEN_0 ^ {io_update_folded_hist_hist_7_folded_hist, 1'h0};
wire update_req_bank_1h_0 = _GEN_0[1:0] == 2'h0;
wire update_req_bank_1h_1 = _GEN_0[1:0] == 2'h1;
wire update_req_bank_1h_2 = _GEN_0[1:0] == 2'h2;
wire [8:0] update_idx_in_bank = {io_update_pc[11:9], _GEN_0[7:2]};
wire [1:0] per_bank_update_way_mask_0 =
{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
& per_bank_not_silent_update_0_1,
(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
& per_bank_not_silent_update_0_0};
wire [1:0] per_bank_update_way_mask_1 =
{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
& per_bank_not_silent_update_1_1,
(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
& per_bank_not_silent_update_1_0};
wire [1:0] per_bank_update_way_mask_2 =
{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
& per_bank_not_silent_update_2_1,
(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
& per_bank_not_silent_update_2_0};
wire [1:0] per_bank_update_way_mask_3 =
{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
& per_bank_not_silent_update_3_1,
(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
& per_bank_not_silent_update_3_0};
wire _s1_bank_has_write_on_this_req_WIRE_0 =
(|per_bank_update_way_mask_0) & update_req_bank_1h_0;
wire _s1_bank_has_write_on_this_req_WIRE_1 =
(|per_bank_update_way_mask_1) & update_req_bank_1h_1;
wire _s1_bank_has_write_on_this_req_WIRE_2 =
(|per_bank_update_way_mask_2) & update_req_bank_1h_2;
wire _s1_bank_has_write_on_this_req_WIRE_3 =
(|per_bank_update_way_mask_3) & (&(_GEN_0[1:0]));
wire [2:0] _wrbypass_io_T_6 =
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _bank_wrbypasses_0_1_io_hit_data_0_bits : 3'h0);
wire wrbypass_data_valid =
(~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit | io_update_pc[1]
& _bank_wrbypasses_0_1_io_hit)
& (~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit_data_0_valid | io_update_pc[1]
& _bank_wrbypasses_0_1_io_hit_data_0_valid);
wire _GEN_1 = io_update_pc[1] ? io_update_takens_1 : io_update_takens_0;
wire [2:0] _GEN_2 = io_update_pc[1] ? io_update_oldCtrs_1 : io_update_oldCtrs_0;
wire _GEN_3 = (|_GEN_2) | _GEN_1;
wire _GEN_4 = io_update_pc[1] ? io_update_alloc_1 : io_update_alloc_0;
wire [2:0] per_bank_update_wdata_0_0_ctr =
_GEN_4
? (_GEN_1 ? 3'h4 : 3'h3)
: wrbypass_data_valid
? ((&_wrbypass_io_T_6) & _GEN_1
? 3'h7
: _wrbypass_io_T_6 == 3'h0 & ~_GEN_1
? 3'h0
: _GEN_1 ? 3'(_wrbypass_io_T_6 + 3'h1) : 3'(_wrbypass_io_T_6 - 3'h1))
: (&_GEN_2) & _GEN_1
? 3'h7
: _GEN_3 ? (_GEN_1 ? 3'(_GEN_2 + 3'h1) : 3'(_GEN_2 - 3'h1)) : 3'h0;
assign per_bank_not_silent_update_0_0 =
(wrbypass_data_valid
? ~((&_wrbypass_io_T_6) & _GEN_1 | _wrbypass_io_T_6 == 3'h0 & ~_GEN_1)
: ~((&_GEN_2) & _GEN_1 | _GEN_2 == 3'h0 & ~_GEN_1)) | _GEN_4;
wire [2:0] _wrbypass_io_T_28 =
(io_update_pc[1] ? _bank_wrbypasses_0_0_io_hit_data_0_bits : 3'h0)
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_1_io_hit_data_0_bits);
wire wrbypass_data_valid_1 =
(io_update_pc[1] & _bank_wrbypasses_0_0_io_hit | ~(io_update_pc[1])
& _bank_wrbypasses_0_1_io_hit)
& (io_update_pc[1] & _bank_wrbypasses_0_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _bank_wrbypasses_0_1_io_hit_data_0_valid);
wire _GEN_5 = io_update_pc[1] ? io_update_takens_0 : io_update_takens_1;
wire [2:0] _GEN_6 = io_update_pc[1] ? io_update_oldCtrs_0 : io_update_oldCtrs_1;
wire _GEN_7 = io_update_pc[1] ? io_update_alloc_0 : io_update_alloc_1;
wire [2:0] per_bank_update_wdata_0_1_ctr =
_GEN_7
? (_GEN_5 ? 3'h4 : 3'h3)
: wrbypass_data_valid_1
? ((&_wrbypass_io_T_28) & _GEN_5
? 3'h7
: _wrbypass_io_T_28 == 3'h0 & ~_GEN_5
? 3'h0
: _GEN_5 ? 3'(_wrbypass_io_T_28 + 3'h1) : 3'(_wrbypass_io_T_28 - 3'h1))
: (&_GEN_6) & _GEN_5
? 3'h7
: _GEN_6 == 3'h0 & ~_GEN_5
? 3'h0
: _GEN_5 ? 3'(_GEN_6 + 3'h1) : 3'(_GEN_6 - 3'h1);
assign per_bank_not_silent_update_0_1 =
(wrbypass_data_valid_1
? ~((&_wrbypass_io_T_28) & _GEN_5 | _wrbypass_io_T_28 == 3'h0 & ~_GEN_5)
: ~((&_GEN_6) & _GEN_5 | _GEN_6 == 3'h0 & ~_GEN_5)) | _GEN_7;
wire [2:0] _wrbypass_io_T_50 =
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _bank_wrbypasses_1_1_io_hit_data_0_bits : 3'h0);
wire wrbypass_data_valid_2 =
(~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit | io_update_pc[1]
& _bank_wrbypasses_1_1_io_hit)
& (~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit_data_0_valid | io_update_pc[1]
& _bank_wrbypasses_1_1_io_hit_data_0_valid);
wire [2:0] per_bank_update_wdata_1_0_ctr =
_GEN_4
? (_GEN_1 ? 3'h4 : 3'h3)
: wrbypass_data_valid_2
? ((&_wrbypass_io_T_50) & _GEN_1
? 3'h7
: _wrbypass_io_T_50 == 3'h0 & ~_GEN_1
? 3'h0
: _GEN_1 ? 3'(_wrbypass_io_T_50 + 3'h1) : 3'(_wrbypass_io_T_50 - 3'h1))
: (&_GEN_2) & _GEN_1
? 3'h7
: _GEN_3 ? (_GEN_1 ? 3'(_GEN_2 + 3'h1) : 3'(_GEN_2 - 3'h1)) : 3'h0;
assign per_bank_not_silent_update_1_0 =
(wrbypass_data_valid_2
? ~((&_wrbypass_io_T_50) & _GEN_1 | _wrbypass_io_T_50 == 3'h0 & ~_GEN_1)
: ~((&_GEN_2) & _GEN_1 | _GEN_2 == 3'h0 & ~_GEN_1)) | _GEN_4;
wire [2:0] _wrbypass_io_T_72 =
(io_update_pc[1] ? _bank_wrbypasses_1_0_io_hit_data_0_bits : 3'h0)
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_1_io_hit_data_0_bits);
wire wrbypass_data_valid_3 =
(io_update_pc[1] & _bank_wrbypasses_1_0_io_hit | ~(io_update_pc[1])
& _bank_wrbypasses_1_1_io_hit)
& (io_update_pc[1] & _bank_wrbypasses_1_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _bank_wrbypasses_1_1_io_hit_data_0_valid);
wire [2:0] per_bank_update_wdata_1_1_ctr =
_GEN_7
? (_GEN_5 ? 3'h4 : 3'h3)
: wrbypass_data_valid_3
? ((&_wrbypass_io_T_72) & _GEN_5
? 3'h7
: _wrbypass_io_T_72 == 3'h0 & ~_GEN_5
? 3'h0
: _GEN_5 ? 3'(_wrbypass_io_T_72 + 3'h1) : 3'(_wrbypass_io_T_72 - 3'h1))
: (&_GEN_6) & _GEN_5
? 3'h7
: _GEN_6 == 3'h0 & ~_GEN_5
? 3'h0
: _GEN_5 ? 3'(_GEN_6 + 3'h1) : 3'(_GEN_6 - 3'h1);
assign per_bank_not_silent_update_1_1 =
(wrbypass_data_valid_3
? ~((&_wrbypass_io_T_72) & _GEN_5 | _wrbypass_io_T_72 == 3'h0 & ~_GEN_5)
: ~((&_GEN_6) & _GEN_5 | _GEN_6 == 3'h0 & ~_GEN_5)) | _GEN_7;
wire [2:0] _wrbypass_io_T_94 =
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _bank_wrbypasses_2_1_io_hit_data_0_bits : 3'h0);
wire wrbypass_data_valid_4 =
(~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit | io_update_pc[1]
& _bank_wrbypasses_2_1_io_hit)
& (~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit_data_0_valid | io_update_pc[1]
& _bank_wrbypasses_2_1_io_hit_data_0_valid);
wire [2:0] per_bank_update_wdata_2_0_ctr =
_GEN_4
? (_GEN_1 ? 3'h4 : 3'h3)
: wrbypass_data_valid_4
? ((&_wrbypass_io_T_94) & _GEN_1
? 3'h7
: _wrbypass_io_T_94 == 3'h0 & ~_GEN_1
? 3'h0
: _GEN_1 ? 3'(_wrbypass_io_T_94 + 3'h1) : 3'(_wrbypass_io_T_94 - 3'h1))
: (&_GEN_2) & _GEN_1
? 3'h7
: _GEN_3 ? (_GEN_1 ? 3'(_GEN_2 + 3'h1) : 3'(_GEN_2 - 3'h1)) : 3'h0;
assign per_bank_not_silent_update_2_0 =
(wrbypass_data_valid_4
? ~((&_wrbypass_io_T_94) & _GEN_1 | _wrbypass_io_T_94 == 3'h0 & ~_GEN_1)
: ~((&_GEN_2) & _GEN_1 | _GEN_2 == 3'h0 & ~_GEN_1)) | _GEN_4;
wire [2:0] _wrbypass_io_T_116 =
(io_update_pc[1] ? _bank_wrbypasses_2_0_io_hit_data_0_bits : 3'h0)
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_1_io_hit_data_0_bits);
wire wrbypass_data_valid_5 =
(io_update_pc[1] & _bank_wrbypasses_2_0_io_hit | ~(io_update_pc[1])
& _bank_wrbypasses_2_1_io_hit)
& (io_update_pc[1] & _bank_wrbypasses_2_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _bank_wrbypasses_2_1_io_hit_data_0_valid);
wire [2:0] per_bank_update_wdata_2_1_ctr =
_GEN_7
? (_GEN_5 ? 3'h4 : 3'h3)
: wrbypass_data_valid_5
? ((&_wrbypass_io_T_116) & _GEN_5
? 3'h7
: _wrbypass_io_T_116 == 3'h0 & ~_GEN_5
? 3'h0
: _GEN_5
? 3'(_wrbypass_io_T_116 + 3'h1)
: 3'(_wrbypass_io_T_116 - 3'h1))
: (&_GEN_6) & _GEN_5
? 3'h7
: _GEN_6 == 3'h0 & ~_GEN_5
? 3'h0
: _GEN_5 ? 3'(_GEN_6 + 3'h1) : 3'(_GEN_6 - 3'h1);
assign per_bank_not_silent_update_2_1 =
(wrbypass_data_valid_5
? ~((&_wrbypass_io_T_116) & _GEN_5 | _wrbypass_io_T_116 == 3'h0 & ~_GEN_5)
: ~((&_GEN_6) & _GEN_5 | _GEN_6 == 3'h0 & ~_GEN_5)) | _GEN_7;
wire [2:0] _wrbypass_io_T_138 =
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _bank_wrbypasses_3_1_io_hit_data_0_bits : 3'h0);
wire wrbypass_data_valid_6 =
(~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit | io_update_pc[1]
& _bank_wrbypasses_3_1_io_hit)
& (~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit_data_0_valid | io_update_pc[1]
& _bank_wrbypasses_3_1_io_hit_data_0_valid);
wire [2:0] per_bank_update_wdata_3_0_ctr =
_GEN_4
? (_GEN_1 ? 3'h4 : 3'h3)
: wrbypass_data_valid_6
? ((&_wrbypass_io_T_138) & _GEN_1
? 3'h7
: _wrbypass_io_T_138 == 3'h0 & ~_GEN_1
? 3'h0
: _GEN_1
? 3'(_wrbypass_io_T_138 + 3'h1)
: 3'(_wrbypass_io_T_138 - 3'h1))
: (&_GEN_2) & _GEN_1
? 3'h7
: _GEN_3 ? (_GEN_1 ? 3'(_GEN_2 + 3'h1) : 3'(_GEN_2 - 3'h1)) : 3'h0;
assign per_bank_not_silent_update_3_0 =
(wrbypass_data_valid_6
? ~((&_wrbypass_io_T_138) & _GEN_1 | _wrbypass_io_T_138 == 3'h0 & ~_GEN_1)
: ~((&_GEN_2) & _GEN_1 | _GEN_2 == 3'h0 & ~_GEN_1)) | _GEN_4;
wire [2:0] _wrbypass_io_T_160 =
(io_update_pc[1] ? _bank_wrbypasses_3_0_io_hit_data_0_bits : 3'h0)
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_1_io_hit_data_0_bits);
wire wrbypass_data_valid_7 =
(io_update_pc[1] & _bank_wrbypasses_3_0_io_hit | ~(io_update_pc[1])
& _bank_wrbypasses_3_1_io_hit)
& (io_update_pc[1] & _bank_wrbypasses_3_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _bank_wrbypasses_3_1_io_hit_data_0_valid);
wire [2:0] per_bank_update_wdata_3_1_ctr =
_GEN_7
? (_GEN_5 ? 3'h4 : 3'h3)
: wrbypass_data_valid_7
? ((&_wrbypass_io_T_160) & _GEN_5
? 3'h7
: _wrbypass_io_T_160 == 3'h0 & ~_GEN_5
? 3'h0
: _GEN_5
? 3'(_wrbypass_io_T_160 + 3'h1)
: 3'(_wrbypass_io_T_160 - 3'h1))
: (&_GEN_6) & _GEN_5
? 3'h7
: _GEN_6 == 3'h0 & ~_GEN_5
? 3'h0
: _GEN_5 ? 3'(_GEN_6 + 3'h1) : 3'(_GEN_6 - 3'h1);
assign per_bank_not_silent_update_3_1 =
(wrbypass_data_valid_7
? ~((&_wrbypass_io_T_160) & _GEN_5 | _wrbypass_io_T_160 == 3'h0 & ~_GEN_5)
: ~((&_GEN_6) & _GEN_5 | _GEN_6 == 3'h0 & ~_GEN_5)) | _GEN_7;
always @(posedge clock) begin
if (_s1_bank_req_1h_T) begin
s1_unhashed_idx <= io_req_bits_pc[40:1];
s1_tag <= _GEN ^ {io_req_bits_folded_hist_hist_7_folded_hist, 1'h0};
s1_bank_req_1h_0 <= s0_bank_req_1h_0;
s1_bank_req_1h_1 <= s0_bank_req_1h_1;
s1_bank_req_1h_2 <= s0_bank_req_1h_2;
s1_bank_req_1h_3 <= &(_GEN[1:0]);
end
if (io_req_valid) begin
s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0;
s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1;
s1_bank_has_write_on_this_req_2 <= _s1_bank_has_write_on_this_req_WIRE_2;
s1_bank_has_write_on_this_req_3 <= _s1_bank_has_write_on_this_req_WIRE_3;
end
end // always @(posedge)
always @(posedge clock or posedge reset) begin
if (reset)
powerOnResetState <= 1'h1;
else
powerOnResetState <=
~(_us_io_r_req_ready & _table_banks_0_io_r_req_ready
& _table_banks_1_io_r_req_ready & _table_banks_2_io_r_req_ready
& _table_banks_3_io_r_req_ready) & powerOnResetState;
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:3];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin
_RANDOM[i[1:0]] = `RANDOM;
end
s1_unhashed_idx = {_RANDOM[2'h0], _RANDOM[2'h1][7:0]};
s1_tag = _RANDOM[2'h1][26:19];
s1_bank_req_1h_0 = _RANDOM[2'h3][4];
s1_bank_req_1h_1 = _RANDOM[2'h3][5];
s1_bank_req_1h_2 = _RANDOM[2'h3][6];
s1_bank_req_1h_3 = _RANDOM[2'h3][7];
s1_bank_has_write_on_this_req_0 = _RANDOM[2'h3][8];
s1_bank_has_write_on_this_req_1 = _RANDOM[2'h3][9];
s1_bank_has_write_on_this_req_2 = _RANDOM[2'h3][10];
s1_bank_has_write_on_this_req_3 = _RANDOM[2'h3][11];
powerOnResetState = _RANDOM[2'h3][12];
`endif // RANDOMIZE_REG_INIT
if (reset)
powerOnResetState = 1'h1;
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
FoldedSRAMTemplate us (
.clock (clock),
.reset (reset),
.io_r_req_ready (_us_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T),
.io_r_req_bits_setIdx ({io_req_bits_pc[11:9], _GEN}),
.io_r_resp_data_0 (_us_io_r_resp_data_0),
.io_r_resp_data_1 (_us_io_r_resp_data_1),
.io_w_req_valid
(_us_extra_reset_T_1 & (io_update_uMask_0 | io_update_uMask_1)),
.io_w_req_bits_setIdx ({io_update_pc[11:9], _GEN_0}),
.io_w_req_bits_data_0
(~(io_update_pc[1]) & io_update_us_0 | io_update_pc[1] & io_update_us_1),
.io_w_req_bits_data_1
(io_update_pc[1] & io_update_us_0 | ~(io_update_pc[1]) & io_update_us_1),
.io_w_req_bits_waymask
({io_update_pc[1] & io_update_uMask_0 | ~(io_update_pc[1]) & io_update_uMask_1,
~(io_update_pc[1]) & io_update_uMask_0 | io_update_pc[1] & io_update_uMask_1}),
.extra_reset
((io_update_reset_u_0 | io_update_reset_u_1) & _us_extra_reset_T_1)
);
FoldedSRAMTemplate_1 table_banks_0 (
.clock (clock),
.reset (reset),
.io_r_req_ready (_table_banks_0_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_0),
.io_r_req_bits_setIdx (_table_banks_3_io_r_req_bits_setIdx_T),
.io_r_resp_data_0_valid (_table_banks_0_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (_table_banks_0_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_table_banks_0_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_table_banks_0_io_r_resp_data_1_ctr),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0),
.io_w_req_bits_setIdx (update_idx_in_bank),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_0_0_ctr),
.io_w_req_bits_data_1_tag (update_tag),
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_0_1_ctr),
.io_w_req_bits_waymask (per_bank_update_way_mask_0)
);
FoldedSRAMTemplate_1 table_banks_1 (
.clock (clock),
.reset (reset),
.io_r_req_ready (_table_banks_1_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_1),
.io_r_req_bits_setIdx (_table_banks_3_io_r_req_bits_setIdx_T),
.io_r_resp_data_0_valid (_table_banks_1_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (_table_banks_1_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_table_banks_1_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_table_banks_1_io_r_resp_data_1_ctr),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1),
.io_w_req_bits_setIdx (update_idx_in_bank),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_1_0_ctr),
.io_w_req_bits_data_1_tag (update_tag),
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_1_1_ctr),
.io_w_req_bits_waymask (per_bank_update_way_mask_1)
);
FoldedSRAMTemplate_1 table_banks_2 (
.clock (clock),
.reset (reset),
.io_r_req_ready (_table_banks_2_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_2),
.io_r_req_bits_setIdx (_table_banks_3_io_r_req_bits_setIdx_T),
.io_r_resp_data_0_valid (_table_banks_2_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_2_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_2_io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (_table_banks_2_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_table_banks_2_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_table_banks_2_io_r_resp_data_1_ctr),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_2),
.io_w_req_bits_setIdx (update_idx_in_bank),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_2_0_ctr),
.io_w_req_bits_data_1_tag (update_tag),
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_2_1_ctr),
.io_w_req_bits_waymask (per_bank_update_way_mask_2)
);
FoldedSRAMTemplate_1 table_banks_3 (
.clock (clock),
.reset (reset),
.io_r_req_ready (_table_banks_3_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T & (&(_GEN[1:0]))),
.io_r_req_bits_setIdx (_table_banks_3_io_r_req_bits_setIdx_T),
.io_r_resp_data_0_valid (_table_banks_3_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_3_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_3_io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (_table_banks_3_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_table_banks_3_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_table_banks_3_io_r_resp_data_1_ctr),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_3),
.io_w_req_bits_setIdx (update_idx_in_bank),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_3_0_ctr),
.io_w_req_bits_data_1_tag (update_tag),
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_3_1_ctr),
.io_w_req_bits_waymask (per_bank_update_way_mask_3)
);
WrBypass bank_wrbypasses_0_0 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0 & update_req_bank_1h_0),
.io_write_idx (update_idx_in_bank),
.io_write_data_0
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_0_ctr)
| (io_update_pc[1] ? per_bank_update_wdata_0_1_ctr : 3'h0)),
.io_hit (_bank_wrbypasses_0_0_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_0_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_0_0_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_0_1 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1 & update_req_bank_1h_0),
.io_write_idx (update_idx_in_bank),
.io_write_data_0
((io_update_pc[1] ? per_bank_update_wdata_0_0_ctr : 3'h0)
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_1_ctr)),
.io_hit (_bank_wrbypasses_0_1_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_0_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_0_1_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_1_0 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0 & update_req_bank_1h_1),
.io_write_idx (update_idx_in_bank),
.io_write_data_0
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_0_ctr)
| (io_update_pc[1] ? per_bank_update_wdata_1_1_ctr : 3'h0)),
.io_hit (_bank_wrbypasses_1_0_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_1_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_1_0_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_1_1 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1 & update_req_bank_1h_1),
.io_write_idx (update_idx_in_bank),
.io_write_data_0
((io_update_pc[1] ? per_bank_update_wdata_1_0_ctr : 3'h0)
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_1_ctr)),
.io_hit (_bank_wrbypasses_1_1_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_1_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_1_1_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_2_0 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0 & update_req_bank_1h_2),
.io_write_idx (update_idx_in_bank),
.io_write_data_0
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_0_ctr)
| (io_update_pc[1] ? per_bank_update_wdata_2_1_ctr : 3'h0)),
.io_hit (_bank_wrbypasses_2_0_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_2_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_2_0_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_2_1 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1 & update_req_bank_1h_2),
.io_write_idx (update_idx_in_bank),
.io_write_data_0
((io_update_pc[1] ? per_bank_update_wdata_2_0_ctr : 3'h0)
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_1_ctr)),
.io_hit (_bank_wrbypasses_2_1_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_2_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_2_1_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_3_0 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0 & (&(_GEN_0[1:0]))),
.io_write_idx (update_idx_in_bank),
.io_write_data_0
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_0_ctr)
| (io_update_pc[1] ? per_bank_update_wdata_3_1_ctr : 3'h0)),
.io_hit (_bank_wrbypasses_3_0_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_3_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_3_0_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_3_1 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1 & (&(_GEN_0[1:0]))),
.io_write_idx (update_idx_in_bank),
.io_write_data_0
((io_update_pc[1] ? per_bank_update_wdata_3_0_ctr : 3'h0)
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_1_ctr)),
.io_hit (_bank_wrbypasses_3_1_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_3_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_3_1_io_hit_data_0_bits)
);
assign io_req_ready = ~powerOnResetState;
assign io_resps_0_valid =
~(s1_unhashed_idx[0]) & _hit_selected_T_6 | s1_unhashed_idx[0] & _hit_selected_T_13;
assign io_resps_0_bits_ctr =
(s1_unhashed_idx[0] ? 3'h0 : _resp_selected_T_6)
| (s1_unhashed_idx[0] ? _resp_selected_T_27 : 3'h0);
assign io_resps_0_bits_u =
~(s1_unhashed_idx[0]) & _us_io_r_resp_data_0 | s1_unhashed_idx[0]
& _us_io_r_resp_data_1;
assign io_resps_0_bits_unconf =
~(s1_unhashed_idx[0]) & _unconf_selected_T_6 | s1_unhashed_idx[0]
& _unconf_selected_T_13;
assign io_resps_1_valid =
s1_unhashed_idx[0] & _hit_selected_T_6 | ~(s1_unhashed_idx[0]) & _hit_selected_T_13;
assign io_resps_1_bits_ctr =
(s1_unhashed_idx[0] ? _resp_selected_T_6 : 3'h0)
| (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_T_27);
assign io_resps_1_bits_u =
s1_unhashed_idx[0] & _us_io_r_resp_data_0 | ~(s1_unhashed_idx[0])
& _us_io_r_resp_data_1;
assign io_resps_1_bits_unconf =
s1_unhashed_idx[0] & _unconf_selected_T_6 | ~(s1_unhashed_idx[0])
& _unconf_selected_T_13;
endmodule

754
rtl/BPUTop/TageTable_1.sv
View File

@ -1,754 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module TageTable_1(
input clock,
input reset,
output io_req_ready,
input io_req_valid,
input [40:0] io_req_bits_pc,
input [6:0] io_req_bits_folded_hist_hist_15_folded_hist,
input [7:0] io_req_bits_folded_hist_hist_4_folded_hist,
input [10:0] io_req_bits_folded_hist_hist_1_folded_hist,
output io_resps_0_valid,
output [2:0] io_resps_0_bits_ctr,
output io_resps_0_bits_u,
output io_resps_0_bits_unconf,
output io_resps_1_valid,
output [2:0] io_resps_1_bits_ctr,
output io_resps_1_bits_u,
output io_resps_1_bits_unconf,
input [40:0] io_update_pc,
input [6:0] io_update_folded_hist_hist_15_folded_hist,
input [7:0] io_update_folded_hist_hist_4_folded_hist,
input [10:0] io_update_folded_hist_hist_1_folded_hist,
input io_update_mask_0,
input io_update_mask_1,
input io_update_takens_0,
input io_update_takens_1,
input io_update_alloc_0,
input io_update_alloc_1,
input [2:0] io_update_oldCtrs_0,
input [2:0] io_update_oldCtrs_1,
input io_update_uMask_0,
input io_update_uMask_1,
input io_update_us_0,
input io_update_us_1,
input io_update_reset_u_0,
input io_update_reset_u_1
);
wire per_bank_not_silent_update_3_1;
wire per_bank_not_silent_update_3_0;
wire per_bank_not_silent_update_2_1;
wire per_bank_not_silent_update_2_0;
wire per_bank_not_silent_update_1_1;
wire per_bank_not_silent_update_1_0;
wire per_bank_not_silent_update_0_1;
wire per_bank_not_silent_update_0_0;
reg powerOnResetState;
wire _resp_invalid_by_write_T_6;
wire _bank_wrbypasses_3_1_io_hit;
wire _bank_wrbypasses_3_1_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_3_1_io_hit_data_0_bits;
wire _bank_wrbypasses_3_0_io_hit;
wire _bank_wrbypasses_3_0_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_3_0_io_hit_data_0_bits;
wire _bank_wrbypasses_2_1_io_hit;
wire _bank_wrbypasses_2_1_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_2_1_io_hit_data_0_bits;
wire _bank_wrbypasses_2_0_io_hit;
wire _bank_wrbypasses_2_0_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_2_0_io_hit_data_0_bits;
wire _bank_wrbypasses_1_1_io_hit;
wire _bank_wrbypasses_1_1_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_1_1_io_hit_data_0_bits;
wire _bank_wrbypasses_1_0_io_hit;
wire _bank_wrbypasses_1_0_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_1_0_io_hit_data_0_bits;
wire _bank_wrbypasses_0_1_io_hit;
wire _bank_wrbypasses_0_1_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_0_1_io_hit_data_0_bits;
wire _bank_wrbypasses_0_0_io_hit;
wire _bank_wrbypasses_0_0_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_0_0_io_hit_data_0_bits;
wire _table_banks_3_io_r_req_ready;
wire _table_banks_3_io_r_resp_data_0_valid;
wire [7:0] _table_banks_3_io_r_resp_data_0_tag;
wire [2:0] _table_banks_3_io_r_resp_data_0_ctr;
wire _table_banks_3_io_r_resp_data_1_valid;
wire [7:0] _table_banks_3_io_r_resp_data_1_tag;
wire [2:0] _table_banks_3_io_r_resp_data_1_ctr;
wire _table_banks_2_io_r_req_ready;
wire _table_banks_2_io_r_resp_data_0_valid;
wire [7:0] _table_banks_2_io_r_resp_data_0_tag;
wire [2:0] _table_banks_2_io_r_resp_data_0_ctr;
wire _table_banks_2_io_r_resp_data_1_valid;
wire [7:0] _table_banks_2_io_r_resp_data_1_tag;
wire [2:0] _table_banks_2_io_r_resp_data_1_ctr;
wire _table_banks_1_io_r_req_ready;
wire _table_banks_1_io_r_resp_data_0_valid;
wire [7:0] _table_banks_1_io_r_resp_data_0_tag;
wire [2:0] _table_banks_1_io_r_resp_data_0_ctr;
wire _table_banks_1_io_r_resp_data_1_valid;
wire [7:0] _table_banks_1_io_r_resp_data_1_tag;
wire [2:0] _table_banks_1_io_r_resp_data_1_ctr;
wire _table_banks_0_io_r_req_ready;
wire _table_banks_0_io_r_resp_data_0_valid;
wire [7:0] _table_banks_0_io_r_resp_data_0_tag;
wire [2:0] _table_banks_0_io_r_resp_data_0_ctr;
wire _table_banks_0_io_r_resp_data_1_valid;
wire [7:0] _table_banks_0_io_r_resp_data_1_tag;
wire [2:0] _table_banks_0_io_r_resp_data_1_ctr;
wire _us_io_r_req_ready;
wire _us_io_r_resp_data_0;
wire _us_io_r_resp_data_1;
wire _us_extra_reset_T_1 = io_update_mask_0 | io_update_mask_1;
wire [10:0] s0_idx = io_req_bits_pc[11:1] ^ io_req_bits_folded_hist_hist_1_folded_hist;
wire s0_bank_req_1h_0 = s0_idx[1:0] == 2'h0;
wire s0_bank_req_1h_1 = s0_idx[1:0] == 2'h1;
wire s0_bank_req_1h_2 = s0_idx[1:0] == 2'h2;
wire _s1_bank_req_1h_T = ~powerOnResetState & io_req_valid;
reg [39:0] s1_unhashed_idx;
reg [7:0] s1_tag;
reg s1_bank_req_1h_0;
reg s1_bank_req_1h_1;
reg s1_bank_req_1h_2;
reg s1_bank_req_1h_3;
reg s1_bank_has_write_on_this_req_0;
reg s1_bank_has_write_on_this_req_1;
reg s1_bank_has_write_on_this_req_2;
reg s1_bank_has_write_on_this_req_3;
wire [2:0] _resp_selected_T_6 =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 3'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 3'h0)
| (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_0_ctr : 3'h0)
| (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_0_ctr : 3'h0);
wire [2:0] _resp_selected_T_27 =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_1_ctr : 3'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_1_ctr : 3'h0)
| (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_1_ctr : 3'h0)
| (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_1_ctr : 3'h0);
wire _unconf_selected_T_6 =
s1_bank_req_1h_0
& (_table_banks_0_io_r_resp_data_0_ctr == 3'h4
| _table_banks_0_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_1
& (_table_banks_1_io_r_resp_data_0_ctr == 3'h4
| _table_banks_1_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_2
& (_table_banks_2_io_r_resp_data_0_ctr == 3'h4
| _table_banks_2_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_3
& (_table_banks_3_io_r_resp_data_0_ctr == 3'h4
| _table_banks_3_io_r_resp_data_0_ctr == 3'h3);
wire _unconf_selected_T_13 =
s1_bank_req_1h_0
& (_table_banks_0_io_r_resp_data_1_ctr == 3'h4
| _table_banks_0_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_1
& (_table_banks_1_io_r_resp_data_1_ctr == 3'h4
| _table_banks_1_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_2
& (_table_banks_2_io_r_resp_data_1_ctr == 3'h4
| _table_banks_2_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_3
& (_table_banks_3_io_r_resp_data_1_ctr == 3'h4
| _table_banks_3_io_r_resp_data_1_ctr == 3'h3);
wire _hit_selected_T_6 =
s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_0_tag == s1_tag
& _table_banks_0_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6
| s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_0_tag == s1_tag
& _table_banks_1_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6
| s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_0_tag == s1_tag
& _table_banks_2_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6
| s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_0_tag == s1_tag
& _table_banks_3_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6;
wire _hit_selected_T_13 =
s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_1_tag == s1_tag
& _table_banks_0_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6
| s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_1_tag == s1_tag
& _table_banks_1_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6
| s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_1_tag == s1_tag
& _table_banks_2_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6
| s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_1_tag == s1_tag
& _table_banks_3_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6;
assign _resp_invalid_by_write_T_6 =
s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1
& s1_bank_has_write_on_this_req_1 | s1_bank_req_1h_2 & s1_bank_has_write_on_this_req_2
| s1_bank_req_1h_3 & s1_bank_has_write_on_this_req_3;
wire [10:0] update_idx = io_update_pc[11:1] ^ io_update_folded_hist_hist_1_folded_hist;
wire [7:0] update_tag =
io_update_pc[8:1] ^ io_update_folded_hist_hist_4_folded_hist
^ {io_update_folded_hist_hist_15_folded_hist, 1'h0};
wire update_req_bank_1h_0 = update_idx[1:0] == 2'h0;
wire update_req_bank_1h_1 = update_idx[1:0] == 2'h1;
wire update_req_bank_1h_2 = update_idx[1:0] == 2'h2;
wire [1:0] per_bank_update_way_mask_0 =
{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
& per_bank_not_silent_update_0_1,
(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
& per_bank_not_silent_update_0_0};
wire [1:0] per_bank_update_way_mask_1 =
{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
& per_bank_not_silent_update_1_1,
(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
& per_bank_not_silent_update_1_0};
wire [1:0] per_bank_update_way_mask_2 =
{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
& per_bank_not_silent_update_2_1,
(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
& per_bank_not_silent_update_2_0};
wire [1:0] per_bank_update_way_mask_3 =
{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
& per_bank_not_silent_update_3_1,
(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
& per_bank_not_silent_update_3_0};
wire _s1_bank_has_write_on_this_req_WIRE_0 =
(|per_bank_update_way_mask_0) & update_req_bank_1h_0;
wire _s1_bank_has_write_on_this_req_WIRE_1 =
(|per_bank_update_way_mask_1) & update_req_bank_1h_1;
wire _s1_bank_has_write_on_this_req_WIRE_2 =
(|per_bank_update_way_mask_2) & update_req_bank_1h_2;
wire _s1_bank_has_write_on_this_req_WIRE_3 =
(|per_bank_update_way_mask_3) & (&(update_idx[1:0]));
wire [2:0] _wrbypass_io_T_6 =
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _bank_wrbypasses_0_1_io_hit_data_0_bits : 3'h0);
wire wrbypass_data_valid =
(~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit | io_update_pc[1]
& _bank_wrbypasses_0_1_io_hit)
& (~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit_data_0_valid | io_update_pc[1]
& _bank_wrbypasses_0_1_io_hit_data_0_valid);
wire _GEN = io_update_pc[1] ? io_update_takens_1 : io_update_takens_0;
wire [2:0] _GEN_0 = io_update_pc[1] ? io_update_oldCtrs_1 : io_update_oldCtrs_0;
wire _GEN_1 = (|_GEN_0) | _GEN;
wire _GEN_2 = io_update_pc[1] ? io_update_alloc_1 : io_update_alloc_0;
wire [2:0] per_bank_update_wdata_0_0_ctr =
_GEN_2
? (_GEN ? 3'h4 : 3'h3)
: wrbypass_data_valid
? ((&_wrbypass_io_T_6) & _GEN
? 3'h7
: _wrbypass_io_T_6 == 3'h0 & ~_GEN
? 3'h0
: _GEN ? 3'(_wrbypass_io_T_6 + 3'h1) : 3'(_wrbypass_io_T_6 - 3'h1))
: (&_GEN_0) & _GEN
? 3'h7
: _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0;
assign per_bank_not_silent_update_0_0 =
(wrbypass_data_valid
? ~((&_wrbypass_io_T_6) & _GEN | _wrbypass_io_T_6 == 3'h0 & ~_GEN)
: ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2;
wire [2:0] _wrbypass_io_T_28 =
(io_update_pc[1] ? _bank_wrbypasses_0_0_io_hit_data_0_bits : 3'h0)
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_1_io_hit_data_0_bits);
wire wrbypass_data_valid_1 =
(io_update_pc[1] & _bank_wrbypasses_0_0_io_hit | ~(io_update_pc[1])
& _bank_wrbypasses_0_1_io_hit)
& (io_update_pc[1] & _bank_wrbypasses_0_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _bank_wrbypasses_0_1_io_hit_data_0_valid);
wire _GEN_3 = io_update_pc[1] ? io_update_takens_0 : io_update_takens_1;
wire [2:0] _GEN_4 = io_update_pc[1] ? io_update_oldCtrs_0 : io_update_oldCtrs_1;
wire _GEN_5 = io_update_pc[1] ? io_update_alloc_0 : io_update_alloc_1;
wire [2:0] per_bank_update_wdata_0_1_ctr =
_GEN_5
? (_GEN_3 ? 3'h4 : 3'h3)
: wrbypass_data_valid_1
? ((&_wrbypass_io_T_28) & _GEN_3
? 3'h7
: _wrbypass_io_T_28 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3 ? 3'(_wrbypass_io_T_28 + 3'h1) : 3'(_wrbypass_io_T_28 - 3'h1))
: (&_GEN_4) & _GEN_3
? 3'h7
: _GEN_4 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1);
assign per_bank_not_silent_update_0_1 =
(wrbypass_data_valid_1
? ~((&_wrbypass_io_T_28) & _GEN_3 | _wrbypass_io_T_28 == 3'h0 & ~_GEN_3)
: ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5;
wire [2:0] _wrbypass_io_T_50 =
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _bank_wrbypasses_1_1_io_hit_data_0_bits : 3'h0);
wire wrbypass_data_valid_2 =
(~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit | io_update_pc[1]
& _bank_wrbypasses_1_1_io_hit)
& (~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit_data_0_valid | io_update_pc[1]
& _bank_wrbypasses_1_1_io_hit_data_0_valid);
wire [2:0] per_bank_update_wdata_1_0_ctr =
_GEN_2
? (_GEN ? 3'h4 : 3'h3)
: wrbypass_data_valid_2
? ((&_wrbypass_io_T_50) & _GEN
? 3'h7
: _wrbypass_io_T_50 == 3'h0 & ~_GEN
? 3'h0
: _GEN ? 3'(_wrbypass_io_T_50 + 3'h1) : 3'(_wrbypass_io_T_50 - 3'h1))
: (&_GEN_0) & _GEN
? 3'h7
: _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0;
assign per_bank_not_silent_update_1_0 =
(wrbypass_data_valid_2
? ~((&_wrbypass_io_T_50) & _GEN | _wrbypass_io_T_50 == 3'h0 & ~_GEN)
: ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2;
wire [2:0] _wrbypass_io_T_72 =
(io_update_pc[1] ? _bank_wrbypasses_1_0_io_hit_data_0_bits : 3'h0)
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_1_io_hit_data_0_bits);
wire wrbypass_data_valid_3 =
(io_update_pc[1] & _bank_wrbypasses_1_0_io_hit | ~(io_update_pc[1])
& _bank_wrbypasses_1_1_io_hit)
& (io_update_pc[1] & _bank_wrbypasses_1_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _bank_wrbypasses_1_1_io_hit_data_0_valid);
wire [2:0] per_bank_update_wdata_1_1_ctr =
_GEN_5
? (_GEN_3 ? 3'h4 : 3'h3)
: wrbypass_data_valid_3
? ((&_wrbypass_io_T_72) & _GEN_3
? 3'h7
: _wrbypass_io_T_72 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3 ? 3'(_wrbypass_io_T_72 + 3'h1) : 3'(_wrbypass_io_T_72 - 3'h1))
: (&_GEN_4) & _GEN_3
? 3'h7
: _GEN_4 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1);
assign per_bank_not_silent_update_1_1 =
(wrbypass_data_valid_3
? ~((&_wrbypass_io_T_72) & _GEN_3 | _wrbypass_io_T_72 == 3'h0 & ~_GEN_3)
: ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5;
wire [2:0] _wrbypass_io_T_94 =
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _bank_wrbypasses_2_1_io_hit_data_0_bits : 3'h0);
wire wrbypass_data_valid_4 =
(~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit | io_update_pc[1]
& _bank_wrbypasses_2_1_io_hit)
& (~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit_data_0_valid | io_update_pc[1]
& _bank_wrbypasses_2_1_io_hit_data_0_valid);
wire [2:0] per_bank_update_wdata_2_0_ctr =
_GEN_2
? (_GEN ? 3'h4 : 3'h3)
: wrbypass_data_valid_4
? ((&_wrbypass_io_T_94) & _GEN
? 3'h7
: _wrbypass_io_T_94 == 3'h0 & ~_GEN
? 3'h0
: _GEN ? 3'(_wrbypass_io_T_94 + 3'h1) : 3'(_wrbypass_io_T_94 - 3'h1))
: (&_GEN_0) & _GEN
? 3'h7
: _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0;
assign per_bank_not_silent_update_2_0 =
(wrbypass_data_valid_4
? ~((&_wrbypass_io_T_94) & _GEN | _wrbypass_io_T_94 == 3'h0 & ~_GEN)
: ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2;
wire [2:0] _wrbypass_io_T_116 =
(io_update_pc[1] ? _bank_wrbypasses_2_0_io_hit_data_0_bits : 3'h0)
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_1_io_hit_data_0_bits);
wire wrbypass_data_valid_5 =
(io_update_pc[1] & _bank_wrbypasses_2_0_io_hit | ~(io_update_pc[1])
& _bank_wrbypasses_2_1_io_hit)
& (io_update_pc[1] & _bank_wrbypasses_2_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _bank_wrbypasses_2_1_io_hit_data_0_valid);
wire [2:0] per_bank_update_wdata_2_1_ctr =
_GEN_5
? (_GEN_3 ? 3'h4 : 3'h3)
: wrbypass_data_valid_5
? ((&_wrbypass_io_T_116) & _GEN_3
? 3'h7
: _wrbypass_io_T_116 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3
? 3'(_wrbypass_io_T_116 + 3'h1)
: 3'(_wrbypass_io_T_116 - 3'h1))
: (&_GEN_4) & _GEN_3
? 3'h7
: _GEN_4 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1);
assign per_bank_not_silent_update_2_1 =
(wrbypass_data_valid_5
? ~((&_wrbypass_io_T_116) & _GEN_3 | _wrbypass_io_T_116 == 3'h0 & ~_GEN_3)
: ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5;
wire [2:0] _wrbypass_io_T_138 =
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _bank_wrbypasses_3_1_io_hit_data_0_bits : 3'h0);
wire wrbypass_data_valid_6 =
(~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit | io_update_pc[1]
& _bank_wrbypasses_3_1_io_hit)
& (~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit_data_0_valid | io_update_pc[1]
& _bank_wrbypasses_3_1_io_hit_data_0_valid);
wire [2:0] per_bank_update_wdata_3_0_ctr =
_GEN_2
? (_GEN ? 3'h4 : 3'h3)
: wrbypass_data_valid_6
? ((&_wrbypass_io_T_138) & _GEN
? 3'h7
: _wrbypass_io_T_138 == 3'h0 & ~_GEN
? 3'h0
: _GEN ? 3'(_wrbypass_io_T_138 + 3'h1) : 3'(_wrbypass_io_T_138 - 3'h1))
: (&_GEN_0) & _GEN
? 3'h7
: _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0;
assign per_bank_not_silent_update_3_0 =
(wrbypass_data_valid_6
? ~((&_wrbypass_io_T_138) & _GEN | _wrbypass_io_T_138 == 3'h0 & ~_GEN)
: ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2;
wire [2:0] _wrbypass_io_T_160 =
(io_update_pc[1] ? _bank_wrbypasses_3_0_io_hit_data_0_bits : 3'h0)
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_1_io_hit_data_0_bits);
wire wrbypass_data_valid_7 =
(io_update_pc[1] & _bank_wrbypasses_3_0_io_hit | ~(io_update_pc[1])
& _bank_wrbypasses_3_1_io_hit)
& (io_update_pc[1] & _bank_wrbypasses_3_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _bank_wrbypasses_3_1_io_hit_data_0_valid);
wire [2:0] per_bank_update_wdata_3_1_ctr =
_GEN_5
? (_GEN_3 ? 3'h4 : 3'h3)
: wrbypass_data_valid_7
? ((&_wrbypass_io_T_160) & _GEN_3
? 3'h7
: _wrbypass_io_T_160 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3
? 3'(_wrbypass_io_T_160 + 3'h1)
: 3'(_wrbypass_io_T_160 - 3'h1))
: (&_GEN_4) & _GEN_3
? 3'h7
: _GEN_4 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1);
assign per_bank_not_silent_update_3_1 =
(wrbypass_data_valid_7
? ~((&_wrbypass_io_T_160) & _GEN_3 | _wrbypass_io_T_160 == 3'h0 & ~_GEN_3)
: ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5;
always @(posedge clock) begin
if (_s1_bank_req_1h_T) begin
s1_unhashed_idx <= io_req_bits_pc[40:1];
s1_tag <=
io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_4_folded_hist
^ {io_req_bits_folded_hist_hist_15_folded_hist, 1'h0};
s1_bank_req_1h_0 <= s0_bank_req_1h_0;
s1_bank_req_1h_1 <= s0_bank_req_1h_1;
s1_bank_req_1h_2 <= s0_bank_req_1h_2;
s1_bank_req_1h_3 <= &(s0_idx[1:0]);
end
if (io_req_valid) begin
s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0;
s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1;
s1_bank_has_write_on_this_req_2 <= _s1_bank_has_write_on_this_req_WIRE_2;
s1_bank_has_write_on_this_req_3 <= _s1_bank_has_write_on_this_req_WIRE_3;
end
end // always @(posedge)
always @(posedge clock or posedge reset) begin
if (reset)
powerOnResetState <= 1'h1;
else
powerOnResetState <=
~(_us_io_r_req_ready & _table_banks_0_io_r_req_ready
& _table_banks_1_io_r_req_ready & _table_banks_2_io_r_req_ready
& _table_banks_3_io_r_req_ready) & powerOnResetState;
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:3];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin
_RANDOM[i[1:0]] = `RANDOM;
end
s1_unhashed_idx = {_RANDOM[2'h0], _RANDOM[2'h1][7:0]};
s1_tag = _RANDOM[2'h1][26:19];
s1_bank_req_1h_0 = _RANDOM[2'h3][4];
s1_bank_req_1h_1 = _RANDOM[2'h3][5];
s1_bank_req_1h_2 = _RANDOM[2'h3][6];
s1_bank_req_1h_3 = _RANDOM[2'h3][7];
s1_bank_has_write_on_this_req_0 = _RANDOM[2'h3][8];
s1_bank_has_write_on_this_req_1 = _RANDOM[2'h3][9];
s1_bank_has_write_on_this_req_2 = _RANDOM[2'h3][10];
s1_bank_has_write_on_this_req_3 = _RANDOM[2'h3][11];
powerOnResetState = _RANDOM[2'h3][12];
`endif // RANDOMIZE_REG_INIT
if (reset)
powerOnResetState = 1'h1;
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
FoldedSRAMTemplate us (
.clock (clock),
.reset (reset),
.io_r_req_ready (_us_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T),
.io_r_req_bits_setIdx (s0_idx),
.io_r_resp_data_0 (_us_io_r_resp_data_0),
.io_r_resp_data_1 (_us_io_r_resp_data_1),
.io_w_req_valid
(_us_extra_reset_T_1 & (io_update_uMask_0 | io_update_uMask_1)),
.io_w_req_bits_setIdx (update_idx),
.io_w_req_bits_data_0
(~(io_update_pc[1]) & io_update_us_0 | io_update_pc[1] & io_update_us_1),
.io_w_req_bits_data_1
(io_update_pc[1] & io_update_us_0 | ~(io_update_pc[1]) & io_update_us_1),
.io_w_req_bits_waymask
({io_update_pc[1] & io_update_uMask_0 | ~(io_update_pc[1]) & io_update_uMask_1,
~(io_update_pc[1]) & io_update_uMask_0 | io_update_pc[1] & io_update_uMask_1}),
.extra_reset
((io_update_reset_u_0 | io_update_reset_u_1) & _us_extra_reset_T_1)
);
FoldedSRAMTemplate_1 table_banks_0 (
.clock (clock),
.reset (reset),
.io_r_req_ready (_table_banks_0_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_0),
.io_r_req_bits_setIdx (s0_idx[10:2]),
.io_r_resp_data_0_valid (_table_banks_0_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (_table_banks_0_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_table_banks_0_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_table_banks_0_io_r_resp_data_1_ctr),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0),
.io_w_req_bits_setIdx (update_idx[10:2]),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_0_0_ctr),
.io_w_req_bits_data_1_tag (update_tag),
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_0_1_ctr),
.io_w_req_bits_waymask (per_bank_update_way_mask_0)
);
FoldedSRAMTemplate_1 table_banks_1 (
.clock (clock),
.reset (reset),
.io_r_req_ready (_table_banks_1_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_1),
.io_r_req_bits_setIdx (s0_idx[10:2]),
.io_r_resp_data_0_valid (_table_banks_1_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (_table_banks_1_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_table_banks_1_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_table_banks_1_io_r_resp_data_1_ctr),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1),
.io_w_req_bits_setIdx (update_idx[10:2]),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_1_0_ctr),
.io_w_req_bits_data_1_tag (update_tag),
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_1_1_ctr),
.io_w_req_bits_waymask (per_bank_update_way_mask_1)
);
FoldedSRAMTemplate_1 table_banks_2 (
.clock (clock),
.reset (reset),
.io_r_req_ready (_table_banks_2_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_2),
.io_r_req_bits_setIdx (s0_idx[10:2]),
.io_r_resp_data_0_valid (_table_banks_2_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_2_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_2_io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (_table_banks_2_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_table_banks_2_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_table_banks_2_io_r_resp_data_1_ctr),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_2),
.io_w_req_bits_setIdx (update_idx[10:2]),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_2_0_ctr),
.io_w_req_bits_data_1_tag (update_tag),
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_2_1_ctr),
.io_w_req_bits_waymask (per_bank_update_way_mask_2)
);
FoldedSRAMTemplate_1 table_banks_3 (
.clock (clock),
.reset (reset),
.io_r_req_ready (_table_banks_3_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T & (&(s0_idx[1:0]))),
.io_r_req_bits_setIdx (s0_idx[10:2]),
.io_r_resp_data_0_valid (_table_banks_3_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_3_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_3_io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (_table_banks_3_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_table_banks_3_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_table_banks_3_io_r_resp_data_1_ctr),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_3),
.io_w_req_bits_setIdx (update_idx[10:2]),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_3_0_ctr),
.io_w_req_bits_data_1_tag (update_tag),
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_3_1_ctr),
.io_w_req_bits_waymask (per_bank_update_way_mask_3)
);
WrBypass bank_wrbypasses_0_0 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0 & update_req_bank_1h_0),
.io_write_idx (update_idx[10:2]),
.io_write_data_0
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_0_ctr)
| (io_update_pc[1] ? per_bank_update_wdata_0_1_ctr : 3'h0)),
.io_hit (_bank_wrbypasses_0_0_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_0_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_0_0_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_0_1 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1 & update_req_bank_1h_0),
.io_write_idx (update_idx[10:2]),
.io_write_data_0
((io_update_pc[1] ? per_bank_update_wdata_0_0_ctr : 3'h0)
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_1_ctr)),
.io_hit (_bank_wrbypasses_0_1_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_0_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_0_1_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_1_0 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0 & update_req_bank_1h_1),
.io_write_idx (update_idx[10:2]),
.io_write_data_0
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_0_ctr)
| (io_update_pc[1] ? per_bank_update_wdata_1_1_ctr : 3'h0)),
.io_hit (_bank_wrbypasses_1_0_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_1_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_1_0_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_1_1 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1 & update_req_bank_1h_1),
.io_write_idx (update_idx[10:2]),
.io_write_data_0
((io_update_pc[1] ? per_bank_update_wdata_1_0_ctr : 3'h0)
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_1_ctr)),
.io_hit (_bank_wrbypasses_1_1_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_1_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_1_1_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_2_0 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0 & update_req_bank_1h_2),
.io_write_idx (update_idx[10:2]),
.io_write_data_0
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_0_ctr)
| (io_update_pc[1] ? per_bank_update_wdata_2_1_ctr : 3'h0)),
.io_hit (_bank_wrbypasses_2_0_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_2_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_2_0_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_2_1 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1 & update_req_bank_1h_2),
.io_write_idx (update_idx[10:2]),
.io_write_data_0
((io_update_pc[1] ? per_bank_update_wdata_2_0_ctr : 3'h0)
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_1_ctr)),
.io_hit (_bank_wrbypasses_2_1_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_2_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_2_1_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_3_0 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0 & (&(update_idx[1:0]))),
.io_write_idx (update_idx[10:2]),
.io_write_data_0
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_0_ctr)
| (io_update_pc[1] ? per_bank_update_wdata_3_1_ctr : 3'h0)),
.io_hit (_bank_wrbypasses_3_0_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_3_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_3_0_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_3_1 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1 & (&(update_idx[1:0]))),
.io_write_idx (update_idx[10:2]),
.io_write_data_0
((io_update_pc[1] ? per_bank_update_wdata_3_0_ctr : 3'h0)
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_1_ctr)),
.io_hit (_bank_wrbypasses_3_1_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_3_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_3_1_io_hit_data_0_bits)
);
assign io_req_ready = ~powerOnResetState;
assign io_resps_0_valid =
~(s1_unhashed_idx[0]) & _hit_selected_T_6 | s1_unhashed_idx[0] & _hit_selected_T_13;
assign io_resps_0_bits_ctr =
(s1_unhashed_idx[0] ? 3'h0 : _resp_selected_T_6)
| (s1_unhashed_idx[0] ? _resp_selected_T_27 : 3'h0);
assign io_resps_0_bits_u =
~(s1_unhashed_idx[0]) & _us_io_r_resp_data_0 | s1_unhashed_idx[0]
& _us_io_r_resp_data_1;
assign io_resps_0_bits_unconf =
~(s1_unhashed_idx[0]) & _unconf_selected_T_6 | s1_unhashed_idx[0]
& _unconf_selected_T_13;
assign io_resps_1_valid =
s1_unhashed_idx[0] & _hit_selected_T_6 | ~(s1_unhashed_idx[0]) & _hit_selected_T_13;
assign io_resps_1_bits_ctr =
(s1_unhashed_idx[0] ? _resp_selected_T_6 : 3'h0)
| (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_T_27);
assign io_resps_1_bits_u =
s1_unhashed_idx[0] & _us_io_r_resp_data_0 | ~(s1_unhashed_idx[0])
& _us_io_r_resp_data_1;
assign io_resps_1_bits_unconf =
s1_unhashed_idx[0] & _unconf_selected_T_6 | ~(s1_unhashed_idx[0])
& _unconf_selected_T_13;
endmodule

754
rtl/BPUTop/TageTable_2.sv
View File

@ -1,754 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module TageTable_2(
input clock,
input reset,
output io_req_ready,
input io_req_valid,
input [40:0] io_req_bits_pc,
input [10:0] io_req_bits_folded_hist_hist_17_folded_hist,
input [6:0] io_req_bits_folded_hist_hist_9_folded_hist,
input [7:0] io_req_bits_folded_hist_hist_3_folded_hist,
output io_resps_0_valid,
output [2:0] io_resps_0_bits_ctr,
output io_resps_0_bits_u,
output io_resps_0_bits_unconf,
output io_resps_1_valid,
output [2:0] io_resps_1_bits_ctr,
output io_resps_1_bits_u,
output io_resps_1_bits_unconf,
input [40:0] io_update_pc,
input [10:0] io_update_folded_hist_hist_17_folded_hist,
input [6:0] io_update_folded_hist_hist_9_folded_hist,
input [7:0] io_update_folded_hist_hist_3_folded_hist,
input io_update_mask_0,
input io_update_mask_1,
input io_update_takens_0,
input io_update_takens_1,
input io_update_alloc_0,
input io_update_alloc_1,
input [2:0] io_update_oldCtrs_0,
input [2:0] io_update_oldCtrs_1,
input io_update_uMask_0,
input io_update_uMask_1,
input io_update_us_0,
input io_update_us_1,
input io_update_reset_u_0,
input io_update_reset_u_1
);
wire per_bank_not_silent_update_3_1;
wire per_bank_not_silent_update_3_0;
wire per_bank_not_silent_update_2_1;
wire per_bank_not_silent_update_2_0;
wire per_bank_not_silent_update_1_1;
wire per_bank_not_silent_update_1_0;
wire per_bank_not_silent_update_0_1;
wire per_bank_not_silent_update_0_0;
reg powerOnResetState;
wire _resp_invalid_by_write_T_6;
wire _bank_wrbypasses_3_1_io_hit;
wire _bank_wrbypasses_3_1_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_3_1_io_hit_data_0_bits;
wire _bank_wrbypasses_3_0_io_hit;
wire _bank_wrbypasses_3_0_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_3_0_io_hit_data_0_bits;
wire _bank_wrbypasses_2_1_io_hit;
wire _bank_wrbypasses_2_1_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_2_1_io_hit_data_0_bits;
wire _bank_wrbypasses_2_0_io_hit;
wire _bank_wrbypasses_2_0_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_2_0_io_hit_data_0_bits;
wire _bank_wrbypasses_1_1_io_hit;
wire _bank_wrbypasses_1_1_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_1_1_io_hit_data_0_bits;
wire _bank_wrbypasses_1_0_io_hit;
wire _bank_wrbypasses_1_0_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_1_0_io_hit_data_0_bits;
wire _bank_wrbypasses_0_1_io_hit;
wire _bank_wrbypasses_0_1_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_0_1_io_hit_data_0_bits;
wire _bank_wrbypasses_0_0_io_hit;
wire _bank_wrbypasses_0_0_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_0_0_io_hit_data_0_bits;
wire _table_banks_3_io_r_req_ready;
wire _table_banks_3_io_r_resp_data_0_valid;
wire [7:0] _table_banks_3_io_r_resp_data_0_tag;
wire [2:0] _table_banks_3_io_r_resp_data_0_ctr;
wire _table_banks_3_io_r_resp_data_1_valid;
wire [7:0] _table_banks_3_io_r_resp_data_1_tag;
wire [2:0] _table_banks_3_io_r_resp_data_1_ctr;
wire _table_banks_2_io_r_req_ready;
wire _table_banks_2_io_r_resp_data_0_valid;
wire [7:0] _table_banks_2_io_r_resp_data_0_tag;
wire [2:0] _table_banks_2_io_r_resp_data_0_ctr;
wire _table_banks_2_io_r_resp_data_1_valid;
wire [7:0] _table_banks_2_io_r_resp_data_1_tag;
wire [2:0] _table_banks_2_io_r_resp_data_1_ctr;
wire _table_banks_1_io_r_req_ready;
wire _table_banks_1_io_r_resp_data_0_valid;
wire [7:0] _table_banks_1_io_r_resp_data_0_tag;
wire [2:0] _table_banks_1_io_r_resp_data_0_ctr;
wire _table_banks_1_io_r_resp_data_1_valid;
wire [7:0] _table_banks_1_io_r_resp_data_1_tag;
wire [2:0] _table_banks_1_io_r_resp_data_1_ctr;
wire _table_banks_0_io_r_req_ready;
wire _table_banks_0_io_r_resp_data_0_valid;
wire [7:0] _table_banks_0_io_r_resp_data_0_tag;
wire [2:0] _table_banks_0_io_r_resp_data_0_ctr;
wire _table_banks_0_io_r_resp_data_1_valid;
wire [7:0] _table_banks_0_io_r_resp_data_1_tag;
wire [2:0] _table_banks_0_io_r_resp_data_1_ctr;
wire _us_io_r_req_ready;
wire _us_io_r_resp_data_0;
wire _us_io_r_resp_data_1;
wire _us_extra_reset_T_1 = io_update_mask_0 | io_update_mask_1;
wire [10:0] s0_idx = io_req_bits_pc[11:1] ^ io_req_bits_folded_hist_hist_17_folded_hist;
wire s0_bank_req_1h_0 = s0_idx[1:0] == 2'h0;
wire s0_bank_req_1h_1 = s0_idx[1:0] == 2'h1;
wire s0_bank_req_1h_2 = s0_idx[1:0] == 2'h2;
wire _s1_bank_req_1h_T = ~powerOnResetState & io_req_valid;
reg [39:0] s1_unhashed_idx;
reg [7:0] s1_tag;
reg s1_bank_req_1h_0;
reg s1_bank_req_1h_1;
reg s1_bank_req_1h_2;
reg s1_bank_req_1h_3;
reg s1_bank_has_write_on_this_req_0;
reg s1_bank_has_write_on_this_req_1;
reg s1_bank_has_write_on_this_req_2;
reg s1_bank_has_write_on_this_req_3;
wire [2:0] _resp_selected_T_6 =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 3'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 3'h0)
| (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_0_ctr : 3'h0)
| (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_0_ctr : 3'h0);
wire [2:0] _resp_selected_T_27 =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_1_ctr : 3'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_1_ctr : 3'h0)
| (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_1_ctr : 3'h0)
| (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_1_ctr : 3'h0);
wire _unconf_selected_T_6 =
s1_bank_req_1h_0
& (_table_banks_0_io_r_resp_data_0_ctr == 3'h4
| _table_banks_0_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_1
& (_table_banks_1_io_r_resp_data_0_ctr == 3'h4
| _table_banks_1_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_2
& (_table_banks_2_io_r_resp_data_0_ctr == 3'h4
| _table_banks_2_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_3
& (_table_banks_3_io_r_resp_data_0_ctr == 3'h4
| _table_banks_3_io_r_resp_data_0_ctr == 3'h3);
wire _unconf_selected_T_13 =
s1_bank_req_1h_0
& (_table_banks_0_io_r_resp_data_1_ctr == 3'h4
| _table_banks_0_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_1
& (_table_banks_1_io_r_resp_data_1_ctr == 3'h4
| _table_banks_1_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_2
& (_table_banks_2_io_r_resp_data_1_ctr == 3'h4
| _table_banks_2_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_3
& (_table_banks_3_io_r_resp_data_1_ctr == 3'h4
| _table_banks_3_io_r_resp_data_1_ctr == 3'h3);
wire _hit_selected_T_6 =
s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_0_tag == s1_tag
& _table_banks_0_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6
| s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_0_tag == s1_tag
& _table_banks_1_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6
| s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_0_tag == s1_tag
& _table_banks_2_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6
| s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_0_tag == s1_tag
& _table_banks_3_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6;
wire _hit_selected_T_13 =
s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_1_tag == s1_tag
& _table_banks_0_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6
| s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_1_tag == s1_tag
& _table_banks_1_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6
| s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_1_tag == s1_tag
& _table_banks_2_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6
| s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_1_tag == s1_tag
& _table_banks_3_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6;
assign _resp_invalid_by_write_T_6 =
s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1
& s1_bank_has_write_on_this_req_1 | s1_bank_req_1h_2 & s1_bank_has_write_on_this_req_2
| s1_bank_req_1h_3 & s1_bank_has_write_on_this_req_3;
wire [10:0] update_idx = io_update_pc[11:1] ^ io_update_folded_hist_hist_17_folded_hist;
wire [7:0] update_tag =
io_update_pc[8:1] ^ io_update_folded_hist_hist_3_folded_hist
^ {io_update_folded_hist_hist_9_folded_hist, 1'h0};
wire update_req_bank_1h_0 = update_idx[1:0] == 2'h0;
wire update_req_bank_1h_1 = update_idx[1:0] == 2'h1;
wire update_req_bank_1h_2 = update_idx[1:0] == 2'h2;
wire [1:0] per_bank_update_way_mask_0 =
{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
& per_bank_not_silent_update_0_1,
(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
& per_bank_not_silent_update_0_0};
wire [1:0] per_bank_update_way_mask_1 =
{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
& per_bank_not_silent_update_1_1,
(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
& per_bank_not_silent_update_1_0};
wire [1:0] per_bank_update_way_mask_2 =
{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
& per_bank_not_silent_update_2_1,
(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
& per_bank_not_silent_update_2_0};
wire [1:0] per_bank_update_way_mask_3 =
{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
& per_bank_not_silent_update_3_1,
(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
& per_bank_not_silent_update_3_0};
wire _s1_bank_has_write_on_this_req_WIRE_0 =
(|per_bank_update_way_mask_0) & update_req_bank_1h_0;
wire _s1_bank_has_write_on_this_req_WIRE_1 =
(|per_bank_update_way_mask_1) & update_req_bank_1h_1;
wire _s1_bank_has_write_on_this_req_WIRE_2 =
(|per_bank_update_way_mask_2) & update_req_bank_1h_2;
wire _s1_bank_has_write_on_this_req_WIRE_3 =
(|per_bank_update_way_mask_3) & (&(update_idx[1:0]));
wire [2:0] _wrbypass_io_T_6 =
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _bank_wrbypasses_0_1_io_hit_data_0_bits : 3'h0);
wire wrbypass_data_valid =
(~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit | io_update_pc[1]
& _bank_wrbypasses_0_1_io_hit)
& (~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit_data_0_valid | io_update_pc[1]
& _bank_wrbypasses_0_1_io_hit_data_0_valid);
wire _GEN = io_update_pc[1] ? io_update_takens_1 : io_update_takens_0;
wire [2:0] _GEN_0 = io_update_pc[1] ? io_update_oldCtrs_1 : io_update_oldCtrs_0;
wire _GEN_1 = (|_GEN_0) | _GEN;
wire _GEN_2 = io_update_pc[1] ? io_update_alloc_1 : io_update_alloc_0;
wire [2:0] per_bank_update_wdata_0_0_ctr =
_GEN_2
? (_GEN ? 3'h4 : 3'h3)
: wrbypass_data_valid
? ((&_wrbypass_io_T_6) & _GEN
? 3'h7
: _wrbypass_io_T_6 == 3'h0 & ~_GEN
? 3'h0
: _GEN ? 3'(_wrbypass_io_T_6 + 3'h1) : 3'(_wrbypass_io_T_6 - 3'h1))
: (&_GEN_0) & _GEN
? 3'h7
: _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0;
assign per_bank_not_silent_update_0_0 =
(wrbypass_data_valid
? ~((&_wrbypass_io_T_6) & _GEN | _wrbypass_io_T_6 == 3'h0 & ~_GEN)
: ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2;
wire [2:0] _wrbypass_io_T_28 =
(io_update_pc[1] ? _bank_wrbypasses_0_0_io_hit_data_0_bits : 3'h0)
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_1_io_hit_data_0_bits);
wire wrbypass_data_valid_1 =
(io_update_pc[1] & _bank_wrbypasses_0_0_io_hit | ~(io_update_pc[1])
& _bank_wrbypasses_0_1_io_hit)
& (io_update_pc[1] & _bank_wrbypasses_0_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _bank_wrbypasses_0_1_io_hit_data_0_valid);
wire _GEN_3 = io_update_pc[1] ? io_update_takens_0 : io_update_takens_1;
wire [2:0] _GEN_4 = io_update_pc[1] ? io_update_oldCtrs_0 : io_update_oldCtrs_1;
wire _GEN_5 = io_update_pc[1] ? io_update_alloc_0 : io_update_alloc_1;
wire [2:0] per_bank_update_wdata_0_1_ctr =
_GEN_5
? (_GEN_3 ? 3'h4 : 3'h3)
: wrbypass_data_valid_1
? ((&_wrbypass_io_T_28) & _GEN_3
? 3'h7
: _wrbypass_io_T_28 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3 ? 3'(_wrbypass_io_T_28 + 3'h1) : 3'(_wrbypass_io_T_28 - 3'h1))
: (&_GEN_4) & _GEN_3
? 3'h7
: _GEN_4 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1);
assign per_bank_not_silent_update_0_1 =
(wrbypass_data_valid_1
? ~((&_wrbypass_io_T_28) & _GEN_3 | _wrbypass_io_T_28 == 3'h0 & ~_GEN_3)
: ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5;
wire [2:0] _wrbypass_io_T_50 =
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _bank_wrbypasses_1_1_io_hit_data_0_bits : 3'h0);
wire wrbypass_data_valid_2 =
(~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit | io_update_pc[1]
& _bank_wrbypasses_1_1_io_hit)
& (~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit_data_0_valid | io_update_pc[1]
& _bank_wrbypasses_1_1_io_hit_data_0_valid);
wire [2:0] per_bank_update_wdata_1_0_ctr =
_GEN_2
? (_GEN ? 3'h4 : 3'h3)
: wrbypass_data_valid_2
? ((&_wrbypass_io_T_50) & _GEN
? 3'h7
: _wrbypass_io_T_50 == 3'h0 & ~_GEN
? 3'h0
: _GEN ? 3'(_wrbypass_io_T_50 + 3'h1) : 3'(_wrbypass_io_T_50 - 3'h1))
: (&_GEN_0) & _GEN
? 3'h7
: _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0;
assign per_bank_not_silent_update_1_0 =
(wrbypass_data_valid_2
? ~((&_wrbypass_io_T_50) & _GEN | _wrbypass_io_T_50 == 3'h0 & ~_GEN)
: ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2;
wire [2:0] _wrbypass_io_T_72 =
(io_update_pc[1] ? _bank_wrbypasses_1_0_io_hit_data_0_bits : 3'h0)
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_1_io_hit_data_0_bits);
wire wrbypass_data_valid_3 =
(io_update_pc[1] & _bank_wrbypasses_1_0_io_hit | ~(io_update_pc[1])
& _bank_wrbypasses_1_1_io_hit)
& (io_update_pc[1] & _bank_wrbypasses_1_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _bank_wrbypasses_1_1_io_hit_data_0_valid);
wire [2:0] per_bank_update_wdata_1_1_ctr =
_GEN_5
? (_GEN_3 ? 3'h4 : 3'h3)
: wrbypass_data_valid_3
? ((&_wrbypass_io_T_72) & _GEN_3
? 3'h7
: _wrbypass_io_T_72 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3 ? 3'(_wrbypass_io_T_72 + 3'h1) : 3'(_wrbypass_io_T_72 - 3'h1))
: (&_GEN_4) & _GEN_3
? 3'h7
: _GEN_4 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1);
assign per_bank_not_silent_update_1_1 =
(wrbypass_data_valid_3
? ~((&_wrbypass_io_T_72) & _GEN_3 | _wrbypass_io_T_72 == 3'h0 & ~_GEN_3)
: ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5;
wire [2:0] _wrbypass_io_T_94 =
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _bank_wrbypasses_2_1_io_hit_data_0_bits : 3'h0);
wire wrbypass_data_valid_4 =
(~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit | io_update_pc[1]
& _bank_wrbypasses_2_1_io_hit)
& (~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit_data_0_valid | io_update_pc[1]
& _bank_wrbypasses_2_1_io_hit_data_0_valid);
wire [2:0] per_bank_update_wdata_2_0_ctr =
_GEN_2
? (_GEN ? 3'h4 : 3'h3)
: wrbypass_data_valid_4
? ((&_wrbypass_io_T_94) & _GEN
? 3'h7
: _wrbypass_io_T_94 == 3'h0 & ~_GEN
? 3'h0
: _GEN ? 3'(_wrbypass_io_T_94 + 3'h1) : 3'(_wrbypass_io_T_94 - 3'h1))
: (&_GEN_0) & _GEN
? 3'h7
: _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0;
assign per_bank_not_silent_update_2_0 =
(wrbypass_data_valid_4
? ~((&_wrbypass_io_T_94) & _GEN | _wrbypass_io_T_94 == 3'h0 & ~_GEN)
: ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2;
wire [2:0] _wrbypass_io_T_116 =
(io_update_pc[1] ? _bank_wrbypasses_2_0_io_hit_data_0_bits : 3'h0)
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_1_io_hit_data_0_bits);
wire wrbypass_data_valid_5 =
(io_update_pc[1] & _bank_wrbypasses_2_0_io_hit | ~(io_update_pc[1])
& _bank_wrbypasses_2_1_io_hit)
& (io_update_pc[1] & _bank_wrbypasses_2_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _bank_wrbypasses_2_1_io_hit_data_0_valid);
wire [2:0] per_bank_update_wdata_2_1_ctr =
_GEN_5
? (_GEN_3 ? 3'h4 : 3'h3)
: wrbypass_data_valid_5
? ((&_wrbypass_io_T_116) & _GEN_3
? 3'h7
: _wrbypass_io_T_116 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3
? 3'(_wrbypass_io_T_116 + 3'h1)
: 3'(_wrbypass_io_T_116 - 3'h1))
: (&_GEN_4) & _GEN_3
? 3'h7
: _GEN_4 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1);
assign per_bank_not_silent_update_2_1 =
(wrbypass_data_valid_5
? ~((&_wrbypass_io_T_116) & _GEN_3 | _wrbypass_io_T_116 == 3'h0 & ~_GEN_3)
: ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5;
wire [2:0] _wrbypass_io_T_138 =
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _bank_wrbypasses_3_1_io_hit_data_0_bits : 3'h0);
wire wrbypass_data_valid_6 =
(~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit | io_update_pc[1]
& _bank_wrbypasses_3_1_io_hit)
& (~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit_data_0_valid | io_update_pc[1]
& _bank_wrbypasses_3_1_io_hit_data_0_valid);
wire [2:0] per_bank_update_wdata_3_0_ctr =
_GEN_2
? (_GEN ? 3'h4 : 3'h3)
: wrbypass_data_valid_6
? ((&_wrbypass_io_T_138) & _GEN
? 3'h7
: _wrbypass_io_T_138 == 3'h0 & ~_GEN
? 3'h0
: _GEN ? 3'(_wrbypass_io_T_138 + 3'h1) : 3'(_wrbypass_io_T_138 - 3'h1))
: (&_GEN_0) & _GEN
? 3'h7
: _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0;
assign per_bank_not_silent_update_3_0 =
(wrbypass_data_valid_6
? ~((&_wrbypass_io_T_138) & _GEN | _wrbypass_io_T_138 == 3'h0 & ~_GEN)
: ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2;
wire [2:0] _wrbypass_io_T_160 =
(io_update_pc[1] ? _bank_wrbypasses_3_0_io_hit_data_0_bits : 3'h0)
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_1_io_hit_data_0_bits);
wire wrbypass_data_valid_7 =
(io_update_pc[1] & _bank_wrbypasses_3_0_io_hit | ~(io_update_pc[1])
& _bank_wrbypasses_3_1_io_hit)
& (io_update_pc[1] & _bank_wrbypasses_3_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _bank_wrbypasses_3_1_io_hit_data_0_valid);
wire [2:0] per_bank_update_wdata_3_1_ctr =
_GEN_5
? (_GEN_3 ? 3'h4 : 3'h3)
: wrbypass_data_valid_7
? ((&_wrbypass_io_T_160) & _GEN_3
? 3'h7
: _wrbypass_io_T_160 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3
? 3'(_wrbypass_io_T_160 + 3'h1)
: 3'(_wrbypass_io_T_160 - 3'h1))
: (&_GEN_4) & _GEN_3
? 3'h7
: _GEN_4 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1);
assign per_bank_not_silent_update_3_1 =
(wrbypass_data_valid_7
? ~((&_wrbypass_io_T_160) & _GEN_3 | _wrbypass_io_T_160 == 3'h0 & ~_GEN_3)
: ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5;
always @(posedge clock) begin
if (_s1_bank_req_1h_T) begin
s1_unhashed_idx <= io_req_bits_pc[40:1];
s1_tag <=
io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_3_folded_hist
^ {io_req_bits_folded_hist_hist_9_folded_hist, 1'h0};
s1_bank_req_1h_0 <= s0_bank_req_1h_0;
s1_bank_req_1h_1 <= s0_bank_req_1h_1;
s1_bank_req_1h_2 <= s0_bank_req_1h_2;
s1_bank_req_1h_3 <= &(s0_idx[1:0]);
end
if (io_req_valid) begin
s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0;
s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1;
s1_bank_has_write_on_this_req_2 <= _s1_bank_has_write_on_this_req_WIRE_2;
s1_bank_has_write_on_this_req_3 <= _s1_bank_has_write_on_this_req_WIRE_3;
end
end // always @(posedge)
always @(posedge clock or posedge reset) begin
if (reset)
powerOnResetState <= 1'h1;
else
powerOnResetState <=
~(_us_io_r_req_ready & _table_banks_0_io_r_req_ready
& _table_banks_1_io_r_req_ready & _table_banks_2_io_r_req_ready
& _table_banks_3_io_r_req_ready) & powerOnResetState;
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:3];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin
_RANDOM[i[1:0]] = `RANDOM;
end
s1_unhashed_idx = {_RANDOM[2'h0], _RANDOM[2'h1][7:0]};
s1_tag = _RANDOM[2'h1][26:19];
s1_bank_req_1h_0 = _RANDOM[2'h3][4];
s1_bank_req_1h_1 = _RANDOM[2'h3][5];
s1_bank_req_1h_2 = _RANDOM[2'h3][6];
s1_bank_req_1h_3 = _RANDOM[2'h3][7];
s1_bank_has_write_on_this_req_0 = _RANDOM[2'h3][8];
s1_bank_has_write_on_this_req_1 = _RANDOM[2'h3][9];
s1_bank_has_write_on_this_req_2 = _RANDOM[2'h3][10];
s1_bank_has_write_on_this_req_3 = _RANDOM[2'h3][11];
powerOnResetState = _RANDOM[2'h3][12];
`endif // RANDOMIZE_REG_INIT
if (reset)
powerOnResetState = 1'h1;
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
FoldedSRAMTemplate us (
.clock (clock),
.reset (reset),
.io_r_req_ready (_us_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T),
.io_r_req_bits_setIdx (s0_idx),
.io_r_resp_data_0 (_us_io_r_resp_data_0),
.io_r_resp_data_1 (_us_io_r_resp_data_1),
.io_w_req_valid
(_us_extra_reset_T_1 & (io_update_uMask_0 | io_update_uMask_1)),
.io_w_req_bits_setIdx (update_idx),
.io_w_req_bits_data_0
(~(io_update_pc[1]) & io_update_us_0 | io_update_pc[1] & io_update_us_1),
.io_w_req_bits_data_1
(io_update_pc[1] & io_update_us_0 | ~(io_update_pc[1]) & io_update_us_1),
.io_w_req_bits_waymask
({io_update_pc[1] & io_update_uMask_0 | ~(io_update_pc[1]) & io_update_uMask_1,
~(io_update_pc[1]) & io_update_uMask_0 | io_update_pc[1] & io_update_uMask_1}),
.extra_reset
((io_update_reset_u_0 | io_update_reset_u_1) & _us_extra_reset_T_1)
);
FoldedSRAMTemplate_1 table_banks_0 (
.clock (clock),
.reset (reset),
.io_r_req_ready (_table_banks_0_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_0),
.io_r_req_bits_setIdx (s0_idx[10:2]),
.io_r_resp_data_0_valid (_table_banks_0_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (_table_banks_0_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_table_banks_0_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_table_banks_0_io_r_resp_data_1_ctr),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0),
.io_w_req_bits_setIdx (update_idx[10:2]),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_0_0_ctr),
.io_w_req_bits_data_1_tag (update_tag),
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_0_1_ctr),
.io_w_req_bits_waymask (per_bank_update_way_mask_0)
);
FoldedSRAMTemplate_1 table_banks_1 (
.clock (clock),
.reset (reset),
.io_r_req_ready (_table_banks_1_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_1),
.io_r_req_bits_setIdx (s0_idx[10:2]),
.io_r_resp_data_0_valid (_table_banks_1_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (_table_banks_1_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_table_banks_1_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_table_banks_1_io_r_resp_data_1_ctr),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1),
.io_w_req_bits_setIdx (update_idx[10:2]),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_1_0_ctr),
.io_w_req_bits_data_1_tag (update_tag),
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_1_1_ctr),
.io_w_req_bits_waymask (per_bank_update_way_mask_1)
);
FoldedSRAMTemplate_1 table_banks_2 (
.clock (clock),
.reset (reset),
.io_r_req_ready (_table_banks_2_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_2),
.io_r_req_bits_setIdx (s0_idx[10:2]),
.io_r_resp_data_0_valid (_table_banks_2_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_2_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_2_io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (_table_banks_2_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_table_banks_2_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_table_banks_2_io_r_resp_data_1_ctr),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_2),
.io_w_req_bits_setIdx (update_idx[10:2]),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_2_0_ctr),
.io_w_req_bits_data_1_tag (update_tag),
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_2_1_ctr),
.io_w_req_bits_waymask (per_bank_update_way_mask_2)
);
FoldedSRAMTemplate_1 table_banks_3 (
.clock (clock),
.reset (reset),
.io_r_req_ready (_table_banks_3_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T & (&(s0_idx[1:0]))),
.io_r_req_bits_setIdx (s0_idx[10:2]),
.io_r_resp_data_0_valid (_table_banks_3_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_3_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_3_io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (_table_banks_3_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_table_banks_3_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_table_banks_3_io_r_resp_data_1_ctr),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_3),
.io_w_req_bits_setIdx (update_idx[10:2]),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_3_0_ctr),
.io_w_req_bits_data_1_tag (update_tag),
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_3_1_ctr),
.io_w_req_bits_waymask (per_bank_update_way_mask_3)
);
WrBypass bank_wrbypasses_0_0 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0 & update_req_bank_1h_0),
.io_write_idx (update_idx[10:2]),
.io_write_data_0
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_0_ctr)
| (io_update_pc[1] ? per_bank_update_wdata_0_1_ctr : 3'h0)),
.io_hit (_bank_wrbypasses_0_0_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_0_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_0_0_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_0_1 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1 & update_req_bank_1h_0),
.io_write_idx (update_idx[10:2]),
.io_write_data_0
((io_update_pc[1] ? per_bank_update_wdata_0_0_ctr : 3'h0)
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_1_ctr)),
.io_hit (_bank_wrbypasses_0_1_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_0_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_0_1_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_1_0 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0 & update_req_bank_1h_1),
.io_write_idx (update_idx[10:2]),
.io_write_data_0
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_0_ctr)
| (io_update_pc[1] ? per_bank_update_wdata_1_1_ctr : 3'h0)),
.io_hit (_bank_wrbypasses_1_0_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_1_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_1_0_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_1_1 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1 & update_req_bank_1h_1),
.io_write_idx (update_idx[10:2]),
.io_write_data_0
((io_update_pc[1] ? per_bank_update_wdata_1_0_ctr : 3'h0)
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_1_ctr)),
.io_hit (_bank_wrbypasses_1_1_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_1_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_1_1_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_2_0 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0 & update_req_bank_1h_2),
.io_write_idx (update_idx[10:2]),
.io_write_data_0
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_0_ctr)
| (io_update_pc[1] ? per_bank_update_wdata_2_1_ctr : 3'h0)),
.io_hit (_bank_wrbypasses_2_0_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_2_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_2_0_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_2_1 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1 & update_req_bank_1h_2),
.io_write_idx (update_idx[10:2]),
.io_write_data_0
((io_update_pc[1] ? per_bank_update_wdata_2_0_ctr : 3'h0)
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_1_ctr)),
.io_hit (_bank_wrbypasses_2_1_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_2_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_2_1_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_3_0 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0 & (&(update_idx[1:0]))),
.io_write_idx (update_idx[10:2]),
.io_write_data_0
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_0_ctr)
| (io_update_pc[1] ? per_bank_update_wdata_3_1_ctr : 3'h0)),
.io_hit (_bank_wrbypasses_3_0_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_3_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_3_0_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_3_1 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1 & (&(update_idx[1:0]))),
.io_write_idx (update_idx[10:2]),
.io_write_data_0
((io_update_pc[1] ? per_bank_update_wdata_3_0_ctr : 3'h0)
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_1_ctr)),
.io_hit (_bank_wrbypasses_3_1_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_3_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_3_1_io_hit_data_0_bits)
);
assign io_req_ready = ~powerOnResetState;
assign io_resps_0_valid =
~(s1_unhashed_idx[0]) & _hit_selected_T_6 | s1_unhashed_idx[0] & _hit_selected_T_13;
assign io_resps_0_bits_ctr =
(s1_unhashed_idx[0] ? 3'h0 : _resp_selected_T_6)
| (s1_unhashed_idx[0] ? _resp_selected_T_27 : 3'h0);
assign io_resps_0_bits_u =
~(s1_unhashed_idx[0]) & _us_io_r_resp_data_0 | s1_unhashed_idx[0]
& _us_io_r_resp_data_1;
assign io_resps_0_bits_unconf =
~(s1_unhashed_idx[0]) & _unconf_selected_T_6 | s1_unhashed_idx[0]
& _unconf_selected_T_13;
assign io_resps_1_valid =
s1_unhashed_idx[0] & _hit_selected_T_6 | ~(s1_unhashed_idx[0]) & _hit_selected_T_13;
assign io_resps_1_bits_ctr =
(s1_unhashed_idx[0] ? _resp_selected_T_6 : 3'h0)
| (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_T_27);
assign io_resps_1_bits_u =
s1_unhashed_idx[0] & _us_io_r_resp_data_0 | ~(s1_unhashed_idx[0])
& _us_io_r_resp_data_1;
assign io_resps_1_bits_unconf =
s1_unhashed_idx[0] & _unconf_selected_T_6 | ~(s1_unhashed_idx[0])
& _unconf_selected_T_13;
endmodule

754
rtl/BPUTop/TageTable_3.sv
View File

@ -1,754 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module TageTable_3(
input clock,
input reset,
output io_req_ready,
input io_req_valid,
input [40:0] io_req_bits_pc,
input [10:0] io_req_bits_folded_hist_hist_16_folded_hist,
input [7:0] io_req_bits_folded_hist_hist_8_folded_hist,
input [6:0] io_req_bits_folded_hist_hist_5_folded_hist,
output io_resps_0_valid,
output [2:0] io_resps_0_bits_ctr,
output io_resps_0_bits_u,
output io_resps_0_bits_unconf,
output io_resps_1_valid,
output [2:0] io_resps_1_bits_ctr,
output io_resps_1_bits_u,
output io_resps_1_bits_unconf,
input [40:0] io_update_pc,
input [10:0] io_update_folded_hist_hist_16_folded_hist,
input [7:0] io_update_folded_hist_hist_8_folded_hist,
input [6:0] io_update_folded_hist_hist_5_folded_hist,
input io_update_mask_0,
input io_update_mask_1,
input io_update_takens_0,
input io_update_takens_1,
input io_update_alloc_0,
input io_update_alloc_1,
input [2:0] io_update_oldCtrs_0,
input [2:0] io_update_oldCtrs_1,
input io_update_uMask_0,
input io_update_uMask_1,
input io_update_us_0,
input io_update_us_1,
input io_update_reset_u_0,
input io_update_reset_u_1
);
wire per_bank_not_silent_update_3_1;
wire per_bank_not_silent_update_3_0;
wire per_bank_not_silent_update_2_1;
wire per_bank_not_silent_update_2_0;
wire per_bank_not_silent_update_1_1;
wire per_bank_not_silent_update_1_0;
wire per_bank_not_silent_update_0_1;
wire per_bank_not_silent_update_0_0;
reg powerOnResetState;
wire _resp_invalid_by_write_T_6;
wire _bank_wrbypasses_3_1_io_hit;
wire _bank_wrbypasses_3_1_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_3_1_io_hit_data_0_bits;
wire _bank_wrbypasses_3_0_io_hit;
wire _bank_wrbypasses_3_0_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_3_0_io_hit_data_0_bits;
wire _bank_wrbypasses_2_1_io_hit;
wire _bank_wrbypasses_2_1_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_2_1_io_hit_data_0_bits;
wire _bank_wrbypasses_2_0_io_hit;
wire _bank_wrbypasses_2_0_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_2_0_io_hit_data_0_bits;
wire _bank_wrbypasses_1_1_io_hit;
wire _bank_wrbypasses_1_1_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_1_1_io_hit_data_0_bits;
wire _bank_wrbypasses_1_0_io_hit;
wire _bank_wrbypasses_1_0_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_1_0_io_hit_data_0_bits;
wire _bank_wrbypasses_0_1_io_hit;
wire _bank_wrbypasses_0_1_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_0_1_io_hit_data_0_bits;
wire _bank_wrbypasses_0_0_io_hit;
wire _bank_wrbypasses_0_0_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_0_0_io_hit_data_0_bits;
wire _table_banks_3_io_r_req_ready;
wire _table_banks_3_io_r_resp_data_0_valid;
wire [7:0] _table_banks_3_io_r_resp_data_0_tag;
wire [2:0] _table_banks_3_io_r_resp_data_0_ctr;
wire _table_banks_3_io_r_resp_data_1_valid;
wire [7:0] _table_banks_3_io_r_resp_data_1_tag;
wire [2:0] _table_banks_3_io_r_resp_data_1_ctr;
wire _table_banks_2_io_r_req_ready;
wire _table_banks_2_io_r_resp_data_0_valid;
wire [7:0] _table_banks_2_io_r_resp_data_0_tag;
wire [2:0] _table_banks_2_io_r_resp_data_0_ctr;
wire _table_banks_2_io_r_resp_data_1_valid;
wire [7:0] _table_banks_2_io_r_resp_data_1_tag;
wire [2:0] _table_banks_2_io_r_resp_data_1_ctr;
wire _table_banks_1_io_r_req_ready;
wire _table_banks_1_io_r_resp_data_0_valid;
wire [7:0] _table_banks_1_io_r_resp_data_0_tag;
wire [2:0] _table_banks_1_io_r_resp_data_0_ctr;
wire _table_banks_1_io_r_resp_data_1_valid;
wire [7:0] _table_banks_1_io_r_resp_data_1_tag;
wire [2:0] _table_banks_1_io_r_resp_data_1_ctr;
wire _table_banks_0_io_r_req_ready;
wire _table_banks_0_io_r_resp_data_0_valid;
wire [7:0] _table_banks_0_io_r_resp_data_0_tag;
wire [2:0] _table_banks_0_io_r_resp_data_0_ctr;
wire _table_banks_0_io_r_resp_data_1_valid;
wire [7:0] _table_banks_0_io_r_resp_data_1_tag;
wire [2:0] _table_banks_0_io_r_resp_data_1_ctr;
wire _us_io_r_req_ready;
wire _us_io_r_resp_data_0;
wire _us_io_r_resp_data_1;
wire _us_extra_reset_T_1 = io_update_mask_0 | io_update_mask_1;
wire [10:0] s0_idx = io_req_bits_pc[11:1] ^ io_req_bits_folded_hist_hist_16_folded_hist;
wire s0_bank_req_1h_0 = s0_idx[1:0] == 2'h0;
wire s0_bank_req_1h_1 = s0_idx[1:0] == 2'h1;
wire s0_bank_req_1h_2 = s0_idx[1:0] == 2'h2;
wire _s1_bank_req_1h_T = ~powerOnResetState & io_req_valid;
reg [39:0] s1_unhashed_idx;
reg [7:0] s1_tag;
reg s1_bank_req_1h_0;
reg s1_bank_req_1h_1;
reg s1_bank_req_1h_2;
reg s1_bank_req_1h_3;
reg s1_bank_has_write_on_this_req_0;
reg s1_bank_has_write_on_this_req_1;
reg s1_bank_has_write_on_this_req_2;
reg s1_bank_has_write_on_this_req_3;
wire [2:0] _resp_selected_T_6 =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 3'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 3'h0)
| (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_0_ctr : 3'h0)
| (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_0_ctr : 3'h0);
wire [2:0] _resp_selected_T_27 =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_1_ctr : 3'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_1_ctr : 3'h0)
| (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_1_ctr : 3'h0)
| (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_1_ctr : 3'h0);
wire _unconf_selected_T_6 =
s1_bank_req_1h_0
& (_table_banks_0_io_r_resp_data_0_ctr == 3'h4
| _table_banks_0_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_1
& (_table_banks_1_io_r_resp_data_0_ctr == 3'h4
| _table_banks_1_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_2
& (_table_banks_2_io_r_resp_data_0_ctr == 3'h4
| _table_banks_2_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_3
& (_table_banks_3_io_r_resp_data_0_ctr == 3'h4
| _table_banks_3_io_r_resp_data_0_ctr == 3'h3);
wire _unconf_selected_T_13 =
s1_bank_req_1h_0
& (_table_banks_0_io_r_resp_data_1_ctr == 3'h4
| _table_banks_0_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_1
& (_table_banks_1_io_r_resp_data_1_ctr == 3'h4
| _table_banks_1_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_2
& (_table_banks_2_io_r_resp_data_1_ctr == 3'h4
| _table_banks_2_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_3
& (_table_banks_3_io_r_resp_data_1_ctr == 3'h4
| _table_banks_3_io_r_resp_data_1_ctr == 3'h3);
wire _hit_selected_T_6 =
s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_0_tag == s1_tag
& _table_banks_0_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6
| s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_0_tag == s1_tag
& _table_banks_1_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6
| s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_0_tag == s1_tag
& _table_banks_2_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6
| s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_0_tag == s1_tag
& _table_banks_3_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6;
wire _hit_selected_T_13 =
s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_1_tag == s1_tag
& _table_banks_0_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6
| s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_1_tag == s1_tag
& _table_banks_1_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6
| s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_1_tag == s1_tag
& _table_banks_2_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6
| s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_1_tag == s1_tag
& _table_banks_3_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6;
assign _resp_invalid_by_write_T_6 =
s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1
& s1_bank_has_write_on_this_req_1 | s1_bank_req_1h_2 & s1_bank_has_write_on_this_req_2
| s1_bank_req_1h_3 & s1_bank_has_write_on_this_req_3;
wire [10:0] update_idx = io_update_pc[11:1] ^ io_update_folded_hist_hist_16_folded_hist;
wire [7:0] update_tag =
io_update_pc[8:1] ^ io_update_folded_hist_hist_8_folded_hist
^ {io_update_folded_hist_hist_5_folded_hist, 1'h0};
wire update_req_bank_1h_0 = update_idx[1:0] == 2'h0;
wire update_req_bank_1h_1 = update_idx[1:0] == 2'h1;
wire update_req_bank_1h_2 = update_idx[1:0] == 2'h2;
wire [1:0] per_bank_update_way_mask_0 =
{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
& per_bank_not_silent_update_0_1,
(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
& per_bank_not_silent_update_0_0};
wire [1:0] per_bank_update_way_mask_1 =
{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
& per_bank_not_silent_update_1_1,
(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
& per_bank_not_silent_update_1_0};
wire [1:0] per_bank_update_way_mask_2 =
{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
& per_bank_not_silent_update_2_1,
(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
& per_bank_not_silent_update_2_0};
wire [1:0] per_bank_update_way_mask_3 =
{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
& per_bank_not_silent_update_3_1,
(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
& per_bank_not_silent_update_3_0};
wire _s1_bank_has_write_on_this_req_WIRE_0 =
(|per_bank_update_way_mask_0) & update_req_bank_1h_0;
wire _s1_bank_has_write_on_this_req_WIRE_1 =
(|per_bank_update_way_mask_1) & update_req_bank_1h_1;
wire _s1_bank_has_write_on_this_req_WIRE_2 =
(|per_bank_update_way_mask_2) & update_req_bank_1h_2;
wire _s1_bank_has_write_on_this_req_WIRE_3 =
(|per_bank_update_way_mask_3) & (&(update_idx[1:0]));
wire [2:0] _wrbypass_io_T_6 =
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _bank_wrbypasses_0_1_io_hit_data_0_bits : 3'h0);
wire wrbypass_data_valid =
(~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit | io_update_pc[1]
& _bank_wrbypasses_0_1_io_hit)
& (~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit_data_0_valid | io_update_pc[1]
& _bank_wrbypasses_0_1_io_hit_data_0_valid);
wire _GEN = io_update_pc[1] ? io_update_takens_1 : io_update_takens_0;
wire [2:0] _GEN_0 = io_update_pc[1] ? io_update_oldCtrs_1 : io_update_oldCtrs_0;
wire _GEN_1 = (|_GEN_0) | _GEN;
wire _GEN_2 = io_update_pc[1] ? io_update_alloc_1 : io_update_alloc_0;
wire [2:0] per_bank_update_wdata_0_0_ctr =
_GEN_2
? (_GEN ? 3'h4 : 3'h3)
: wrbypass_data_valid
? ((&_wrbypass_io_T_6) & _GEN
? 3'h7
: _wrbypass_io_T_6 == 3'h0 & ~_GEN
? 3'h0
: _GEN ? 3'(_wrbypass_io_T_6 + 3'h1) : 3'(_wrbypass_io_T_6 - 3'h1))
: (&_GEN_0) & _GEN
? 3'h7
: _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0;
assign per_bank_not_silent_update_0_0 =
(wrbypass_data_valid
? ~((&_wrbypass_io_T_6) & _GEN | _wrbypass_io_T_6 == 3'h0 & ~_GEN)
: ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2;
wire [2:0] _wrbypass_io_T_28 =
(io_update_pc[1] ? _bank_wrbypasses_0_0_io_hit_data_0_bits : 3'h0)
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_1_io_hit_data_0_bits);
wire wrbypass_data_valid_1 =
(io_update_pc[1] & _bank_wrbypasses_0_0_io_hit | ~(io_update_pc[1])
& _bank_wrbypasses_0_1_io_hit)
& (io_update_pc[1] & _bank_wrbypasses_0_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _bank_wrbypasses_0_1_io_hit_data_0_valid);
wire _GEN_3 = io_update_pc[1] ? io_update_takens_0 : io_update_takens_1;
wire [2:0] _GEN_4 = io_update_pc[1] ? io_update_oldCtrs_0 : io_update_oldCtrs_1;
wire _GEN_5 = io_update_pc[1] ? io_update_alloc_0 : io_update_alloc_1;
wire [2:0] per_bank_update_wdata_0_1_ctr =
_GEN_5
? (_GEN_3 ? 3'h4 : 3'h3)
: wrbypass_data_valid_1
? ((&_wrbypass_io_T_28) & _GEN_3
? 3'h7
: _wrbypass_io_T_28 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3 ? 3'(_wrbypass_io_T_28 + 3'h1) : 3'(_wrbypass_io_T_28 - 3'h1))
: (&_GEN_4) & _GEN_3
? 3'h7
: _GEN_4 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1);
assign per_bank_not_silent_update_0_1 =
(wrbypass_data_valid_1
? ~((&_wrbypass_io_T_28) & _GEN_3 | _wrbypass_io_T_28 == 3'h0 & ~_GEN_3)
: ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5;
wire [2:0] _wrbypass_io_T_50 =
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _bank_wrbypasses_1_1_io_hit_data_0_bits : 3'h0);
wire wrbypass_data_valid_2 =
(~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit | io_update_pc[1]
& _bank_wrbypasses_1_1_io_hit)
& (~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit_data_0_valid | io_update_pc[1]
& _bank_wrbypasses_1_1_io_hit_data_0_valid);
wire [2:0] per_bank_update_wdata_1_0_ctr =
_GEN_2
? (_GEN ? 3'h4 : 3'h3)
: wrbypass_data_valid_2
? ((&_wrbypass_io_T_50) & _GEN
? 3'h7
: _wrbypass_io_T_50 == 3'h0 & ~_GEN
? 3'h0
: _GEN ? 3'(_wrbypass_io_T_50 + 3'h1) : 3'(_wrbypass_io_T_50 - 3'h1))
: (&_GEN_0) & _GEN
? 3'h7
: _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0;
assign per_bank_not_silent_update_1_0 =
(wrbypass_data_valid_2
? ~((&_wrbypass_io_T_50) & _GEN | _wrbypass_io_T_50 == 3'h0 & ~_GEN)
: ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2;
wire [2:0] _wrbypass_io_T_72 =
(io_update_pc[1] ? _bank_wrbypasses_1_0_io_hit_data_0_bits : 3'h0)
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_1_io_hit_data_0_bits);
wire wrbypass_data_valid_3 =
(io_update_pc[1] & _bank_wrbypasses_1_0_io_hit | ~(io_update_pc[1])
& _bank_wrbypasses_1_1_io_hit)
& (io_update_pc[1] & _bank_wrbypasses_1_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _bank_wrbypasses_1_1_io_hit_data_0_valid);
wire [2:0] per_bank_update_wdata_1_1_ctr =
_GEN_5
? (_GEN_3 ? 3'h4 : 3'h3)
: wrbypass_data_valid_3
? ((&_wrbypass_io_T_72) & _GEN_3
? 3'h7
: _wrbypass_io_T_72 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3 ? 3'(_wrbypass_io_T_72 + 3'h1) : 3'(_wrbypass_io_T_72 - 3'h1))
: (&_GEN_4) & _GEN_3
? 3'h7
: _GEN_4 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1);
assign per_bank_not_silent_update_1_1 =
(wrbypass_data_valid_3
? ~((&_wrbypass_io_T_72) & _GEN_3 | _wrbypass_io_T_72 == 3'h0 & ~_GEN_3)
: ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5;
wire [2:0] _wrbypass_io_T_94 =
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _bank_wrbypasses_2_1_io_hit_data_0_bits : 3'h0);
wire wrbypass_data_valid_4 =
(~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit | io_update_pc[1]
& _bank_wrbypasses_2_1_io_hit)
& (~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit_data_0_valid | io_update_pc[1]
& _bank_wrbypasses_2_1_io_hit_data_0_valid);
wire [2:0] per_bank_update_wdata_2_0_ctr =
_GEN_2
? (_GEN ? 3'h4 : 3'h3)
: wrbypass_data_valid_4
? ((&_wrbypass_io_T_94) & _GEN
? 3'h7
: _wrbypass_io_T_94 == 3'h0 & ~_GEN
? 3'h0
: _GEN ? 3'(_wrbypass_io_T_94 + 3'h1) : 3'(_wrbypass_io_T_94 - 3'h1))
: (&_GEN_0) & _GEN
? 3'h7
: _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0;
assign per_bank_not_silent_update_2_0 =
(wrbypass_data_valid_4
? ~((&_wrbypass_io_T_94) & _GEN | _wrbypass_io_T_94 == 3'h0 & ~_GEN)
: ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2;
wire [2:0] _wrbypass_io_T_116 =
(io_update_pc[1] ? _bank_wrbypasses_2_0_io_hit_data_0_bits : 3'h0)
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_1_io_hit_data_0_bits);
wire wrbypass_data_valid_5 =
(io_update_pc[1] & _bank_wrbypasses_2_0_io_hit | ~(io_update_pc[1])
& _bank_wrbypasses_2_1_io_hit)
& (io_update_pc[1] & _bank_wrbypasses_2_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _bank_wrbypasses_2_1_io_hit_data_0_valid);
wire [2:0] per_bank_update_wdata_2_1_ctr =
_GEN_5
? (_GEN_3 ? 3'h4 : 3'h3)
: wrbypass_data_valid_5
? ((&_wrbypass_io_T_116) & _GEN_3
? 3'h7
: _wrbypass_io_T_116 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3
? 3'(_wrbypass_io_T_116 + 3'h1)
: 3'(_wrbypass_io_T_116 - 3'h1))
: (&_GEN_4) & _GEN_3
? 3'h7
: _GEN_4 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1);
assign per_bank_not_silent_update_2_1 =
(wrbypass_data_valid_5
? ~((&_wrbypass_io_T_116) & _GEN_3 | _wrbypass_io_T_116 == 3'h0 & ~_GEN_3)
: ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5;
wire [2:0] _wrbypass_io_T_138 =
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _bank_wrbypasses_3_1_io_hit_data_0_bits : 3'h0);
wire wrbypass_data_valid_6 =
(~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit | io_update_pc[1]
& _bank_wrbypasses_3_1_io_hit)
& (~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit_data_0_valid | io_update_pc[1]
& _bank_wrbypasses_3_1_io_hit_data_0_valid);
wire [2:0] per_bank_update_wdata_3_0_ctr =
_GEN_2
? (_GEN ? 3'h4 : 3'h3)
: wrbypass_data_valid_6
? ((&_wrbypass_io_T_138) & _GEN
? 3'h7
: _wrbypass_io_T_138 == 3'h0 & ~_GEN
? 3'h0
: _GEN ? 3'(_wrbypass_io_T_138 + 3'h1) : 3'(_wrbypass_io_T_138 - 3'h1))
: (&_GEN_0) & _GEN
? 3'h7
: _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0;
assign per_bank_not_silent_update_3_0 =
(wrbypass_data_valid_6
? ~((&_wrbypass_io_T_138) & _GEN | _wrbypass_io_T_138 == 3'h0 & ~_GEN)
: ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2;
wire [2:0] _wrbypass_io_T_160 =
(io_update_pc[1] ? _bank_wrbypasses_3_0_io_hit_data_0_bits : 3'h0)
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_1_io_hit_data_0_bits);
wire wrbypass_data_valid_7 =
(io_update_pc[1] & _bank_wrbypasses_3_0_io_hit | ~(io_update_pc[1])
& _bank_wrbypasses_3_1_io_hit)
& (io_update_pc[1] & _bank_wrbypasses_3_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _bank_wrbypasses_3_1_io_hit_data_0_valid);
wire [2:0] per_bank_update_wdata_3_1_ctr =
_GEN_5
? (_GEN_3 ? 3'h4 : 3'h3)
: wrbypass_data_valid_7
? ((&_wrbypass_io_T_160) & _GEN_3
? 3'h7
: _wrbypass_io_T_160 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3
? 3'(_wrbypass_io_T_160 + 3'h1)
: 3'(_wrbypass_io_T_160 - 3'h1))
: (&_GEN_4) & _GEN_3
? 3'h7
: _GEN_4 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1);
assign per_bank_not_silent_update_3_1 =
(wrbypass_data_valid_7
? ~((&_wrbypass_io_T_160) & _GEN_3 | _wrbypass_io_T_160 == 3'h0 & ~_GEN_3)
: ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5;
always @(posedge clock) begin
if (_s1_bank_req_1h_T) begin
s1_unhashed_idx <= io_req_bits_pc[40:1];
s1_tag <=
io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_8_folded_hist
^ {io_req_bits_folded_hist_hist_5_folded_hist, 1'h0};
s1_bank_req_1h_0 <= s0_bank_req_1h_0;
s1_bank_req_1h_1 <= s0_bank_req_1h_1;
s1_bank_req_1h_2 <= s0_bank_req_1h_2;
s1_bank_req_1h_3 <= &(s0_idx[1:0]);
end
if (io_req_valid) begin
s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0;
s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1;
s1_bank_has_write_on_this_req_2 <= _s1_bank_has_write_on_this_req_WIRE_2;
s1_bank_has_write_on_this_req_3 <= _s1_bank_has_write_on_this_req_WIRE_3;
end
end // always @(posedge)
always @(posedge clock or posedge reset) begin
if (reset)
powerOnResetState <= 1'h1;
else
powerOnResetState <=
~(_us_io_r_req_ready & _table_banks_0_io_r_req_ready
& _table_banks_1_io_r_req_ready & _table_banks_2_io_r_req_ready
& _table_banks_3_io_r_req_ready) & powerOnResetState;
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:3];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin
_RANDOM[i[1:0]] = `RANDOM;
end
s1_unhashed_idx = {_RANDOM[2'h0], _RANDOM[2'h1][7:0]};
s1_tag = _RANDOM[2'h1][26:19];
s1_bank_req_1h_0 = _RANDOM[2'h3][4];
s1_bank_req_1h_1 = _RANDOM[2'h3][5];
s1_bank_req_1h_2 = _RANDOM[2'h3][6];
s1_bank_req_1h_3 = _RANDOM[2'h3][7];
s1_bank_has_write_on_this_req_0 = _RANDOM[2'h3][8];
s1_bank_has_write_on_this_req_1 = _RANDOM[2'h3][9];
s1_bank_has_write_on_this_req_2 = _RANDOM[2'h3][10];
s1_bank_has_write_on_this_req_3 = _RANDOM[2'h3][11];
powerOnResetState = _RANDOM[2'h3][12];
`endif // RANDOMIZE_REG_INIT
if (reset)
powerOnResetState = 1'h1;
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
FoldedSRAMTemplate us (
.clock (clock),
.reset (reset),
.io_r_req_ready (_us_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T),
.io_r_req_bits_setIdx (s0_idx),
.io_r_resp_data_0 (_us_io_r_resp_data_0),
.io_r_resp_data_1 (_us_io_r_resp_data_1),
.io_w_req_valid
(_us_extra_reset_T_1 & (io_update_uMask_0 | io_update_uMask_1)),
.io_w_req_bits_setIdx (update_idx),
.io_w_req_bits_data_0
(~(io_update_pc[1]) & io_update_us_0 | io_update_pc[1] & io_update_us_1),
.io_w_req_bits_data_1
(io_update_pc[1] & io_update_us_0 | ~(io_update_pc[1]) & io_update_us_1),
.io_w_req_bits_waymask
({io_update_pc[1] & io_update_uMask_0 | ~(io_update_pc[1]) & io_update_uMask_1,
~(io_update_pc[1]) & io_update_uMask_0 | io_update_pc[1] & io_update_uMask_1}),
.extra_reset
((io_update_reset_u_0 | io_update_reset_u_1) & _us_extra_reset_T_1)
);
FoldedSRAMTemplate_1 table_banks_0 (
.clock (clock),
.reset (reset),
.io_r_req_ready (_table_banks_0_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_0),
.io_r_req_bits_setIdx (s0_idx[10:2]),
.io_r_resp_data_0_valid (_table_banks_0_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (_table_banks_0_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_table_banks_0_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_table_banks_0_io_r_resp_data_1_ctr),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0),
.io_w_req_bits_setIdx (update_idx[10:2]),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_0_0_ctr),
.io_w_req_bits_data_1_tag (update_tag),
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_0_1_ctr),
.io_w_req_bits_waymask (per_bank_update_way_mask_0)
);
FoldedSRAMTemplate_1 table_banks_1 (
.clock (clock),
.reset (reset),
.io_r_req_ready (_table_banks_1_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_1),
.io_r_req_bits_setIdx (s0_idx[10:2]),
.io_r_resp_data_0_valid (_table_banks_1_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (_table_banks_1_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_table_banks_1_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_table_banks_1_io_r_resp_data_1_ctr),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1),
.io_w_req_bits_setIdx (update_idx[10:2]),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_1_0_ctr),
.io_w_req_bits_data_1_tag (update_tag),
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_1_1_ctr),
.io_w_req_bits_waymask (per_bank_update_way_mask_1)
);
FoldedSRAMTemplate_1 table_banks_2 (
.clock (clock),
.reset (reset),
.io_r_req_ready (_table_banks_2_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_2),
.io_r_req_bits_setIdx (s0_idx[10:2]),
.io_r_resp_data_0_valid (_table_banks_2_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_2_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_2_io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (_table_banks_2_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_table_banks_2_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_table_banks_2_io_r_resp_data_1_ctr),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_2),
.io_w_req_bits_setIdx (update_idx[10:2]),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_2_0_ctr),
.io_w_req_bits_data_1_tag (update_tag),
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_2_1_ctr),
.io_w_req_bits_waymask (per_bank_update_way_mask_2)
);
FoldedSRAMTemplate_1 table_banks_3 (
.clock (clock),
.reset (reset),
.io_r_req_ready (_table_banks_3_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T & (&(s0_idx[1:0]))),
.io_r_req_bits_setIdx (s0_idx[10:2]),
.io_r_resp_data_0_valid (_table_banks_3_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_3_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_3_io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (_table_banks_3_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_table_banks_3_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_table_banks_3_io_r_resp_data_1_ctr),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_3),
.io_w_req_bits_setIdx (update_idx[10:2]),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_3_0_ctr),
.io_w_req_bits_data_1_tag (update_tag),
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_3_1_ctr),
.io_w_req_bits_waymask (per_bank_update_way_mask_3)
);
WrBypass bank_wrbypasses_0_0 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0 & update_req_bank_1h_0),
.io_write_idx (update_idx[10:2]),
.io_write_data_0
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_0_ctr)
| (io_update_pc[1] ? per_bank_update_wdata_0_1_ctr : 3'h0)),
.io_hit (_bank_wrbypasses_0_0_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_0_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_0_0_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_0_1 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1 & update_req_bank_1h_0),
.io_write_idx (update_idx[10:2]),
.io_write_data_0
((io_update_pc[1] ? per_bank_update_wdata_0_0_ctr : 3'h0)
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_1_ctr)),
.io_hit (_bank_wrbypasses_0_1_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_0_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_0_1_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_1_0 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0 & update_req_bank_1h_1),
.io_write_idx (update_idx[10:2]),
.io_write_data_0
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_0_ctr)
| (io_update_pc[1] ? per_bank_update_wdata_1_1_ctr : 3'h0)),
.io_hit (_bank_wrbypasses_1_0_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_1_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_1_0_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_1_1 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1 & update_req_bank_1h_1),
.io_write_idx (update_idx[10:2]),
.io_write_data_0
((io_update_pc[1] ? per_bank_update_wdata_1_0_ctr : 3'h0)
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_1_ctr)),
.io_hit (_bank_wrbypasses_1_1_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_1_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_1_1_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_2_0 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0 & update_req_bank_1h_2),
.io_write_idx (update_idx[10:2]),
.io_write_data_0
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_0_ctr)
| (io_update_pc[1] ? per_bank_update_wdata_2_1_ctr : 3'h0)),
.io_hit (_bank_wrbypasses_2_0_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_2_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_2_0_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_2_1 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1 & update_req_bank_1h_2),
.io_write_idx (update_idx[10:2]),
.io_write_data_0
((io_update_pc[1] ? per_bank_update_wdata_2_0_ctr : 3'h0)
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_1_ctr)),
.io_hit (_bank_wrbypasses_2_1_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_2_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_2_1_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_3_0 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0 & (&(update_idx[1:0]))),
.io_write_idx (update_idx[10:2]),
.io_write_data_0
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_0_ctr)
| (io_update_pc[1] ? per_bank_update_wdata_3_1_ctr : 3'h0)),
.io_hit (_bank_wrbypasses_3_0_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_3_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_3_0_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_3_1 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1 & (&(update_idx[1:0]))),
.io_write_idx (update_idx[10:2]),
.io_write_data_0
((io_update_pc[1] ? per_bank_update_wdata_3_0_ctr : 3'h0)
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_1_ctr)),
.io_hit (_bank_wrbypasses_3_1_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_3_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_3_1_io_hit_data_0_bits)
);
assign io_req_ready = ~powerOnResetState;
assign io_resps_0_valid =
~(s1_unhashed_idx[0]) & _hit_selected_T_6 | s1_unhashed_idx[0] & _hit_selected_T_13;
assign io_resps_0_bits_ctr =
(s1_unhashed_idx[0] ? 3'h0 : _resp_selected_T_6)
| (s1_unhashed_idx[0] ? _resp_selected_T_27 : 3'h0);
assign io_resps_0_bits_u =
~(s1_unhashed_idx[0]) & _us_io_r_resp_data_0 | s1_unhashed_idx[0]
& _us_io_r_resp_data_1;
assign io_resps_0_bits_unconf =
~(s1_unhashed_idx[0]) & _unconf_selected_T_6 | s1_unhashed_idx[0]
& _unconf_selected_T_13;
assign io_resps_1_valid =
s1_unhashed_idx[0] & _hit_selected_T_6 | ~(s1_unhashed_idx[0]) & _hit_selected_T_13;
assign io_resps_1_bits_ctr =
(s1_unhashed_idx[0] ? _resp_selected_T_6 : 3'h0)
| (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_T_27);
assign io_resps_1_bits_u =
s1_unhashed_idx[0] & _us_io_r_resp_data_0 | ~(s1_unhashed_idx[0])
& _us_io_r_resp_data_1;
assign io_resps_1_bits_unconf =
s1_unhashed_idx[0] & _unconf_selected_T_6 | ~(s1_unhashed_idx[0])
& _unconf_selected_T_13;
endmodule

5910
rtl/BPUTop/Tage_SC.sv
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281
rtl/BPUTop/WrBypass.sv
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@ -1,281 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module WrBypass(
input clock,
input reset,
input io_wen,
input [8:0] io_write_idx,
input [2:0] io_write_data_0,
output io_hit,
output io_hit_data_0_valid,
output [2:0] io_hit_data_0_bits
);
wire _idx_tag_cam_io_r_resp_0_0;
wire _idx_tag_cam_io_r_resp_0_1;
wire _idx_tag_cam_io_r_resp_0_2;
wire _idx_tag_cam_io_r_resp_0_3;
wire _idx_tag_cam_io_r_resp_0_4;
wire _idx_tag_cam_io_r_resp_0_5;
wire _idx_tag_cam_io_r_resp_0_6;
wire _idx_tag_cam_io_r_resp_0_7;
reg valids_0_0;
reg valids_1_0;
reg valids_2_0;
reg valids_3_0;
reg valids_4_0;
reg valids_5_0;
reg valids_6_0;
reg valids_7_0;
reg ever_written_0;
reg ever_written_1;
reg ever_written_2;
reg ever_written_3;
reg ever_written_4;
reg ever_written_5;
reg ever_written_6;
reg ever_written_7;
wire hits_oh_0 = _idx_tag_cam_io_r_resp_0_0 & ever_written_0;
wire hits_oh_1 = _idx_tag_cam_io_r_resp_0_1 & ever_written_1;
wire hits_oh_2 = _idx_tag_cam_io_r_resp_0_2 & ever_written_2;
wire hits_oh_3 = _idx_tag_cam_io_r_resp_0_3 & ever_written_3;
wire hits_oh_4 = _idx_tag_cam_io_r_resp_0_4 & ever_written_4;
wire hits_oh_5 = _idx_tag_cam_io_r_resp_0_5 & ever_written_5;
wire hits_oh_6 = _idx_tag_cam_io_r_resp_0_6 & ever_written_6;
wire hits_oh_7 = _idx_tag_cam_io_r_resp_0_7 & ever_written_7;
wire [2:0] _hit_idx_T_2 =
{hits_oh_7, hits_oh_6, hits_oh_5} | {hits_oh_3, hits_oh_2, hits_oh_1};
wire [2:0] hit_idx =
{|{hits_oh_7, hits_oh_6, hits_oh_5, hits_oh_4},
|(_hit_idx_T_2[2:1]),
_hit_idx_T_2[2] | _hit_idx_T_2[0]};
wire hit =
hits_oh_0 | hits_oh_1 | hits_oh_2 | hits_oh_3 | hits_oh_4 | hits_oh_5 | hits_oh_6
| hits_oh_7;
reg [6:0] state_reg;
wire [2:0] enq_idx =
{state_reg[6],
state_reg[6]
? {state_reg[5], state_reg[5] ? state_reg[4] : state_reg[3]}
: {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]}};
wire [2:0] state_reg_touch_way_sized = hit ? hit_idx : enq_idx;
wire _GEN = enq_idx == 3'h0;
wire _GEN_0 = enq_idx == 3'h1;
wire _GEN_1 = enq_idx == 3'h2;
wire _GEN_2 = enq_idx == 3'h3;
wire _GEN_3 = enq_idx == 3'h4;
wire _GEN_4 = enq_idx == 3'h5;
wire _GEN_5 = enq_idx == 3'h6;
always @(posedge clock or posedge reset) begin
if (reset) begin
valids_0_0 <= 1'h0;
valids_1_0 <= 1'h0;
valids_2_0 <= 1'h0;
valids_3_0 <= 1'h0;
valids_4_0 <= 1'h0;
valids_5_0 <= 1'h0;
valids_6_0 <= 1'h0;
valids_7_0 <= 1'h0;
ever_written_0 <= 1'h0;
ever_written_1 <= 1'h0;
ever_written_2 <= 1'h0;
ever_written_3 <= 1'h0;
ever_written_4 <= 1'h0;
ever_written_5 <= 1'h0;
ever_written_6 <= 1'h0;
ever_written_7 <= 1'h0;
state_reg <= 7'h0;
end
else begin
if (io_wen) begin
if (hit) begin
valids_0_0 <= hit_idx == 3'h0 | valids_0_0;
valids_1_0 <= hit_idx == 3'h1 | valids_1_0;
valids_2_0 <= hit_idx == 3'h2 | valids_2_0;
valids_3_0 <= hit_idx == 3'h3 | valids_3_0;
valids_4_0 <= hit_idx == 3'h4 | valids_4_0;
valids_5_0 <= hit_idx == 3'h5 | valids_5_0;
valids_6_0 <= hit_idx == 3'h6 | valids_6_0;
valids_7_0 <= (&hit_idx) | valids_7_0;
end
else begin
valids_0_0 <= _GEN | ~_GEN & valids_0_0;
valids_1_0 <= _GEN_0 | ~_GEN_0 & valids_1_0;
valids_2_0 <= _GEN_1 | ~_GEN_1 & valids_2_0;
valids_3_0 <= _GEN_2 | ~_GEN_2 & valids_3_0;
valids_4_0 <= _GEN_3 | ~_GEN_3 & valids_4_0;
valids_5_0 <= _GEN_4 | ~_GEN_4 & valids_5_0;
valids_6_0 <= _GEN_5 | ~_GEN_5 & valids_6_0;
valids_7_0 <= (&enq_idx) | ~(&enq_idx) & valids_7_0;
end
state_reg <=
{~(state_reg_touch_way_sized[2]),
state_reg_touch_way_sized[2]
? {~(state_reg_touch_way_sized[1]),
state_reg_touch_way_sized[1]
? ~(state_reg_touch_way_sized[0])
: state_reg[4],
state_reg_touch_way_sized[1]
? state_reg[3]
: ~(state_reg_touch_way_sized[0])}
: state_reg[5:3],
state_reg_touch_way_sized[2]
? state_reg[2:0]
: {~(state_reg_touch_way_sized[1]),
state_reg_touch_way_sized[1]
? ~(state_reg_touch_way_sized[0])
: state_reg[1],
state_reg_touch_way_sized[1]
? state_reg[0]
: ~(state_reg_touch_way_sized[0])}};
end
ever_written_0 <= io_wen & ~hit & _GEN | ever_written_0;
ever_written_1 <= io_wen & ~hit & _GEN_0 | ever_written_1;
ever_written_2 <= io_wen & ~hit & _GEN_1 | ever_written_2;
ever_written_3 <= io_wen & ~hit & _GEN_2 | ever_written_3;
ever_written_4 <= io_wen & ~hit & _GEN_3 | ever_written_4;
ever_written_5 <= io_wen & ~hit & _GEN_4 | ever_written_5;
ever_written_6 <= io_wen & ~hit & _GEN_5 | ever_written_6;
ever_written_7 <= io_wen & ~hit & (&enq_idx) | ever_written_7;
end
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
valids_0_0 = _RANDOM[/*Zero width*/ 1'b0][0];
valids_1_0 = _RANDOM[/*Zero width*/ 1'b0][1];
valids_2_0 = _RANDOM[/*Zero width*/ 1'b0][2];
valids_3_0 = _RANDOM[/*Zero width*/ 1'b0][3];
valids_4_0 = _RANDOM[/*Zero width*/ 1'b0][4];
valids_5_0 = _RANDOM[/*Zero width*/ 1'b0][5];
valids_6_0 = _RANDOM[/*Zero width*/ 1'b0][6];
valids_7_0 = _RANDOM[/*Zero width*/ 1'b0][7];
ever_written_0 = _RANDOM[/*Zero width*/ 1'b0][8];
ever_written_1 = _RANDOM[/*Zero width*/ 1'b0][9];
ever_written_2 = _RANDOM[/*Zero width*/ 1'b0][10];
ever_written_3 = _RANDOM[/*Zero width*/ 1'b0][11];
ever_written_4 = _RANDOM[/*Zero width*/ 1'b0][12];
ever_written_5 = _RANDOM[/*Zero width*/ 1'b0][13];
ever_written_6 = _RANDOM[/*Zero width*/ 1'b0][14];
ever_written_7 = _RANDOM[/*Zero width*/ 1'b0][15];
state_reg = _RANDOM[/*Zero width*/ 1'b0][22:16];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
valids_0_0 = 1'h0;
valids_1_0 = 1'h0;
valids_2_0 = 1'h0;
valids_3_0 = 1'h0;
valids_4_0 = 1'h0;
valids_5_0 = 1'h0;
valids_6_0 = 1'h0;
valids_7_0 = 1'h0;
ever_written_0 = 1'h0;
ever_written_1 = 1'h0;
ever_written_2 = 1'h0;
ever_written_3 = 1'h0;
ever_written_4 = 1'h0;
ever_written_5 = 1'h0;
ever_written_6 = 1'h0;
ever_written_7 = 1'h0;
state_reg = 7'h0;
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
CAMTemplate idx_tag_cam (
.clock (clock),
.io_r_req_0_idx (io_write_idx),
.io_r_resp_0_0 (_idx_tag_cam_io_r_resp_0_0),
.io_r_resp_0_1 (_idx_tag_cam_io_r_resp_0_1),
.io_r_resp_0_2 (_idx_tag_cam_io_r_resp_0_2),
.io_r_resp_0_3 (_idx_tag_cam_io_r_resp_0_3),
.io_r_resp_0_4 (_idx_tag_cam_io_r_resp_0_4),
.io_r_resp_0_5 (_idx_tag_cam_io_r_resp_0_5),
.io_r_resp_0_6 (_idx_tag_cam_io_r_resp_0_6),
.io_r_resp_0_7 (_idx_tag_cam_io_r_resp_0_7),
.io_w_valid (io_wen & ~hit),
.io_w_bits_data_idx (io_write_idx),
.io_w_bits_index (enq_idx)
);
data_mem_0_8x3 data_mem_0_ext (
.R0_addr (hit_idx),
.R0_en (1'h1),
.R0_clk (clock),
.R0_data (io_hit_data_0_bits),
.W0_addr (hit ? hit_idx : enq_idx),
.W0_en (io_wen),
.W0_clk (clock),
.W0_data (io_write_data_0)
);
assign io_hit = hit;
assign io_hit_data_0_valid =
hits_oh_0 & valids_0_0 | hits_oh_1 & valids_1_0 | hits_oh_2 & valids_2_0 | hits_oh_3
& valids_3_0 | hits_oh_4 & valids_4_0 | hits_oh_5 & valids_5_0 | hits_oh_6
& valids_6_0 | hits_oh_7 & valids_7_0;
endmodule

355
rtl/BPUTop/WrBypass_32.sv
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@ -1,355 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module WrBypass_32(
input clock,
input reset,
input io_wen,
input [10:0] io_write_idx,
input [1:0] io_write_data_0,
input [1:0] io_write_data_1,
input io_write_way_mask_0,
input io_write_way_mask_1,
output io_hit,
output io_hit_data_0_valid,
output [1:0] io_hit_data_0_bits,
output io_hit_data_1_valid,
output [1:0] io_hit_data_1_bits
);
wire [3:0] _data_mem_ext_R0_data;
wire [3:0] _data_mem_ext_R1_data;
wire _idx_tag_cam_io_r_resp_0_0;
wire _idx_tag_cam_io_r_resp_0_1;
wire _idx_tag_cam_io_r_resp_0_2;
wire _idx_tag_cam_io_r_resp_0_3;
wire _idx_tag_cam_io_r_resp_0_4;
wire _idx_tag_cam_io_r_resp_0_5;
wire _idx_tag_cam_io_r_resp_0_6;
wire _idx_tag_cam_io_r_resp_0_7;
reg valids_0_0;
reg valids_0_1;
reg valids_1_0;
reg valids_1_1;
reg valids_2_0;
reg valids_2_1;
reg valids_3_0;
reg valids_3_1;
reg valids_4_0;
reg valids_4_1;
reg valids_5_0;
reg valids_5_1;
reg valids_6_0;
reg valids_6_1;
reg valids_7_0;
reg valids_7_1;
reg ever_written_0;
reg ever_written_1;
reg ever_written_2;
reg ever_written_3;
reg ever_written_4;
reg ever_written_5;
reg ever_written_6;
reg ever_written_7;
wire hits_oh_0 = _idx_tag_cam_io_r_resp_0_0 & ever_written_0;
wire hits_oh_1 = _idx_tag_cam_io_r_resp_0_1 & ever_written_1;
wire hits_oh_2 = _idx_tag_cam_io_r_resp_0_2 & ever_written_2;
wire hits_oh_3 = _idx_tag_cam_io_r_resp_0_3 & ever_written_3;
wire hits_oh_4 = _idx_tag_cam_io_r_resp_0_4 & ever_written_4;
wire hits_oh_5 = _idx_tag_cam_io_r_resp_0_5 & ever_written_5;
wire hits_oh_6 = _idx_tag_cam_io_r_resp_0_6 & ever_written_6;
wire hits_oh_7 = _idx_tag_cam_io_r_resp_0_7 & ever_written_7;
wire [2:0] _hit_idx_T_2 =
{hits_oh_7, hits_oh_6, hits_oh_5} | {hits_oh_3, hits_oh_2, hits_oh_1};
wire [2:0] hit_idx =
{|{hits_oh_7, hits_oh_6, hits_oh_5, hits_oh_4},
|(_hit_idx_T_2[2:1]),
_hit_idx_T_2[2] | _hit_idx_T_2[0]};
wire hit =
hits_oh_0 | hits_oh_1 | hits_oh_2 | hits_oh_3 | hits_oh_4 | hits_oh_5 | hits_oh_6
| hits_oh_7;
reg [6:0] state_reg;
wire [2:0] enq_idx =
{state_reg[6],
state_reg[6]
? {state_reg[5], state_reg[5] ? state_reg[4] : state_reg[3]}
: {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]}};
wire _GEN = hit_idx == 3'h0;
wire _GEN_0 = hit_idx == 3'h1;
wire _GEN_1 = hit_idx == 3'h2;
wire _GEN_2 = hit_idx == 3'h3;
wire _GEN_3 = hit_idx == 3'h4;
wire _GEN_4 = hit_idx == 3'h5;
wire _GEN_5 = hit_idx == 3'h6;
wire [2:0] state_reg_touch_way_sized = hit ? hit_idx : enq_idx;
wire _GEN_6 = enq_idx == 3'h0;
wire _GEN_7 = enq_idx == 3'h1;
wire _GEN_8 = enq_idx == 3'h2;
wire _GEN_9 = enq_idx == 3'h3;
wire _GEN_10 = enq_idx == 3'h4;
wire _GEN_11 = enq_idx == 3'h5;
wire _GEN_12 = enq_idx == 3'h6;
always @(posedge clock or posedge reset) begin
if (reset) begin
valids_0_0 <= 1'h0;
valids_0_1 <= 1'h0;
valids_1_0 <= 1'h0;
valids_1_1 <= 1'h0;
valids_2_0 <= 1'h0;
valids_2_1 <= 1'h0;
valids_3_0 <= 1'h0;
valids_3_1 <= 1'h0;
valids_4_0 <= 1'h0;
valids_4_1 <= 1'h0;
valids_5_0 <= 1'h0;
valids_5_1 <= 1'h0;
valids_6_0 <= 1'h0;
valids_6_1 <= 1'h0;
valids_7_0 <= 1'h0;
valids_7_1 <= 1'h0;
ever_written_0 <= 1'h0;
ever_written_1 <= 1'h0;
ever_written_2 <= 1'h0;
ever_written_3 <= 1'h0;
ever_written_4 <= 1'h0;
ever_written_5 <= 1'h0;
ever_written_6 <= 1'h0;
ever_written_7 <= 1'h0;
state_reg <= 7'h0;
end
else begin
if (io_wen) begin
if (hit) begin
valids_0_0 <= io_write_way_mask_0 & _GEN | valids_0_0;
valids_0_1 <= io_write_way_mask_1 & _GEN | valids_0_1;
valids_1_0 <= io_write_way_mask_0 & _GEN_0 | valids_1_0;
valids_1_1 <= io_write_way_mask_1 & _GEN_0 | valids_1_1;
valids_2_0 <= io_write_way_mask_0 & _GEN_1 | valids_2_0;
valids_2_1 <= io_write_way_mask_1 & _GEN_1 | valids_2_1;
valids_3_0 <= io_write_way_mask_0 & _GEN_2 | valids_3_0;
valids_3_1 <= io_write_way_mask_1 & _GEN_2 | valids_3_1;
valids_4_0 <= io_write_way_mask_0 & _GEN_3 | valids_4_0;
valids_4_1 <= io_write_way_mask_1 & _GEN_3 | valids_4_1;
valids_5_0 <= io_write_way_mask_0 & _GEN_4 | valids_5_0;
valids_5_1 <= io_write_way_mask_1 & _GEN_4 | valids_5_1;
valids_6_0 <= io_write_way_mask_0 & _GEN_5 | valids_6_0;
valids_6_1 <= io_write_way_mask_1 & _GEN_5 | valids_6_1;
valids_7_0 <= io_write_way_mask_0 & (&hit_idx) | valids_7_0;
valids_7_1 <= io_write_way_mask_1 & (&hit_idx) | valids_7_1;
end
else begin
valids_0_0 <= io_write_way_mask_0 & _GEN_6 | ~_GEN_6 & valids_0_0;
valids_0_1 <= io_write_way_mask_1 & _GEN_6 | ~_GEN_6 & valids_0_1;
valids_1_0 <= io_write_way_mask_0 & _GEN_7 | ~_GEN_7 & valids_1_0;
valids_1_1 <= io_write_way_mask_1 & _GEN_7 | ~_GEN_7 & valids_1_1;
valids_2_0 <= io_write_way_mask_0 & _GEN_8 | ~_GEN_8 & valids_2_0;
valids_2_1 <= io_write_way_mask_1 & _GEN_8 | ~_GEN_8 & valids_2_1;
valids_3_0 <= io_write_way_mask_0 & _GEN_9 | ~_GEN_9 & valids_3_0;
valids_3_1 <= io_write_way_mask_1 & _GEN_9 | ~_GEN_9 & valids_3_1;
valids_4_0 <= io_write_way_mask_0 & _GEN_10 | ~_GEN_10 & valids_4_0;
valids_4_1 <= io_write_way_mask_1 & _GEN_10 | ~_GEN_10 & valids_4_1;
valids_5_0 <= io_write_way_mask_0 & _GEN_11 | ~_GEN_11 & valids_5_0;
valids_5_1 <= io_write_way_mask_1 & _GEN_11 | ~_GEN_11 & valids_5_1;
valids_6_0 <= io_write_way_mask_0 & _GEN_12 | ~_GEN_12 & valids_6_0;
valids_6_1 <= io_write_way_mask_1 & _GEN_12 | ~_GEN_12 & valids_6_1;
valids_7_0 <= io_write_way_mask_0 & (&enq_idx) | ~(&enq_idx) & valids_7_0;
valids_7_1 <= io_write_way_mask_1 & (&enq_idx) | ~(&enq_idx) & valids_7_1;
end
state_reg <=
{~(state_reg_touch_way_sized[2]),
state_reg_touch_way_sized[2]
? {~(state_reg_touch_way_sized[1]),
state_reg_touch_way_sized[1]
? ~(state_reg_touch_way_sized[0])
: state_reg[4],
state_reg_touch_way_sized[1]
? state_reg[3]
: ~(state_reg_touch_way_sized[0])}
: state_reg[5:3],
state_reg_touch_way_sized[2]
? state_reg[2:0]
: {~(state_reg_touch_way_sized[1]),
state_reg_touch_way_sized[1]
? ~(state_reg_touch_way_sized[0])
: state_reg[1],
state_reg_touch_way_sized[1]
? state_reg[0]
: ~(state_reg_touch_way_sized[0])}};
end
ever_written_0 <= io_wen & ~hit & (_GEN_6 | io_wen & _GEN_6) | ever_written_0;
ever_written_1 <= io_wen & ~hit & (_GEN_7 | io_wen & _GEN_7) | ever_written_1;
ever_written_2 <= io_wen & ~hit & (_GEN_8 | io_wen & _GEN_8) | ever_written_2;
ever_written_3 <= io_wen & ~hit & (_GEN_9 | io_wen & _GEN_9) | ever_written_3;
ever_written_4 <= io_wen & ~hit & (_GEN_10 | io_wen & _GEN_10) | ever_written_4;
ever_written_5 <= io_wen & ~hit & (_GEN_11 | io_wen & _GEN_11) | ever_written_5;
ever_written_6 <= io_wen & ~hit & (_GEN_12 | io_wen & _GEN_12) | ever_written_6;
ever_written_7 <=
io_wen & ~hit & ((&enq_idx) | io_wen & (&enq_idx)) | ever_written_7;
end
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
valids_0_0 = _RANDOM[/*Zero width*/ 1'b0][0];
valids_0_1 = _RANDOM[/*Zero width*/ 1'b0][1];
valids_1_0 = _RANDOM[/*Zero width*/ 1'b0][2];
valids_1_1 = _RANDOM[/*Zero width*/ 1'b0][3];
valids_2_0 = _RANDOM[/*Zero width*/ 1'b0][4];
valids_2_1 = _RANDOM[/*Zero width*/ 1'b0][5];
valids_3_0 = _RANDOM[/*Zero width*/ 1'b0][6];
valids_3_1 = _RANDOM[/*Zero width*/ 1'b0][7];
valids_4_0 = _RANDOM[/*Zero width*/ 1'b0][8];
valids_4_1 = _RANDOM[/*Zero width*/ 1'b0][9];
valids_5_0 = _RANDOM[/*Zero width*/ 1'b0][10];
valids_5_1 = _RANDOM[/*Zero width*/ 1'b0][11];
valids_6_0 = _RANDOM[/*Zero width*/ 1'b0][12];
valids_6_1 = _RANDOM[/*Zero width*/ 1'b0][13];
valids_7_0 = _RANDOM[/*Zero width*/ 1'b0][14];
valids_7_1 = _RANDOM[/*Zero width*/ 1'b0][15];
ever_written_0 = _RANDOM[/*Zero width*/ 1'b0][16];
ever_written_1 = _RANDOM[/*Zero width*/ 1'b0][17];
ever_written_2 = _RANDOM[/*Zero width*/ 1'b0][18];
ever_written_3 = _RANDOM[/*Zero width*/ 1'b0][19];
ever_written_4 = _RANDOM[/*Zero width*/ 1'b0][20];
ever_written_5 = _RANDOM[/*Zero width*/ 1'b0][21];
ever_written_6 = _RANDOM[/*Zero width*/ 1'b0][22];
ever_written_7 = _RANDOM[/*Zero width*/ 1'b0][23];
state_reg = _RANDOM[/*Zero width*/ 1'b0][30:24];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
valids_0_0 = 1'h0;
valids_0_1 = 1'h0;
valids_1_0 = 1'h0;
valids_1_1 = 1'h0;
valids_2_0 = 1'h0;
valids_2_1 = 1'h0;
valids_3_0 = 1'h0;
valids_3_1 = 1'h0;
valids_4_0 = 1'h0;
valids_4_1 = 1'h0;
valids_5_0 = 1'h0;
valids_5_1 = 1'h0;
valids_6_0 = 1'h0;
valids_6_1 = 1'h0;
valids_7_0 = 1'h0;
valids_7_1 = 1'h0;
ever_written_0 = 1'h0;
ever_written_1 = 1'h0;
ever_written_2 = 1'h0;
ever_written_3 = 1'h0;
ever_written_4 = 1'h0;
ever_written_5 = 1'h0;
ever_written_6 = 1'h0;
ever_written_7 = 1'h0;
state_reg = 7'h0;
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
CAMTemplate_32 idx_tag_cam (
.clock (clock),
.io_r_req_0_idx (io_write_idx),
.io_r_resp_0_0 (_idx_tag_cam_io_r_resp_0_0),
.io_r_resp_0_1 (_idx_tag_cam_io_r_resp_0_1),
.io_r_resp_0_2 (_idx_tag_cam_io_r_resp_0_2),
.io_r_resp_0_3 (_idx_tag_cam_io_r_resp_0_3),
.io_r_resp_0_4 (_idx_tag_cam_io_r_resp_0_4),
.io_r_resp_0_5 (_idx_tag_cam_io_r_resp_0_5),
.io_r_resp_0_6 (_idx_tag_cam_io_r_resp_0_6),
.io_r_resp_0_7 (_idx_tag_cam_io_r_resp_0_7),
.io_w_valid (io_wen & ~hit),
.io_w_bits_data_idx (io_write_idx),
.io_w_bits_index (enq_idx)
);
data_mem_8x4 data_mem_ext (
.R0_addr (hit_idx),
.R0_en (1'h1),
.R0_clk (clock),
.R0_data (_data_mem_ext_R0_data),
.R1_addr (hit_idx),
.R1_en (1'h1),
.R1_clk (clock),
.R1_data (_data_mem_ext_R1_data),
.W0_addr (hit ? hit_idx : enq_idx),
.W0_en (io_wen),
.W0_clk (clock),
.W0_data ({io_write_data_1, io_write_data_0}),
.W0_mask ({io_write_way_mask_1, io_write_way_mask_0})
);
assign io_hit = hit;
assign io_hit_data_0_valid =
hits_oh_0 & valids_0_0 | hits_oh_1 & valids_1_0 | hits_oh_2 & valids_2_0 | hits_oh_3
& valids_3_0 | hits_oh_4 & valids_4_0 | hits_oh_5 & valids_5_0 | hits_oh_6
& valids_6_0 | hits_oh_7 & valids_7_0;
assign io_hit_data_0_bits = _data_mem_ext_R1_data[1:0];
assign io_hit_data_1_valid =
hits_oh_0 & valids_0_1 | hits_oh_1 & valids_1_1 | hits_oh_2 & valids_2_1 | hits_oh_3
& valids_3_1 | hits_oh_4 & valids_4_1 | hits_oh_5 & valids_5_1 | hits_oh_6
& valids_6_1 | hits_oh_7 & valids_7_1;
assign io_hit_data_1_bits = _data_mem_ext_R0_data[3:2];
endmodule

580
rtl/BPUTop/WrBypass_33.sv
View File

@ -1,580 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module WrBypass_33(
input clock,
input reset,
input io_wen,
input [7:0] io_write_idx,
input [5:0] io_write_data_0,
input [5:0] io_write_data_1,
input io_write_way_mask_0,
input io_write_way_mask_1,
output io_hit,
output io_hit_data_0_valid,
output [5:0] io_hit_data_0_bits,
output io_hit_data_1_valid,
output [5:0] io_hit_data_1_bits
);
wire [11:0] _data_mem_ext_R0_data;
wire [11:0] _data_mem_ext_R1_data;
wire _idx_tag_cam_io_r_resp_0_0;
wire _idx_tag_cam_io_r_resp_0_1;
wire _idx_tag_cam_io_r_resp_0_2;
wire _idx_tag_cam_io_r_resp_0_3;
wire _idx_tag_cam_io_r_resp_0_4;
wire _idx_tag_cam_io_r_resp_0_5;
wire _idx_tag_cam_io_r_resp_0_6;
wire _idx_tag_cam_io_r_resp_0_7;
wire _idx_tag_cam_io_r_resp_0_8;
wire _idx_tag_cam_io_r_resp_0_9;
wire _idx_tag_cam_io_r_resp_0_10;
wire _idx_tag_cam_io_r_resp_0_11;
wire _idx_tag_cam_io_r_resp_0_12;
wire _idx_tag_cam_io_r_resp_0_13;
wire _idx_tag_cam_io_r_resp_0_14;
wire _idx_tag_cam_io_r_resp_0_15;
reg valids_0_0;
reg valids_0_1;
reg valids_1_0;
reg valids_1_1;
reg valids_2_0;
reg valids_2_1;
reg valids_3_0;
reg valids_3_1;
reg valids_4_0;
reg valids_4_1;
reg valids_5_0;
reg valids_5_1;
reg valids_6_0;
reg valids_6_1;
reg valids_7_0;
reg valids_7_1;
reg valids_8_0;
reg valids_8_1;
reg valids_9_0;
reg valids_9_1;
reg valids_10_0;
reg valids_10_1;
reg valids_11_0;
reg valids_11_1;
reg valids_12_0;
reg valids_12_1;
reg valids_13_0;
reg valids_13_1;
reg valids_14_0;
reg valids_14_1;
reg valids_15_0;
reg valids_15_1;
reg ever_written_0;
reg ever_written_1;
reg ever_written_2;
reg ever_written_3;
reg ever_written_4;
reg ever_written_5;
reg ever_written_6;
reg ever_written_7;
reg ever_written_8;
reg ever_written_9;
reg ever_written_10;
reg ever_written_11;
reg ever_written_12;
reg ever_written_13;
reg ever_written_14;
reg ever_written_15;
wire hits_oh_0 = _idx_tag_cam_io_r_resp_0_0 & ever_written_0;
wire hits_oh_1 = _idx_tag_cam_io_r_resp_0_1 & ever_written_1;
wire hits_oh_2 = _idx_tag_cam_io_r_resp_0_2 & ever_written_2;
wire hits_oh_3 = _idx_tag_cam_io_r_resp_0_3 & ever_written_3;
wire hits_oh_4 = _idx_tag_cam_io_r_resp_0_4 & ever_written_4;
wire hits_oh_5 = _idx_tag_cam_io_r_resp_0_5 & ever_written_5;
wire hits_oh_6 = _idx_tag_cam_io_r_resp_0_6 & ever_written_6;
wire hits_oh_7 = _idx_tag_cam_io_r_resp_0_7 & ever_written_7;
wire hits_oh_8 = _idx_tag_cam_io_r_resp_0_8 & ever_written_8;
wire hits_oh_9 = _idx_tag_cam_io_r_resp_0_9 & ever_written_9;
wire hits_oh_10 = _idx_tag_cam_io_r_resp_0_10 & ever_written_10;
wire hits_oh_11 = _idx_tag_cam_io_r_resp_0_11 & ever_written_11;
wire hits_oh_12 = _idx_tag_cam_io_r_resp_0_12 & ever_written_12;
wire hits_oh_13 = _idx_tag_cam_io_r_resp_0_13 & ever_written_13;
wire hits_oh_14 = _idx_tag_cam_io_r_resp_0_14 & ever_written_14;
wire hits_oh_15 = _idx_tag_cam_io_r_resp_0_15 & ever_written_15;
wire [6:0] _hit_idx_T_2 =
{hits_oh_15, hits_oh_14, hits_oh_13, hits_oh_12, hits_oh_11, hits_oh_10, hits_oh_9}
| {hits_oh_7, hits_oh_6, hits_oh_5, hits_oh_4, hits_oh_3, hits_oh_2, hits_oh_1};
wire [2:0] _hit_idx_T_4 = _hit_idx_T_2[6:4] | _hit_idx_T_2[2:0];
wire [3:0] hit_idx =
{|{hits_oh_15,
hits_oh_14,
hits_oh_13,
hits_oh_12,
hits_oh_11,
hits_oh_10,
hits_oh_9,
hits_oh_8},
|(_hit_idx_T_2[6:3]),
|(_hit_idx_T_4[2:1]),
_hit_idx_T_4[2] | _hit_idx_T_4[0]};
wire hit =
hits_oh_0 | hits_oh_1 | hits_oh_2 | hits_oh_3 | hits_oh_4 | hits_oh_5 | hits_oh_6
| hits_oh_7 | hits_oh_8 | hits_oh_9 | hits_oh_10 | hits_oh_11 | hits_oh_12
| hits_oh_13 | hits_oh_14 | hits_oh_15;
reg [14:0] state_reg;
wire [3:0] enq_idx =
{state_reg[14],
state_reg[14]
? {state_reg[13],
state_reg[13]
? {state_reg[12], state_reg[12] ? state_reg[11] : state_reg[10]}
: {state_reg[9], state_reg[9] ? state_reg[8] : state_reg[7]}}
: {state_reg[6],
state_reg[6]
? {state_reg[5], state_reg[5] ? state_reg[4] : state_reg[3]}
: {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]}}};
wire _GEN = hit_idx == 4'h0;
wire _GEN_0 = hit_idx == 4'h1;
wire _GEN_1 = hit_idx == 4'h2;
wire _GEN_2 = hit_idx == 4'h3;
wire _GEN_3 = hit_idx == 4'h4;
wire _GEN_4 = hit_idx == 4'h5;
wire _GEN_5 = hit_idx == 4'h6;
wire _GEN_6 = hit_idx == 4'h7;
wire _GEN_7 = hit_idx == 4'h8;
wire _GEN_8 = hit_idx == 4'h9;
wire _GEN_9 = hit_idx == 4'hA;
wire _GEN_10 = hit_idx == 4'hB;
wire _GEN_11 = hit_idx == 4'hC;
wire _GEN_12 = hit_idx == 4'hD;
wire _GEN_13 = hit_idx == 4'hE;
wire [3:0] state_reg_touch_way_sized = hit ? hit_idx : enq_idx;
wire _GEN_14 = enq_idx == 4'h0;
wire _GEN_15 = enq_idx == 4'h1;
wire _GEN_16 = enq_idx == 4'h2;
wire _GEN_17 = enq_idx == 4'h3;
wire _GEN_18 = enq_idx == 4'h4;
wire _GEN_19 = enq_idx == 4'h5;
wire _GEN_20 = enq_idx == 4'h6;
wire _GEN_21 = enq_idx == 4'h7;
wire _GEN_22 = enq_idx == 4'h8;
wire _GEN_23 = enq_idx == 4'h9;
wire _GEN_24 = enq_idx == 4'hA;
wire _GEN_25 = enq_idx == 4'hB;
wire _GEN_26 = enq_idx == 4'hC;
wire _GEN_27 = enq_idx == 4'hD;
wire _GEN_28 = enq_idx == 4'hE;
always @(posedge clock or posedge reset) begin
if (reset) begin
valids_0_0 <= 1'h0;
valids_0_1 <= 1'h0;
valids_1_0 <= 1'h0;
valids_1_1 <= 1'h0;
valids_2_0 <= 1'h0;
valids_2_1 <= 1'h0;
valids_3_0 <= 1'h0;
valids_3_1 <= 1'h0;
valids_4_0 <= 1'h0;
valids_4_1 <= 1'h0;
valids_5_0 <= 1'h0;
valids_5_1 <= 1'h0;
valids_6_0 <= 1'h0;
valids_6_1 <= 1'h0;
valids_7_0 <= 1'h0;
valids_7_1 <= 1'h0;
valids_8_0 <= 1'h0;
valids_8_1 <= 1'h0;
valids_9_0 <= 1'h0;
valids_9_1 <= 1'h0;
valids_10_0 <= 1'h0;
valids_10_1 <= 1'h0;
valids_11_0 <= 1'h0;
valids_11_1 <= 1'h0;
valids_12_0 <= 1'h0;
valids_12_1 <= 1'h0;
valids_13_0 <= 1'h0;
valids_13_1 <= 1'h0;
valids_14_0 <= 1'h0;
valids_14_1 <= 1'h0;
valids_15_0 <= 1'h0;
valids_15_1 <= 1'h0;
ever_written_0 <= 1'h0;
ever_written_1 <= 1'h0;
ever_written_2 <= 1'h0;
ever_written_3 <= 1'h0;
ever_written_4 <= 1'h0;
ever_written_5 <= 1'h0;
ever_written_6 <= 1'h0;
ever_written_7 <= 1'h0;
ever_written_8 <= 1'h0;
ever_written_9 <= 1'h0;
ever_written_10 <= 1'h0;
ever_written_11 <= 1'h0;
ever_written_12 <= 1'h0;
ever_written_13 <= 1'h0;
ever_written_14 <= 1'h0;
ever_written_15 <= 1'h0;
state_reg <= 15'h0;
end
else begin
if (io_wen) begin
if (hit) begin
valids_0_0 <= io_write_way_mask_0 & _GEN | valids_0_0;
valids_0_1 <= io_write_way_mask_1 & _GEN | valids_0_1;
valids_1_0 <= io_write_way_mask_0 & _GEN_0 | valids_1_0;
valids_1_1 <= io_write_way_mask_1 & _GEN_0 | valids_1_1;
valids_2_0 <= io_write_way_mask_0 & _GEN_1 | valids_2_0;
valids_2_1 <= io_write_way_mask_1 & _GEN_1 | valids_2_1;
valids_3_0 <= io_write_way_mask_0 & _GEN_2 | valids_3_0;
valids_3_1 <= io_write_way_mask_1 & _GEN_2 | valids_3_1;
valids_4_0 <= io_write_way_mask_0 & _GEN_3 | valids_4_0;
valids_4_1 <= io_write_way_mask_1 & _GEN_3 | valids_4_1;
valids_5_0 <= io_write_way_mask_0 & _GEN_4 | valids_5_0;
valids_5_1 <= io_write_way_mask_1 & _GEN_4 | valids_5_1;
valids_6_0 <= io_write_way_mask_0 & _GEN_5 | valids_6_0;
valids_6_1 <= io_write_way_mask_1 & _GEN_5 | valids_6_1;
valids_7_0 <= io_write_way_mask_0 & _GEN_6 | valids_7_0;
valids_7_1 <= io_write_way_mask_1 & _GEN_6 | valids_7_1;
valids_8_0 <= io_write_way_mask_0 & _GEN_7 | valids_8_0;
valids_8_1 <= io_write_way_mask_1 & _GEN_7 | valids_8_1;
valids_9_0 <= io_write_way_mask_0 & _GEN_8 | valids_9_0;
valids_9_1 <= io_write_way_mask_1 & _GEN_8 | valids_9_1;
valids_10_0 <= io_write_way_mask_0 & _GEN_9 | valids_10_0;
valids_10_1 <= io_write_way_mask_1 & _GEN_9 | valids_10_1;
valids_11_0 <= io_write_way_mask_0 & _GEN_10 | valids_11_0;
valids_11_1 <= io_write_way_mask_1 & _GEN_10 | valids_11_1;
valids_12_0 <= io_write_way_mask_0 & _GEN_11 | valids_12_0;
valids_12_1 <= io_write_way_mask_1 & _GEN_11 | valids_12_1;
valids_13_0 <= io_write_way_mask_0 & _GEN_12 | valids_13_0;
valids_13_1 <= io_write_way_mask_1 & _GEN_12 | valids_13_1;
valids_14_0 <= io_write_way_mask_0 & _GEN_13 | valids_14_0;
valids_14_1 <= io_write_way_mask_1 & _GEN_13 | valids_14_1;
valids_15_0 <= io_write_way_mask_0 & (&hit_idx) | valids_15_0;
valids_15_1 <= io_write_way_mask_1 & (&hit_idx) | valids_15_1;
end
else begin
valids_0_0 <= io_write_way_mask_0 & _GEN_14 | ~_GEN_14 & valids_0_0;
valids_0_1 <= io_write_way_mask_1 & _GEN_14 | ~_GEN_14 & valids_0_1;
valids_1_0 <= io_write_way_mask_0 & _GEN_15 | ~_GEN_15 & valids_1_0;
valids_1_1 <= io_write_way_mask_1 & _GEN_15 | ~_GEN_15 & valids_1_1;
valids_2_0 <= io_write_way_mask_0 & _GEN_16 | ~_GEN_16 & valids_2_0;
valids_2_1 <= io_write_way_mask_1 & _GEN_16 | ~_GEN_16 & valids_2_1;
valids_3_0 <= io_write_way_mask_0 & _GEN_17 | ~_GEN_17 & valids_3_0;
valids_3_1 <= io_write_way_mask_1 & _GEN_17 | ~_GEN_17 & valids_3_1;
valids_4_0 <= io_write_way_mask_0 & _GEN_18 | ~_GEN_18 & valids_4_0;
valids_4_1 <= io_write_way_mask_1 & _GEN_18 | ~_GEN_18 & valids_4_1;
valids_5_0 <= io_write_way_mask_0 & _GEN_19 | ~_GEN_19 & valids_5_0;
valids_5_1 <= io_write_way_mask_1 & _GEN_19 | ~_GEN_19 & valids_5_1;
valids_6_0 <= io_write_way_mask_0 & _GEN_20 | ~_GEN_20 & valids_6_0;
valids_6_1 <= io_write_way_mask_1 & _GEN_20 | ~_GEN_20 & valids_6_1;
valids_7_0 <= io_write_way_mask_0 & _GEN_21 | ~_GEN_21 & valids_7_0;
valids_7_1 <= io_write_way_mask_1 & _GEN_21 | ~_GEN_21 & valids_7_1;
valids_8_0 <= io_write_way_mask_0 & _GEN_22 | ~_GEN_22 & valids_8_0;
valids_8_1 <= io_write_way_mask_1 & _GEN_22 | ~_GEN_22 & valids_8_1;
valids_9_0 <= io_write_way_mask_0 & _GEN_23 | ~_GEN_23 & valids_9_0;
valids_9_1 <= io_write_way_mask_1 & _GEN_23 | ~_GEN_23 & valids_9_1;
valids_10_0 <= io_write_way_mask_0 & _GEN_24 | ~_GEN_24 & valids_10_0;
valids_10_1 <= io_write_way_mask_1 & _GEN_24 | ~_GEN_24 & valids_10_1;
valids_11_0 <= io_write_way_mask_0 & _GEN_25 | ~_GEN_25 & valids_11_0;
valids_11_1 <= io_write_way_mask_1 & _GEN_25 | ~_GEN_25 & valids_11_1;
valids_12_0 <= io_write_way_mask_0 & _GEN_26 | ~_GEN_26 & valids_12_0;
valids_12_1 <= io_write_way_mask_1 & _GEN_26 | ~_GEN_26 & valids_12_1;
valids_13_0 <= io_write_way_mask_0 & _GEN_27 | ~_GEN_27 & valids_13_0;
valids_13_1 <= io_write_way_mask_1 & _GEN_27 | ~_GEN_27 & valids_13_1;
valids_14_0 <= io_write_way_mask_0 & _GEN_28 | ~_GEN_28 & valids_14_0;
valids_14_1 <= io_write_way_mask_1 & _GEN_28 | ~_GEN_28 & valids_14_1;
valids_15_0 <= io_write_way_mask_0 & (&enq_idx) | ~(&enq_idx) & valids_15_0;
valids_15_1 <= io_write_way_mask_1 & (&enq_idx) | ~(&enq_idx) & valids_15_1;
end
state_reg <=
{~(state_reg_touch_way_sized[3]),
state_reg_touch_way_sized[3]
? {~(state_reg_touch_way_sized[2]),
state_reg_touch_way_sized[2]
? {~(state_reg_touch_way_sized[1]),
state_reg_touch_way_sized[1]
? ~(state_reg_touch_way_sized[0])
: state_reg[11],
state_reg_touch_way_sized[1]
? state_reg[10]
: ~(state_reg_touch_way_sized[0])}
: state_reg[12:10],
state_reg_touch_way_sized[2]
? state_reg[9:7]
: {~(state_reg_touch_way_sized[1]),
state_reg_touch_way_sized[1]
? ~(state_reg_touch_way_sized[0])
: state_reg[8],
state_reg_touch_way_sized[1]
? state_reg[7]
: ~(state_reg_touch_way_sized[0])}}
: state_reg[13:7],
state_reg_touch_way_sized[3]
? state_reg[6:0]
: {~(state_reg_touch_way_sized[2]),
state_reg_touch_way_sized[2]
? {~(state_reg_touch_way_sized[1]),
state_reg_touch_way_sized[1]
? ~(state_reg_touch_way_sized[0])
: state_reg[4],
state_reg_touch_way_sized[1]
? state_reg[3]
: ~(state_reg_touch_way_sized[0])}
: state_reg[5:3],
state_reg_touch_way_sized[2]
? state_reg[2:0]
: {~(state_reg_touch_way_sized[1]),
state_reg_touch_way_sized[1]
? ~(state_reg_touch_way_sized[0])
: state_reg[1],
state_reg_touch_way_sized[1]
? state_reg[0]
: ~(state_reg_touch_way_sized[0])}}};
end
ever_written_0 <= io_wen & ~hit & (_GEN_14 | io_wen & _GEN_14) | ever_written_0;
ever_written_1 <= io_wen & ~hit & (_GEN_15 | io_wen & _GEN_15) | ever_written_1;
ever_written_2 <= io_wen & ~hit & (_GEN_16 | io_wen & _GEN_16) | ever_written_2;
ever_written_3 <= io_wen & ~hit & (_GEN_17 | io_wen & _GEN_17) | ever_written_3;
ever_written_4 <= io_wen & ~hit & (_GEN_18 | io_wen & _GEN_18) | ever_written_4;
ever_written_5 <= io_wen & ~hit & (_GEN_19 | io_wen & _GEN_19) | ever_written_5;
ever_written_6 <= io_wen & ~hit & (_GEN_20 | io_wen & _GEN_20) | ever_written_6;
ever_written_7 <= io_wen & ~hit & (_GEN_21 | io_wen & _GEN_21) | ever_written_7;
ever_written_8 <= io_wen & ~hit & (_GEN_22 | io_wen & _GEN_22) | ever_written_8;
ever_written_9 <= io_wen & ~hit & (_GEN_23 | io_wen & _GEN_23) | ever_written_9;
ever_written_10 <= io_wen & ~hit & (_GEN_24 | io_wen & _GEN_24) | ever_written_10;
ever_written_11 <= io_wen & ~hit & (_GEN_25 | io_wen & _GEN_25) | ever_written_11;
ever_written_12 <= io_wen & ~hit & (_GEN_26 | io_wen & _GEN_26) | ever_written_12;
ever_written_13 <= io_wen & ~hit & (_GEN_27 | io_wen & _GEN_27) | ever_written_13;
ever_written_14 <= io_wen & ~hit & (_GEN_28 | io_wen & _GEN_28) | ever_written_14;
ever_written_15 <=
io_wen & ~hit & ((&enq_idx) | io_wen & (&enq_idx)) | ever_written_15;
end
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:1];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin
_RANDOM[i[0]] = `RANDOM;
end
valids_0_0 = _RANDOM[1'h0][0];
valids_0_1 = _RANDOM[1'h0][1];
valids_1_0 = _RANDOM[1'h0][2];
valids_1_1 = _RANDOM[1'h0][3];
valids_2_0 = _RANDOM[1'h0][4];
valids_2_1 = _RANDOM[1'h0][5];
valids_3_0 = _RANDOM[1'h0][6];
valids_3_1 = _RANDOM[1'h0][7];
valids_4_0 = _RANDOM[1'h0][8];
valids_4_1 = _RANDOM[1'h0][9];
valids_5_0 = _RANDOM[1'h0][10];
valids_5_1 = _RANDOM[1'h0][11];
valids_6_0 = _RANDOM[1'h0][12];
valids_6_1 = _RANDOM[1'h0][13];
valids_7_0 = _RANDOM[1'h0][14];
valids_7_1 = _RANDOM[1'h0][15];
valids_8_0 = _RANDOM[1'h0][16];
valids_8_1 = _RANDOM[1'h0][17];
valids_9_0 = _RANDOM[1'h0][18];
valids_9_1 = _RANDOM[1'h0][19];
valids_10_0 = _RANDOM[1'h0][20];
valids_10_1 = _RANDOM[1'h0][21];
valids_11_0 = _RANDOM[1'h0][22];
valids_11_1 = _RANDOM[1'h0][23];
valids_12_0 = _RANDOM[1'h0][24];
valids_12_1 = _RANDOM[1'h0][25];
valids_13_0 = _RANDOM[1'h0][26];
valids_13_1 = _RANDOM[1'h0][27];
valids_14_0 = _RANDOM[1'h0][28];
valids_14_1 = _RANDOM[1'h0][29];
valids_15_0 = _RANDOM[1'h0][30];
valids_15_1 = _RANDOM[1'h0][31];
ever_written_0 = _RANDOM[1'h1][0];
ever_written_1 = _RANDOM[1'h1][1];
ever_written_2 = _RANDOM[1'h1][2];
ever_written_3 = _RANDOM[1'h1][3];
ever_written_4 = _RANDOM[1'h1][4];
ever_written_5 = _RANDOM[1'h1][5];
ever_written_6 = _RANDOM[1'h1][6];
ever_written_7 = _RANDOM[1'h1][7];
ever_written_8 = _RANDOM[1'h1][8];
ever_written_9 = _RANDOM[1'h1][9];
ever_written_10 = _RANDOM[1'h1][10];
ever_written_11 = _RANDOM[1'h1][11];
ever_written_12 = _RANDOM[1'h1][12];
ever_written_13 = _RANDOM[1'h1][13];
ever_written_14 = _RANDOM[1'h1][14];
ever_written_15 = _RANDOM[1'h1][15];
state_reg = _RANDOM[1'h1][30:16];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
valids_0_0 = 1'h0;
valids_0_1 = 1'h0;
valids_1_0 = 1'h0;
valids_1_1 = 1'h0;
valids_2_0 = 1'h0;
valids_2_1 = 1'h0;
valids_3_0 = 1'h0;
valids_3_1 = 1'h0;
valids_4_0 = 1'h0;
valids_4_1 = 1'h0;
valids_5_0 = 1'h0;
valids_5_1 = 1'h0;
valids_6_0 = 1'h0;
valids_6_1 = 1'h0;
valids_7_0 = 1'h0;
valids_7_1 = 1'h0;
valids_8_0 = 1'h0;
valids_8_1 = 1'h0;
valids_9_0 = 1'h0;
valids_9_1 = 1'h0;
valids_10_0 = 1'h0;
valids_10_1 = 1'h0;
valids_11_0 = 1'h0;
valids_11_1 = 1'h0;
valids_12_0 = 1'h0;
valids_12_1 = 1'h0;
valids_13_0 = 1'h0;
valids_13_1 = 1'h0;
valids_14_0 = 1'h0;
valids_14_1 = 1'h0;
valids_15_0 = 1'h0;
valids_15_1 = 1'h0;
ever_written_0 = 1'h0;
ever_written_1 = 1'h0;
ever_written_2 = 1'h0;
ever_written_3 = 1'h0;
ever_written_4 = 1'h0;
ever_written_5 = 1'h0;
ever_written_6 = 1'h0;
ever_written_7 = 1'h0;
ever_written_8 = 1'h0;
ever_written_9 = 1'h0;
ever_written_10 = 1'h0;
ever_written_11 = 1'h0;
ever_written_12 = 1'h0;
ever_written_13 = 1'h0;
ever_written_14 = 1'h0;
ever_written_15 = 1'h0;
state_reg = 15'h0;
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
CAMTemplate_33 idx_tag_cam (
.clock (clock),
.io_r_req_0_idx (io_write_idx),
.io_r_resp_0_0 (_idx_tag_cam_io_r_resp_0_0),
.io_r_resp_0_1 (_idx_tag_cam_io_r_resp_0_1),
.io_r_resp_0_2 (_idx_tag_cam_io_r_resp_0_2),
.io_r_resp_0_3 (_idx_tag_cam_io_r_resp_0_3),
.io_r_resp_0_4 (_idx_tag_cam_io_r_resp_0_4),
.io_r_resp_0_5 (_idx_tag_cam_io_r_resp_0_5),
.io_r_resp_0_6 (_idx_tag_cam_io_r_resp_0_6),
.io_r_resp_0_7 (_idx_tag_cam_io_r_resp_0_7),
.io_r_resp_0_8 (_idx_tag_cam_io_r_resp_0_8),
.io_r_resp_0_9 (_idx_tag_cam_io_r_resp_0_9),
.io_r_resp_0_10 (_idx_tag_cam_io_r_resp_0_10),
.io_r_resp_0_11 (_idx_tag_cam_io_r_resp_0_11),
.io_r_resp_0_12 (_idx_tag_cam_io_r_resp_0_12),
.io_r_resp_0_13 (_idx_tag_cam_io_r_resp_0_13),
.io_r_resp_0_14 (_idx_tag_cam_io_r_resp_0_14),
.io_r_resp_0_15 (_idx_tag_cam_io_r_resp_0_15),
.io_w_valid (io_wen & ~hit),
.io_w_bits_data_idx (io_write_idx),
.io_w_bits_index (enq_idx)
);
data_mem_16x12 data_mem_ext (
.R0_addr (hit_idx),
.R0_en (1'h1),
.R0_clk (clock),
.R0_data (_data_mem_ext_R0_data),
.R1_addr (hit_idx),
.R1_en (1'h1),
.R1_clk (clock),
.R1_data (_data_mem_ext_R1_data),
.W0_addr (hit ? hit_idx : enq_idx),
.W0_en (io_wen),
.W0_clk (clock),
.W0_data ({io_write_data_1, io_write_data_0}),
.W0_mask ({io_write_way_mask_1, io_write_way_mask_0})
);
assign io_hit = hit;
assign io_hit_data_0_valid =
hits_oh_0 & valids_0_0 | hits_oh_1 & valids_1_0 | hits_oh_2 & valids_2_0 | hits_oh_3
& valids_3_0 | hits_oh_4 & valids_4_0 | hits_oh_5 & valids_5_0 | hits_oh_6
& valids_6_0 | hits_oh_7 & valids_7_0 | hits_oh_8 & valids_8_0 | hits_oh_9
& valids_9_0 | hits_oh_10 & valids_10_0 | hits_oh_11 & valids_11_0 | hits_oh_12
& valids_12_0 | hits_oh_13 & valids_13_0 | hits_oh_14 & valids_14_0 | hits_oh_15
& valids_15_0;
assign io_hit_data_0_bits = _data_mem_ext_R1_data[5:0];
assign io_hit_data_1_valid =
hits_oh_0 & valids_0_1 | hits_oh_1 & valids_1_1 | hits_oh_2 & valids_2_1 | hits_oh_3
& valids_3_1 | hits_oh_4 & valids_4_1 | hits_oh_5 & valids_5_1 | hits_oh_6
& valids_6_1 | hits_oh_7 & valids_7_1 | hits_oh_8 & valids_8_1 | hits_oh_9
& valids_9_1 | hits_oh_10 & valids_10_1 | hits_oh_11 & valids_11_1 | hits_oh_12
& valids_12_1 | hits_oh_13 & valids_13_1 | hits_oh_14 & valids_14_1 | hits_oh_15
& valids_15_1;
assign io_hit_data_1_bits = _data_mem_ext_R0_data[11:6];
endmodule

157
rtl/BPUTop/WrBypass_41.sv
View File

@ -1,157 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module WrBypass_41(
input clock,
input reset,
input io_wen,
input [7:0] io_write_idx,
input [1:0] io_write_data_0,
output io_hit,
output [1:0] io_hit_data_0_bits
);
wire _idx_tag_cam_io_r_resp_0_0;
wire _idx_tag_cam_io_r_resp_0_1;
wire _idx_tag_cam_io_r_resp_0_2;
wire _idx_tag_cam_io_r_resp_0_3;
reg ever_written_0;
reg ever_written_1;
reg ever_written_2;
reg ever_written_3;
wire hits_oh_1 = _idx_tag_cam_io_r_resp_0_1 & ever_written_1;
wire hits_oh_2 = _idx_tag_cam_io_r_resp_0_2 & ever_written_2;
wire hits_oh_3 = _idx_tag_cam_io_r_resp_0_3 & ever_written_3;
wire [1:0] hit_idx = {|{hits_oh_3, hits_oh_2}, hits_oh_3 | hits_oh_1};
wire hit =
_idx_tag_cam_io_r_resp_0_0 & ever_written_0 | hits_oh_1 | hits_oh_2 | hits_oh_3;
reg [2:0] state_reg;
wire [1:0] enq_idx = {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]};
wire [1:0] state_reg_touch_way_sized = hit ? hit_idx : enq_idx;
always @(posedge clock or posedge reset) begin
if (reset) begin
ever_written_0 <= 1'h0;
ever_written_1 <= 1'h0;
ever_written_2 <= 1'h0;
ever_written_3 <= 1'h0;
state_reg <= 3'h0;
end
else begin
ever_written_0 <= io_wen & ~hit & enq_idx == 2'h0 | ever_written_0;
ever_written_1 <= io_wen & ~hit & enq_idx == 2'h1 | ever_written_1;
ever_written_2 <= io_wen & ~hit & enq_idx == 2'h2 | ever_written_2;
ever_written_3 <= io_wen & ~hit & (&enq_idx) | ever_written_3;
if (io_wen)
state_reg <=
{~(state_reg_touch_way_sized[1]),
state_reg_touch_way_sized[1] ? ~(state_reg_touch_way_sized[0]) : state_reg[1],
state_reg_touch_way_sized[1] ? state_reg[0] : ~(state_reg_touch_way_sized[0])};
end
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
ever_written_0 = _RANDOM[/*Zero width*/ 1'b0][4];
ever_written_1 = _RANDOM[/*Zero width*/ 1'b0][5];
ever_written_2 = _RANDOM[/*Zero width*/ 1'b0][6];
ever_written_3 = _RANDOM[/*Zero width*/ 1'b0][7];
state_reg = _RANDOM[/*Zero width*/ 1'b0][10:8];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
ever_written_0 = 1'h0;
ever_written_1 = 1'h0;
ever_written_2 = 1'h0;
ever_written_3 = 1'h0;
state_reg = 3'h0;
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
CAMTemplate_41 idx_tag_cam (
.clock (clock),
.io_r_req_0_idx (io_write_idx),
.io_r_resp_0_0 (_idx_tag_cam_io_r_resp_0_0),
.io_r_resp_0_1 (_idx_tag_cam_io_r_resp_0_1),
.io_r_resp_0_2 (_idx_tag_cam_io_r_resp_0_2),
.io_r_resp_0_3 (_idx_tag_cam_io_r_resp_0_3),
.io_w_valid (io_wen & ~hit),
.io_w_bits_data_idx (io_write_idx),
.io_w_bits_index (enq_idx)
);
data_mem_0_4x2 data_mem_0_ext (
.R0_addr (hit_idx),
.R0_en (1'h1),
.R0_clk (clock),
.R0_data (io_hit_data_0_bits),
.W0_addr (hit ? hit_idx : enq_idx),
.W0_en (io_wen),
.W0_clk (clock),
.W0_data (io_write_data_0)
);
assign io_hit = hit;
endmodule

157
rtl/BPUTop/WrBypass_43.sv
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@ -1,157 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module WrBypass_43(
input clock,
input reset,
input io_wen,
input [8:0] io_write_idx,
input [1:0] io_write_data_0,
output io_hit,
output [1:0] io_hit_data_0_bits
);
wire _idx_tag_cam_io_r_resp_0_0;
wire _idx_tag_cam_io_r_resp_0_1;
wire _idx_tag_cam_io_r_resp_0_2;
wire _idx_tag_cam_io_r_resp_0_3;
reg ever_written_0;
reg ever_written_1;
reg ever_written_2;
reg ever_written_3;
wire hits_oh_1 = _idx_tag_cam_io_r_resp_0_1 & ever_written_1;
wire hits_oh_2 = _idx_tag_cam_io_r_resp_0_2 & ever_written_2;
wire hits_oh_3 = _idx_tag_cam_io_r_resp_0_3 & ever_written_3;
wire [1:0] hit_idx = {|{hits_oh_3, hits_oh_2}, hits_oh_3 | hits_oh_1};
wire hit =
_idx_tag_cam_io_r_resp_0_0 & ever_written_0 | hits_oh_1 | hits_oh_2 | hits_oh_3;
reg [2:0] state_reg;
wire [1:0] enq_idx = {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]};
wire [1:0] state_reg_touch_way_sized = hit ? hit_idx : enq_idx;
always @(posedge clock or posedge reset) begin
if (reset) begin
ever_written_0 <= 1'h0;
ever_written_1 <= 1'h0;
ever_written_2 <= 1'h0;
ever_written_3 <= 1'h0;
state_reg <= 3'h0;
end
else begin
ever_written_0 <= io_wen & ~hit & enq_idx == 2'h0 | ever_written_0;
ever_written_1 <= io_wen & ~hit & enq_idx == 2'h1 | ever_written_1;
ever_written_2 <= io_wen & ~hit & enq_idx == 2'h2 | ever_written_2;
ever_written_3 <= io_wen & ~hit & (&enq_idx) | ever_written_3;
if (io_wen)
state_reg <=
{~(state_reg_touch_way_sized[1]),
state_reg_touch_way_sized[1] ? ~(state_reg_touch_way_sized[0]) : state_reg[1],
state_reg_touch_way_sized[1] ? state_reg[0] : ~(state_reg_touch_way_sized[0])};
end
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
ever_written_0 = _RANDOM[/*Zero width*/ 1'b0][4];
ever_written_1 = _RANDOM[/*Zero width*/ 1'b0][5];
ever_written_2 = _RANDOM[/*Zero width*/ 1'b0][6];
ever_written_3 = _RANDOM[/*Zero width*/ 1'b0][7];
state_reg = _RANDOM[/*Zero width*/ 1'b0][10:8];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
ever_written_0 = 1'h0;
ever_written_1 = 1'h0;
ever_written_2 = 1'h0;
ever_written_3 = 1'h0;
state_reg = 3'h0;
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
CAMTemplate_43 idx_tag_cam (
.clock (clock),
.io_r_req_0_idx (io_write_idx),
.io_r_resp_0_0 (_idx_tag_cam_io_r_resp_0_0),
.io_r_resp_0_1 (_idx_tag_cam_io_r_resp_0_1),
.io_r_resp_0_2 (_idx_tag_cam_io_r_resp_0_2),
.io_r_resp_0_3 (_idx_tag_cam_io_r_resp_0_3),
.io_w_valid (io_wen & ~hit),
.io_w_bits_data_idx (io_write_idx),
.io_w_bits_index (enq_idx)
);
data_mem_0_4x2 data_mem_0_ext (
.R0_addr (hit_idx),
.R0_en (1'h1),
.R0_clk (clock),
.R0_data (io_hit_data_0_bits),
.W0_addr (hit ? hit_idx : enq_idx),
.W0_en (io_wen),
.W0_clk (clock),
.W0_data (io_write_data_0)
);
assign io_hit = hit;
endmodule

76
rtl/BPUTop/array_0_0.sv
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@ -1,76 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module array_0_0(
input [6:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [52:0] RW0_wdata,
output [52:0] RW0_rdata
);
array_0_0_ext array_0_0_ext (
.RW0_addr (RW0_addr),
.RW0_en (RW0_en),
.RW0_clk (RW0_clk),
.RW0_wmode (RW0_wmode),
.RW0_wdata (RW0_wdata),
.RW0_rdata (RW0_rdata)
);
endmodule

49
rtl/BPUTop/array_0_0_ext.v
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@ -1,49 +0,0 @@
module array_0_0_ext(
input RW0_clk,
input [6:0] RW0_addr,
input RW0_en,
input RW0_wmode,
input [52:0] RW0_wdata,
output [52:0] RW0_rdata
);
reg reg_RW0_ren;
reg [6:0] reg_RW0_addr;
reg [52:0] ram [127:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 128; initvar = initvar+1)
ram[initvar] = {2 {$random}};
reg_RW0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge RW0_clk)
reg_RW0_ren <= RW0_en && !RW0_wmode;
always @(posedge RW0_clk)
if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
always @(posedge RW0_clk)
if (RW0_en && RW0_wmode) begin
for (i=0;i<1;i=i+1) begin
ram[RW0_addr][i*53 +: 53] <= RW0_wdata[i*53 +: 53];
end
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [63:0] RW0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
RW0_random = {$random, $random};
reg_RW0_ren = RW0_random[0];
end
`endif
always @(posedge RW0_clk) RW0_random <= {$random, $random};
assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[52:0];
`else
assign RW0_rdata = ram[reg_RW0_addr];
`endif
endmodule

78
rtl/BPUTop/array_3.sv
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@ -1,78 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module array_3(
input [8:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [319:0] RW0_wdata,
output [319:0] RW0_rdata,
input [3:0] RW0_wmask
);
array_3_ext array_3_ext (
.RW0_addr (RW0_addr),
.RW0_en (RW0_en),
.RW0_clk (RW0_clk),
.RW0_wmode (RW0_wmode),
.RW0_wdata (RW0_wdata),
.RW0_rdata (RW0_rdata),
.RW0_wmask (RW0_wmask)
);
endmodule

52
rtl/BPUTop/array_3_ext.v
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@ -1,52 +0,0 @@
module array_3_ext(
input RW0_clk,
input [8:0] RW0_addr,
input RW0_en,
input RW0_wmode,
input [3:0] RW0_wmask,
input [319:0] RW0_wdata,
output [319:0] RW0_rdata
);
reg reg_RW0_ren;
reg [8:0] reg_RW0_addr;
reg [319:0] ram [511:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 512; initvar = initvar+1)
ram[initvar] = {10 {$random}};
reg_RW0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge RW0_clk)
reg_RW0_ren <= RW0_en && !RW0_wmode;
always @(posedge RW0_clk)
if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
always @(posedge RW0_clk)
if (RW0_en && RW0_wmode) begin
for (i=0;i<4;i=i+1) begin
if (RW0_wmask[i]) begin
ram[RW0_addr][i*80 +: 80] <= RW0_wdata[i*80 +: 80];
end
end
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [319:0] RW0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
RW0_random = {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random};
reg_RW0_ren = RW0_random[0];
end
`endif
always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random};
assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[319:0];
`else
assign RW0_rdata = ram[reg_RW0_addr];
`endif
endmodule

78
rtl/BPUTop/array_4.sv
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@ -1,78 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module array_4(
input [7:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [15:0] RW0_wdata,
output [15:0] RW0_rdata,
input [15:0] RW0_wmask
);
array_4_ext array_4_ext (
.RW0_addr (RW0_addr),
.RW0_en (RW0_en),
.RW0_clk (RW0_clk),
.RW0_wmode (RW0_wmode),
.RW0_wdata (RW0_wdata),
.RW0_rdata (RW0_rdata),
.RW0_wmask (RW0_wmask)
);
endmodule

48
rtl/BPUTop/array_4_ext.v
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@ -1,48 +0,0 @@
module array_4_ext(
input RW0_clk,
input [7:0] RW0_addr,
input RW0_en,
input RW0_wmode,
input [15:0] RW0_wmask,
input [15:0] RW0_wdata,
output [15:0] RW0_rdata
);
reg reg_RW0_ren;
reg [7:0] reg_RW0_addr;
reg [15:0] ram [255:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 256; initvar = initvar+1)
ram[initvar] = {1 {$random}};
reg_RW0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge RW0_clk)
reg_RW0_ren <= RW0_en && !RW0_wmode;
always @(posedge RW0_clk)
if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
always @(posedge RW0_clk)
if (RW0_en && RW0_wmode) begin
ram[RW0_addr] <= (RW0_wmask & RW0_wdata) | (~RW0_wmask & ram[RW0_addr]);
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [31:0] RW0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
RW0_random = {$random};
reg_RW0_ren = RW0_random[0];
end
`endif
always @(posedge RW0_clk) RW0_random <= {$random};
assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[15:0];
`else
assign RW0_rdata = ram[reg_RW0_addr];
`endif
endmodule

78
rtl/BPUTop/array_5.sv
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@ -1,78 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module array_5(
input [8:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [23:0] RW0_wdata,
output [23:0] RW0_rdata,
input [1:0] RW0_wmask
);
array_5_ext array_5_ext (
.RW0_addr (RW0_addr),
.RW0_en (RW0_en),
.RW0_clk (RW0_clk),
.RW0_wmode (RW0_wmode),
.RW0_wdata (RW0_wdata),
.RW0_rdata (RW0_rdata),
.RW0_wmask (RW0_wmask)
);
endmodule

52
rtl/BPUTop/array_5_ext.v
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@ -1,52 +0,0 @@
module array_5_ext(
input RW0_clk,
input [8:0] RW0_addr,
input RW0_en,
input RW0_wmode,
input [1:0] RW0_wmask,
input [23:0] RW0_wdata,
output [23:0] RW0_rdata
);
reg reg_RW0_ren;
reg [8:0] reg_RW0_addr;
reg [23:0] ram [511:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 512; initvar = initvar+1)
ram[initvar] = {1 {$random}};
reg_RW0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge RW0_clk)
reg_RW0_ren <= RW0_en && !RW0_wmode;
always @(posedge RW0_clk)
if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
always @(posedge RW0_clk)
if (RW0_en && RW0_wmode) begin
for (i=0;i<2;i=i+1) begin
if (RW0_wmask[i]) begin
ram[RW0_addr][i*12 +: 12] <= RW0_wdata[i*12 +: 12];
end
end
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [31:0] RW0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
RW0_random = {$random};
reg_RW0_ren = RW0_random[0];
end
`endif
always @(posedge RW0_clk) RW0_random <= {$random};
assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[23:0];
`else
assign RW0_rdata = ram[reg_RW0_addr];
`endif
endmodule

82
rtl/BPUTop/array_6.sv
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@ -1,82 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module array_6(
input [8:0] R0_addr,
input R0_en,
input R0_clk,
output [15:0] R0_data,
input [8:0] W0_addr,
input W0_en,
input W0_clk,
input [15:0] W0_data,
input [7:0] W0_mask
);
array_6_ext array_6_ext (
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data),
.W0_mask (W0_mask)
);
endmodule

57
rtl/BPUTop/array_6_ext.v
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@ -1,57 +0,0 @@
module array_6_ext(
input W0_clk,
input [8:0] W0_addr,
input W0_en,
input [15:0] W0_data,
input [7:0] W0_mask,
input R0_clk,
input [8:0] R0_addr,
input R0_en,
output [15:0] R0_data
);
reg reg_R0_ren;
reg [8:0] reg_R0_addr;
reg [15:0] ram [511:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 512; initvar = initvar+1)
ram[initvar] = {1 {$random}};
reg_R0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge R0_clk)
reg_R0_ren <= R0_en;
always @(posedge R0_clk)
if (R0_en) reg_R0_addr <= R0_addr;
always @(posedge W0_clk)
if (W0_en) begin
if (W0_mask[0]) ram[W0_addr][1:0] <= W0_data[1:0];
if (W0_mask[1]) ram[W0_addr][3:2] <= W0_data[3:2];
if (W0_mask[2]) ram[W0_addr][5:4] <= W0_data[5:4];
if (W0_mask[3]) ram[W0_addr][7:6] <= W0_data[7:6];
if (W0_mask[4]) ram[W0_addr][9:8] <= W0_data[9:8];
if (W0_mask[5]) ram[W0_addr][11:10] <= W0_data[11:10];
if (W0_mask[6]) ram[W0_addr][13:12] <= W0_data[13:12];
if (W0_mask[7]) ram[W0_addr][15:14] <= W0_data[15:14];
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [31:0] R0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
R0_random = {$random};
reg_R0_ren = R0_random[0];
end
`endif
always @(posedge R0_clk) R0_random <= {$random};
assign R0_data = reg_R0_ren ? ram[reg_R0_addr] : R0_random[15:0];
`else
assign R0_data = ram[reg_R0_addr];
`endif
endmodule

82
rtl/BPUTop/array_7.sv
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@ -1,82 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module array_7(
input [7:0] R0_addr,
input R0_en,
input R0_clk,
output [23:0] R0_data,
input [7:0] W0_addr,
input W0_en,
input W0_clk,
input [23:0] W0_data,
input [3:0] W0_mask
);
array_7_ext array_7_ext (
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data),
.W0_mask (W0_mask)
);
endmodule

53
rtl/BPUTop/array_7_ext.v
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@ -1,53 +0,0 @@
module array_7_ext(
input W0_clk,
input [7:0] W0_addr,
input W0_en,
input [23:0] W0_data,
input [3:0] W0_mask,
input R0_clk,
input [7:0] R0_addr,
input R0_en,
output [23:0] R0_data
);
reg reg_R0_ren;
reg [7:0] reg_R0_addr;
reg [23:0] ram [255:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 256; initvar = initvar+1)
ram[initvar] = {1 {$random}};
reg_R0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge R0_clk)
reg_R0_ren <= R0_en;
always @(posedge R0_clk)
if (R0_en) reg_R0_addr <= R0_addr;
always @(posedge W0_clk)
if (W0_en) begin
if (W0_mask[0]) ram[W0_addr][5:0] <= W0_data[5:0];
if (W0_mask[1]) ram[W0_addr][11:6] <= W0_data[11:6];
if (W0_mask[2]) ram[W0_addr][17:12] <= W0_data[17:12];
if (W0_mask[3]) ram[W0_addr][23:18] <= W0_data[23:18];
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [31:0] R0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
R0_random = {$random};
reg_R0_ren = R0_random[0];
end
`endif
always @(posedge R0_clk) R0_random <= {$random};
assign R0_data = reg_R0_ren ? ram[reg_R0_addr] : R0_random[23:0];
`else
assign R0_data = ram[reg_R0_addr];
`endif
endmodule

78
rtl/BPUTop/array_8.sv
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@ -1,78 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module array_8(
input [6:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [105:0] RW0_wdata,
output [105:0] RW0_rdata,
input [1:0] RW0_wmask
);
array_8_ext array_8_ext (
.RW0_addr (RW0_addr),
.RW0_en (RW0_en),
.RW0_clk (RW0_clk),
.RW0_wmode (RW0_wmode),
.RW0_wdata (RW0_wdata),
.RW0_rdata (RW0_rdata),
.RW0_wmask (RW0_wmask)
);
endmodule

52
rtl/BPUTop/array_8_ext.v
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@ -1,52 +0,0 @@
module array_8_ext(
input RW0_clk,
input [6:0] RW0_addr,
input RW0_en,
input RW0_wmode,
input [1:0] RW0_wmask,
input [105:0] RW0_wdata,
output [105:0] RW0_rdata
);
reg reg_RW0_ren;
reg [6:0] reg_RW0_addr;
reg [105:0] ram [127:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 128; initvar = initvar+1)
ram[initvar] = {4 {$random}};
reg_RW0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge RW0_clk)
reg_RW0_ren <= RW0_en && !RW0_wmode;
always @(posedge RW0_clk)
if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
always @(posedge RW0_clk)
if (RW0_en && RW0_wmode) begin
for (i=0;i<2;i=i+1) begin
if (RW0_wmask[i]) begin
ram[RW0_addr][i*53 +: 53] <= RW0_wdata[i*53 +: 53];
end
end
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [127:0] RW0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
RW0_random = {$random, $random, $random, $random};
reg_RW0_ren = RW0_random[0];
end
`endif
always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random};
assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[105:0];
`else
assign RW0_rdata = ram[reg_RW0_addr];
`endif
endmodule

95
rtl/BPUTop/data_16x16.sv
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@ -1,95 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
// VCS coverage exclude_file
module data_16x16(
input [3:0] R0_addr,
input R0_en,
input R0_clk,
output [15:0] R0_data,
input [3:0] W0_addr,
input W0_en,
input W0_clk,
input [15:0] W0_data,
input [3:0] W1_addr,
input W1_en,
input W1_clk,
input [15:0] W1_data
);
reg [15:0] Memory[0:15];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data;
if (W1_en & 1'h1)
Memory[W1_addr] <= W1_data;
end // always @(posedge)
`ifdef ENABLE_INITIAL_MEM_
reg [31:0] _RANDOM_MEM;
initial begin
`INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_MEM_INIT
for (logic [4:0] i = 5'h0; i < 5'h10; i += 5'h1) begin
_RANDOM_MEM = `RANDOM;
Memory[i[3:0]] = _RANDOM_MEM[15:0];
end
`endif // RANDOMIZE_MEM_INIT
end // initial
`endif // ENABLE_INITIAL_MEM_
assign R0_data = R0_en ? Memory[R0_addr] : 16'bx;
endmodule

95
rtl/BPUTop/data_32x16.sv
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@ -1,95 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
// VCS coverage exclude_file
module data_32x16(
input [4:0] R0_addr,
input R0_en,
input R0_clk,
output [15:0] R0_data,
input [4:0] W0_addr,
input W0_en,
input W0_clk,
input [15:0] W0_data,
input [4:0] W1_addr,
input W1_en,
input W1_clk,
input [15:0] W1_data
);
reg [15:0] Memory[0:31];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data;
if (W1_en & 1'h1)
Memory[W1_addr] <= W1_data;
end // always @(posedge)
`ifdef ENABLE_INITIAL_MEM_
reg [31:0] _RANDOM_MEM;
initial begin
`INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_MEM_INIT
for (logic [5:0] i = 6'h0; i < 6'h20; i += 6'h1) begin
_RANDOM_MEM = `RANDOM;
Memory[i[4:0]] = _RANDOM_MEM[15:0];
end
`endif // RANDOMIZE_MEM_INIT
end // initial
`endif // ENABLE_INITIAL_MEM_
assign R0_data = R0_en ? Memory[R0_addr] : 16'bx;
endmodule

89
rtl/BPUTop/data_mem_0_4x2.sv
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@ -1,89 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
// VCS coverage exclude_file
module data_mem_0_4x2(
input [1:0] R0_addr,
input R0_en,
input R0_clk,
output [1:0] R0_data,
input [1:0] W0_addr,
input W0_en,
input W0_clk,
input [1:0] W0_data
);
reg [1:0] Memory[0:3];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data;
end // always @(posedge)
`ifdef ENABLE_INITIAL_MEM_
reg [31:0] _RANDOM_MEM;
initial begin
`INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_MEM_INIT
for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin
_RANDOM_MEM = `RANDOM;
Memory[i[1:0]] = _RANDOM_MEM[1:0];
end
`endif // RANDOMIZE_MEM_INIT
end // initial
`endif // ENABLE_INITIAL_MEM_
assign R0_data = R0_en ? Memory[R0_addr] : 2'bx;
endmodule

89
rtl/BPUTop/data_mem_0_8x3.sv
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@ -1,89 +0,0 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
// VCS coverage exclude_file
module data_mem_0_8x3(
input [2:0] R0_addr,
input R0_en,
input R0_clk,
output [2:0] R0_data,
input [2:0] W0_addr,
input W0_en,
input W0_clk,
input [2:0] W0_data
);
reg [2:0] Memory[0:7];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data;
end // always @(posedge)
`ifdef ENABLE_INITIAL_MEM_
reg [31:0] _RANDOM_MEM;
initial begin
`INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_MEM_INIT
for (logic [3:0] i = 4'h0; i < 4'h8; i += 4'h1) begin
_RANDOM_MEM = `RANDOM;
Memory[i[2:0]] = _RANDOM_MEM[2:0];
end
`endif // RANDOMIZE_MEM_INIT
end // initial
`endif // ENABLE_INITIAL_MEM_
assign R0_data = R0_en ? Memory[R0_addr] : 3'bx;
endmodule

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