OSchip
/
UnityChipVerification
13
0
Fork 14
Code Issues Pull Requests Packages Projects Releases Wiki Activity
UnityChipVerification/rtl/common/ext_sram.v

1711 lines
51 KiB
Verilog
Raw Permalink Blame History

module array_ext(
input RW0_clk,
input [6:0] RW0_addr,
input RW0_en,
input RW0_wmode,
input [3:0] RW0_wmask,
input [99:0] RW0_wdata,
output [99:0] RW0_rdata
);
reg reg_RW0_ren;
reg [6:0] reg_RW0_addr;
reg [99:0] ram [127:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 128; initvar = initvar+1)
ram[initvar] = {4 {$random}};
reg_RW0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge RW0_clk)
reg_RW0_ren <= RW0_en && !RW0_wmode;
always @(posedge RW0_clk)
if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
always @(posedge RW0_clk)
if (RW0_en && RW0_wmode) begin
for(i=0;i<4;i=i+1) begin
if(RW0_wmask[i]) begin
ram[RW0_addr][i*25 +: 25] <= RW0_wdata[i*25 +: 25];
end
end
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [127:0] RW0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
RW0_random = {$random, $random, $random, $random};
reg_RW0_ren = RW0_random[0];
end
`endif
always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random};
assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[99:0];
`else
assign RW0_rdata = ram[reg_RW0_addr];
`endif
endmodule
module array_0_ext(
input RW0_clk,
input [6:0] RW0_addr,
input RW0_en,
input RW0_wmode,
input [1:0] RW0_wmask,
input [1023:0] RW0_wdata,
output [1023:0] RW0_rdata
);
reg reg_RW0_ren;
reg [6:0] reg_RW0_addr;
reg [1023:0] ram [127:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 128; initvar = initvar+1)
ram[initvar] = {32 {$random}};
reg_RW0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge RW0_clk)
reg_RW0_ren <= RW0_en && !RW0_wmode;
always @(posedge RW0_clk)
if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
always @(posedge RW0_clk)
if (RW0_en && RW0_wmode) begin
for(i=0;i<2;i=i+1) begin
if(RW0_wmask[i]) begin
ram[RW0_addr][i*512 +: 512] <= RW0_wdata[i*512 +: 512];
end
end
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [1023:0] RW0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
RW0_random = {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random};
reg_RW0_ren = RW0_random[0];
end
`endif
always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random};
assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[1023:0];
`else
assign RW0_rdata = ram[reg_RW0_addr];
`endif
endmodule
module array_1_ext(
input RW0_clk,
input [6:0] RW0_addr,
input RW0_en,
input RW0_wmode,
input [3:0] RW0_wmask,
input [127:0] RW0_wdata,
output [127:0] RW0_rdata
);
reg reg_RW0_ren;
reg [6:0] reg_RW0_addr;
reg [127:0] ram [127:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 128; initvar = initvar+1)
ram[initvar] = {4 {$random}};
reg_RW0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge RW0_clk)
reg_RW0_ren <= RW0_en && !RW0_wmode;
always @(posedge RW0_clk)
if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
always @(posedge RW0_clk)
if (RW0_en && RW0_wmode) begin
for(i=0;i<4;i=i+1) begin
if(RW0_wmask[i]) begin
ram[RW0_addr][i*32 +: 32] <= RW0_wdata[i*32 +: 32];
end
end
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [127:0] RW0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
RW0_random = {$random, $random, $random, $random};
reg_RW0_ren = RW0_random[0];
end
`endif
always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random};
assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[127:0];
`else
assign RW0_rdata = ram[reg_RW0_addr];
`endif
endmodule
module array_2_ext(
input RW0_clk,
input [7:0] RW0_addr,
input RW0_en,
input RW0_wmode,
input [3:0] RW0_wmask,
input [99:0] RW0_wdata,
output [99:0] RW0_rdata
);
reg reg_RW0_ren;
reg [7:0] reg_RW0_addr;
reg [99:0] ram [255:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 256; initvar = initvar+1)
ram[initvar] = {4 {$random}};
reg_RW0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge RW0_clk)
reg_RW0_ren <= RW0_en && !RW0_wmode;
always @(posedge RW0_clk)
if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
always @(posedge RW0_clk)
if (RW0_en && RW0_wmode) begin
for(i=0;i<4;i=i+1) begin
if(RW0_wmask[i]) begin
ram[RW0_addr][i*25 +: 25] <= RW0_wdata[i*25 +: 25];
end
end
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [127:0] RW0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
RW0_random = {$random, $random, $random, $random};
reg_RW0_ren = RW0_random[0];
end
`endif
always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random};
assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[99:0];
`else
assign RW0_rdata = ram[reg_RW0_addr];
`endif
endmodule
module array_3_ext(
input RW0_clk,
input [8:0] RW0_addr,
input RW0_en,
input RW0_wmode,
input [3:0] RW0_wmask,
input [319:0] RW0_wdata,
output [319:0] RW0_rdata
);
reg reg_RW0_ren;
reg [8:0] reg_RW0_addr;
reg [319:0] ram [511:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 512; initvar = initvar+1)
ram[initvar] = {10 {$random}};
reg_RW0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge RW0_clk)
reg_RW0_ren <= RW0_en && !RW0_wmode;
always @(posedge RW0_clk)
if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
always @(posedge RW0_clk)
if (RW0_en && RW0_wmode) begin
for(i=0;i<4;i=i+1) begin
if(RW0_wmask[i]) begin
ram[RW0_addr][i*80 +: 80] <= RW0_wdata[i*80 +: 80];
end
end
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [319:0] RW0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
RW0_random = {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random};
reg_RW0_ren = RW0_random[0];
end
`endif
always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random};
assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[319:0];
`else
assign RW0_rdata = ram[reg_RW0_addr];
`endif
endmodule
module array_4_ext(
input RW0_clk,
input [7:0] RW0_addr,
input RW0_en,
input RW0_wmode,
input [15:0] RW0_wmask,
input [15:0] RW0_wdata,
output [15:0] RW0_rdata
);
reg reg_RW0_ren;
reg [7:0] reg_RW0_addr;
reg [15:0] ram [255:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 256; initvar = initvar+1)
ram[initvar] = {1 {$random}};
reg_RW0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge RW0_clk)
reg_RW0_ren <= RW0_en && !RW0_wmode;
always @(posedge RW0_clk)
if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
always @(posedge RW0_clk)
if (RW0_en && RW0_wmode) begin
for(i=0;i<16;i=i+1) begin
if(RW0_wmask[i]) begin
ram[RW0_addr][i*1 +: 1] <= RW0_wdata[i*1 +: 1];
end
end
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [31:0] RW0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
RW0_random = {$random};
reg_RW0_ren = RW0_random[0];
end
`endif
always @(posedge RW0_clk) RW0_random <= {$random};
assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[15:0];
`else
assign RW0_rdata = ram[reg_RW0_addr];
`endif
endmodule
module array_5_ext(
input RW0_clk,
input [8:0] RW0_addr,
input RW0_en,
input RW0_wmode,
input [1:0] RW0_wmask,
input [23:0] RW0_wdata,
output [23:0] RW0_rdata
);
reg reg_RW0_ren;
reg [8:0] reg_RW0_addr;
reg [23:0] ram [511:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 512; initvar = initvar+1)
ram[initvar] = {1 {$random}};
reg_RW0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge RW0_clk)
reg_RW0_ren <= RW0_en && !RW0_wmode;
always @(posedge RW0_clk)
if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
always @(posedge RW0_clk)
if (RW0_en && RW0_wmode) begin
for(i=0;i<2;i=i+1) begin
if(RW0_wmask[i]) begin
ram[RW0_addr][i*12 +: 12] <= RW0_wdata[i*12 +: 12];
end
end
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [31:0] RW0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
RW0_random = {$random};
reg_RW0_ren = RW0_random[0];
end
`endif
always @(posedge RW0_clk) RW0_random <= {$random};
assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[23:0];
`else
assign RW0_rdata = ram[reg_RW0_addr];
`endif
endmodule
module array_6_ext(
input W0_clk,
input [8:0] W0_addr,
input W0_en,
input [15:0] W0_data,
input [7:0] W0_mask,
input R0_clk,
input [8:0] R0_addr,
input R0_en,
output [15:0] R0_data
);
reg reg_R0_ren;
reg [8:0] reg_R0_addr;
reg [15:0] ram [511:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 512; initvar = initvar+1)
ram[initvar] = {1 {$random}};
reg_R0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge R0_clk)
reg_R0_ren <= R0_en;
always @(posedge R0_clk)
if (R0_en) reg_R0_addr <= R0_addr;
always @(posedge W0_clk)
if (W0_en) begin
if (W0_mask[0]) ram[W0_addr][1:0] <= W0_data[1:0];
if (W0_mask[1]) ram[W0_addr][3:2] <= W0_data[3:2];
if (W0_mask[2]) ram[W0_addr][5:4] <= W0_data[5:4];
if (W0_mask[3]) ram[W0_addr][7:6] <= W0_data[7:6];
if (W0_mask[4]) ram[W0_addr][9:8] <= W0_data[9:8];
if (W0_mask[5]) ram[W0_addr][11:10] <= W0_data[11:10];
if (W0_mask[6]) ram[W0_addr][13:12] <= W0_data[13:12];
if (W0_mask[7]) ram[W0_addr][15:14] <= W0_data[15:14];
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [31:0] R0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
R0_random = {$random};
reg_R0_ren = R0_random[0];
end
`endif
always @(posedge R0_clk) R0_random <= {$random};
assign R0_data = reg_R0_ren ? ram[reg_R0_addr] : R0_random[15:0];
`else
assign R0_data = ram[reg_R0_addr];
`endif
endmodule
module array_7_ext(
input W0_clk,
input [7:0] W0_addr,
input W0_en,
input [23:0] W0_data,
input [3:0] W0_mask,
input R0_clk,
input [7:0] R0_addr,
input R0_en,
output [23:0] R0_data
);
reg reg_R0_ren;
reg [7:0] reg_R0_addr;
reg [23:0] ram [255:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 256; initvar = initvar+1)
ram[initvar] = {1 {$random}};
reg_R0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge R0_clk)
reg_R0_ren <= R0_en;
always @(posedge R0_clk)
if (R0_en) reg_R0_addr <= R0_addr;
always @(posedge W0_clk)
if (W0_en) begin
if (W0_mask[0]) ram[W0_addr][5:0] <= W0_data[5:0];
if (W0_mask[1]) ram[W0_addr][11:6] <= W0_data[11:6];
if (W0_mask[2]) ram[W0_addr][17:12] <= W0_data[17:12];
if (W0_mask[3]) ram[W0_addr][23:18] <= W0_data[23:18];
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [31:0] R0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
R0_random = {$random};
reg_R0_ren = R0_random[0];
end
`endif
always @(posedge R0_clk) R0_random <= {$random};
assign R0_data = reg_R0_ren ? ram[reg_R0_addr] : R0_random[23:0];
`else
assign R0_data = ram[reg_R0_addr];
`endif
endmodule
module array_0_0_ext(
input RW0_clk,
input [6:0] RW0_addr,
input RW0_en,
input RW0_wmode,
input [49:0] RW0_wdata,
output [49:0] RW0_rdata
);
reg reg_RW0_ren;
reg [6:0] reg_RW0_addr;
reg [49:0] ram [127:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 128; initvar = initvar+1)
ram[initvar] = {2 {$random}};
reg_RW0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge RW0_clk)
reg_RW0_ren <= RW0_en && !RW0_wmode;
always @(posedge RW0_clk)
if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
always @(posedge RW0_clk)
if (RW0_en && RW0_wmode) begin
for(i=0;i<1;i=i+1) begin
ram[RW0_addr][i*50 +: 50] <= RW0_wdata[i*50 +: 50];
end
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [63:0] RW0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
RW0_random = {$random, $random};
reg_RW0_ren = RW0_random[0];
end
`endif
always @(posedge RW0_clk) RW0_random <= {$random, $random};
assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[49:0];
`else
assign RW0_rdata = ram[reg_RW0_addr];
`endif
endmodule
module array_8_ext(
input RW0_clk,
input [6:0] RW0_addr,
input RW0_en,
input RW0_wmode,
input [1:0] RW0_wmask,
input [99:0] RW0_wdata,
output [99:0] RW0_rdata
);
reg reg_RW0_ren;
reg [6:0] reg_RW0_addr;
reg [99:0] ram [127:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 128; initvar = initvar+1)
ram[initvar] = {4 {$random}};
reg_RW0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge RW0_clk)
reg_RW0_ren <= RW0_en && !RW0_wmode;
always @(posedge RW0_clk)
if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
always @(posedge RW0_clk)
if (RW0_en && RW0_wmode) begin
for(i=0;i<2;i=i+1) begin
if(RW0_wmask[i]) begin
ram[RW0_addr][i*50 +: 50] <= RW0_wdata[i*50 +: 50];
end
end
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [127:0] RW0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
RW0_random = {$random, $random, $random, $random};
reg_RW0_ren = RW0_random[0];
end
`endif
always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random};
assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[99:0];
`else
assign RW0_rdata = ram[reg_RW0_addr];
`endif
endmodule
module array_0_1_ext(
input W0_clk,
input [5:0] W0_addr,
input W0_en,
input [246:0] W0_data,
input R0_clk,
input [5:0] R0_addr,
input R0_en,
output [246:0] R0_data
);
reg reg_R0_ren;
reg [5:0] reg_R0_addr;
reg [246:0] ram [63:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 64; initvar = initvar+1)
ram[initvar] = {8 {$random}};
reg_R0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge R0_clk)
reg_R0_ren <= R0_en;
always @(posedge R0_clk)
if (R0_en) reg_R0_addr <= R0_addr;
always @(posedge W0_clk)
if (W0_en) begin
ram[W0_addr][246:0] <= W0_data[246:0];
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [255:0] R0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
R0_random = {$random, $random, $random, $random, $random, $random, $random, $random};
reg_R0_ren = R0_random[0];
end
`endif
always @(posedge R0_clk) R0_random <= {$random, $random, $random, $random, $random, $random, $random, $random};
assign R0_data = reg_R0_ren ? ram[reg_R0_addr] : R0_random[246:0];
`else
assign R0_data = ram[reg_R0_addr];
`endif
endmodule
module array_0_2_ext(
input W0_clk,
input [5:0] W0_addr,
input W0_en,
input [218:0] W0_data,
input R0_clk,
input [5:0] R0_addr,
input R0_en,
output [218:0] R0_data
);
reg reg_R0_ren;
reg [5:0] reg_R0_addr;
reg [218:0] ram [63:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 64; initvar = initvar+1)
ram[initvar] = {7 {$random}};
reg_R0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge R0_clk)
reg_R0_ren <= R0_en;
always @(posedge R0_clk)
if (R0_en) reg_R0_addr <= R0_addr;
always @(posedge W0_clk)
if (W0_en) begin
ram[W0_addr][218:0] <= W0_data[218:0];
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [223:0] R0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
R0_random = {$random, $random, $random, $random, $random, $random, $random};
reg_R0_ren = R0_random[0];
end
`endif
always @(posedge R0_clk) R0_random <= {$random, $random, $random, $random, $random, $random, $random};
assign R0_data = reg_R0_ren ? ram[reg_R0_addr] : R0_random[218:0];
`else
assign R0_data = ram[reg_R0_addr];
`endif
endmodule
module array_0_3_ext(
input RW0_clk,
input [7:0] RW0_addr,
input RW0_en,
input RW0_wmode,
input [63:0] RW0_wdata,
output [63:0] RW0_rdata
);
reg reg_RW0_ren;
reg [7:0] reg_RW0_addr;
reg [63:0] ram [255:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 256; initvar = initvar+1)
ram[initvar] = {2 {$random}};
reg_RW0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge RW0_clk)
reg_RW0_ren <= RW0_en && !RW0_wmode;
always @(posedge RW0_clk)
if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
always @(posedge RW0_clk)
if (RW0_en && RW0_wmode) begin
for(i=0;i<1;i=i+1) begin
ram[RW0_addr][i*64 +: 64] <= RW0_wdata[i*64 +: 64];
end
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [63:0] RW0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
RW0_random = {$random, $random};
reg_RW0_ren = RW0_random[0];
end
`endif
always @(posedge RW0_clk) RW0_random <= {$random, $random};
assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[63:0];
`else
assign RW0_rdata = ram[reg_RW0_addr];
`endif
endmodule
module array_9_ext(
input RW0_clk,
input [7:0] RW0_addr,
input RW0_en,
input RW0_wmode,
input [3:0] RW0_wmask,
input [95:0] RW0_wdata,
output [95:0] RW0_rdata
);
reg reg_RW0_ren;
reg [7:0] reg_RW0_addr;
reg [95:0] ram [255:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 256; initvar = initvar+1)
ram[initvar] = {3 {$random}};
reg_RW0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge RW0_clk)
reg_RW0_ren <= RW0_en && !RW0_wmode;
always @(posedge RW0_clk)
if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
always @(posedge RW0_clk)
if (RW0_en && RW0_wmode) begin
for(i=0;i<4;i=i+1) begin
if(RW0_wmask[i]) begin
ram[RW0_addr][i*24 +: 24] <= RW0_wdata[i*24 +: 24];
end
end
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [95:0] RW0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
RW0_random = {$random, $random, $random};
reg_RW0_ren = RW0_random[0];
end
`endif
always @(posedge RW0_clk) RW0_random <= {$random, $random, $random};
assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[95:0];
`else
assign RW0_rdata = ram[reg_RW0_addr];
`endif
endmodule
module array_10_ext(
input RW0_clk,
input [7:0] RW0_addr,
input RW0_en,
input RW0_wmode,
input [3:0] RW0_wmask,
input [23:0] RW0_wdata,
output [23:0] RW0_rdata
);
reg reg_RW0_ren;
reg [7:0] reg_RW0_addr;
reg [23:0] ram [255:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 256; initvar = initvar+1)
ram[initvar] = {1 {$random}};
reg_RW0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge RW0_clk)
reg_RW0_ren <= RW0_en && !RW0_wmode;
always @(posedge RW0_clk)
if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
always @(posedge RW0_clk)
if (RW0_en && RW0_wmode) begin
for(i=0;i<4;i=i+1) begin
if(RW0_wmask[i]) begin
ram[RW0_addr][i*6 +: 6] <= RW0_wdata[i*6 +: 6];
end
end
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [31:0] RW0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
RW0_random = {$random};
reg_RW0_ren = RW0_random[0];
end
`endif
always @(posedge RW0_clk) RW0_random <= {$random};
assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[23:0];
`else
assign RW0_rdata = ram[reg_RW0_addr];
`endif
endmodule
module array_11_ext(
input RW0_clk,
input [2:0] RW0_addr,
input RW0_en,
input RW0_wmode,
input [3:0] RW0_wmask,
input [1039:0] RW0_wdata,
output [1039:0] RW0_rdata
);
reg reg_RW0_ren;
reg [2:0] reg_RW0_addr;
reg [1039:0] ram [7:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 8; initvar = initvar+1)
ram[initvar] = {33 {$random}};
reg_RW0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge RW0_clk)
reg_RW0_ren <= RW0_en && !RW0_wmode;
always @(posedge RW0_clk)
if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
always @(posedge RW0_clk)
if (RW0_en && RW0_wmode) begin
for(i=0;i<4;i=i+1) begin
if(RW0_wmask[i]) begin
ram[RW0_addr][i*260 +: 260] <= RW0_wdata[i*260 +: 260];
end
end
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [1055:0] RW0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
RW0_random = {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random};
reg_RW0_ren = RW0_random[0];
end
`endif
always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random};
assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[1039:0];
`else
assign RW0_rdata = ram[reg_RW0_addr];
`endif
endmodule
module array_12_ext(
input RW0_clk,
input [4:0] RW0_addr,
input RW0_en,
input RW0_wmode,
input [7:0] RW0_wmask,
input [2647:0] RW0_wdata,
output [2647:0] RW0_rdata
);
reg reg_RW0_ren;
reg [4:0] reg_RW0_addr;
reg [2647:0] ram [31:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 32; initvar = initvar+1)
ram[initvar] = {83 {$random}};
reg_RW0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge RW0_clk)
reg_RW0_ren <= RW0_en && !RW0_wmode;
always @(posedge RW0_clk)
if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
always @(posedge RW0_clk)
if (RW0_en && RW0_wmode) begin
for(i=0;i<8;i=i+1) begin
if(RW0_wmask[i]) begin
ram[RW0_addr][i*331 +: 331] <= RW0_wdata[i*331 +: 331];
end
end
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [2655:0] RW0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
RW0_random = {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random};
reg_RW0_ren = RW0_random[0];
end
`endif
always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random};
assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[2647:0];
`else
assign RW0_rdata = ram[reg_RW0_addr];
`endif
endmodule
module array_13_ext(
input RW0_clk,
input [4:0] RW0_addr,
input RW0_en,
input RW0_wmode,
input [1:0] RW0_wmask,
input [147:0] RW0_wdata,
output [147:0] RW0_rdata
);
reg reg_RW0_ren;
reg [4:0] reg_RW0_addr;
reg [147:0] ram [31:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 32; initvar = initvar+1)
ram[initvar] = {5 {$random}};
reg_RW0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge RW0_clk)
reg_RW0_ren <= RW0_en && !RW0_wmode;
always @(posedge RW0_clk)
if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
always @(posedge RW0_clk)
if (RW0_en && RW0_wmode) begin
for(i=0;i<2;i=i+1) begin
if(RW0_wmask[i]) begin
ram[RW0_addr][i*74 +: 74] <= RW0_wdata[i*74 +: 74];
end
end
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [159:0] RW0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
RW0_random = {$random, $random, $random, $random, $random};
reg_RW0_ren = RW0_random[0];
end
`endif
always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random, $random};
assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[147:0];
`else
assign RW0_rdata = ram[reg_RW0_addr];
`endif
endmodule
module array_0_4_ext(
input RW0_clk,
input [7:0] RW0_addr,
input RW0_en,
input RW0_wmode,
input [12:0] RW0_wdata,
output [12:0] RW0_rdata
);
reg reg_RW0_ren;
reg [7:0] reg_RW0_addr;
reg [12:0] ram [255:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 256; initvar = initvar+1)
ram[initvar] = {1 {$random}};
reg_RW0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge RW0_clk)
reg_RW0_ren <= RW0_en && !RW0_wmode;
always @(posedge RW0_clk)
if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
always @(posedge RW0_clk)
if (RW0_en && RW0_wmode) begin
for(i=0;i<1;i=i+1) begin
ram[RW0_addr][i*13 +: 13] <= RW0_wdata[i*13 +: 13];
end
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [31:0] RW0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
RW0_random = {$random};
reg_RW0_ren = RW0_random[0];
end
`endif
always @(posedge RW0_clk) RW0_random <= {$random};
assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[12:0];
`else
assign RW0_rdata = ram[reg_RW0_addr];
`endif
endmodule
module array_14_ext(
input RW0_clk,
input [9:0] RW0_addr,
input RW0_en,
input RW0_wmode,
input [15:0] RW0_wmask,
input [383:0] RW0_wdata,
output [383:0] RW0_rdata
);
reg reg_RW0_ren;
reg [9:0] reg_RW0_addr;
reg [383:0] ram [1023:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 1024; initvar = initvar+1)
ram[initvar] = {12 {$random}};
reg_RW0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge RW0_clk)
reg_RW0_ren <= RW0_en && !RW0_wmode;
always @(posedge RW0_clk)
if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
always @(posedge RW0_clk)
if (RW0_en && RW0_wmode) begin
for(i=0;i<16;i=i+1) begin
if(RW0_wmask[i]) begin
ram[RW0_addr][i*24 +: 24] <= RW0_wdata[i*24 +: 24];
end
end
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [383:0] RW0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
RW0_random = {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random};
reg_RW0_ren = RW0_random[0];
end
`endif
always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random};
assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[383:0];
`else
assign RW0_rdata = ram[reg_RW0_addr];
`endif
endmodule
module array_15_ext(
input RW0_clk,
input [8:0] RW0_addr,
input RW0_en,
input RW0_wmode,
input [7:0] RW0_wmask,
input [151:0] RW0_wdata,
output [151:0] RW0_rdata
);
reg reg_RW0_ren;
reg [8:0] reg_RW0_addr;
reg [151:0] ram [511:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 512; initvar = initvar+1)
ram[initvar] = {5 {$random}};
reg_RW0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge RW0_clk)
reg_RW0_ren <= RW0_en && !RW0_wmode;
always @(posedge RW0_clk)
if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
always @(posedge RW0_clk)
if (RW0_en && RW0_wmode) begin
for(i=0;i<8;i=i+1) begin
if(RW0_wmask[i]) begin
ram[RW0_addr][i*19 +: 19] <= RW0_wdata[i*19 +: 19];
end
end
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [159:0] RW0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
RW0_random = {$random, $random, $random, $random, $random};
reg_RW0_ren = RW0_random[0];
end
`endif
always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random, $random};
assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[151:0];
`else
assign RW0_rdata = ram[reg_RW0_addr];
`endif
endmodule
module array_16_ext(
input RW0_clk,
input [8:0] RW0_addr,
input RW0_en,
input RW0_wmode,
input [7:0] RW0_wmask,
input [87:0] RW0_wdata,
output [87:0] RW0_rdata
);
reg reg_RW0_ren;
reg [8:0] reg_RW0_addr;
reg [87:0] ram [511:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 512; initvar = initvar+1)
ram[initvar] = {3 {$random}};
reg_RW0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge RW0_clk)
reg_RW0_ren <= RW0_en && !RW0_wmode;
always @(posedge RW0_clk)
if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
always @(posedge RW0_clk)
if (RW0_en && RW0_wmode) begin
for(i=0;i<8;i=i+1) begin
if(RW0_wmask[i]) begin
ram[RW0_addr][i*11 +: 11] <= RW0_wdata[i*11 +: 11];
end
end
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [95:0] RW0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
RW0_random = {$random, $random, $random};
reg_RW0_ren = RW0_random[0];
end
`endif
always @(posedge RW0_clk) RW0_random <= {$random, $random, $random};
assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[87:0];
`else
assign RW0_rdata = ram[reg_RW0_addr];
`endif
endmodule
module array_0_5_ext(
input RW0_clk,
input [8:0] RW0_addr,
input RW0_en,
input RW0_wmode,
input [6:0] RW0_wdata,
output [6:0] RW0_rdata
);
reg reg_RW0_ren;
reg [8:0] reg_RW0_addr;
reg [6:0] ram [511:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 512; initvar = initvar+1)
ram[initvar] = {1 {$random}};
reg_RW0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge RW0_clk)
reg_RW0_ren <= RW0_en && !RW0_wmode;
always @(posedge RW0_clk)
if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
always @(posedge RW0_clk)
if (RW0_en && RW0_wmode) begin
for(i=0;i<1;i=i+1) begin
ram[RW0_addr][i*7 +: 7] <= RW0_wdata[i*7 +: 7];
end
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [31:0] RW0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
RW0_random = {$random};
reg_RW0_ren = RW0_random[0];
end
`endif
always @(posedge RW0_clk) RW0_random <= {$random};
assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[6:0];
`else
assign RW0_rdata = ram[reg_RW0_addr];
`endif
endmodule
module array_0_6_ext(
input RW0_clk,
input [11:0] RW0_addr,
input RW0_en,
input RW0_wmode,
input [511:0] RW0_wdata,
output [511:0] RW0_rdata
);
reg reg_RW0_ren;
reg [11:0] reg_RW0_addr;
reg [511:0] ram [4095:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 4096; initvar = initvar+1)
ram[initvar] = {16 {$random}};
reg_RW0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge RW0_clk)
reg_RW0_ren <= RW0_en && !RW0_wmode;
always @(posedge RW0_clk)
if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
always @(posedge RW0_clk)
if (RW0_en && RW0_wmode) begin
for(i=0;i<1;i=i+1) begin
ram[RW0_addr][i*512 +: 512] <= RW0_wdata[i*512 +: 512];
end
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [511:0] RW0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
RW0_random = {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random};
reg_RW0_ren = RW0_random[0];
end
`endif
always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random};
assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[511:0];
`else
assign RW0_rdata = ram[reg_RW0_addr];
`endif
endmodule
module array_17_ext(
input RW0_clk,
input [9:0] RW0_addr,
input RW0_en,
input RW0_wmode,
input [15:0] RW0_wmask,
input [7743:0] RW0_wdata,
output [7743:0] RW0_rdata
);
reg reg_RW0_ren;
reg [9:0] reg_RW0_addr;
reg [7743:0] ram [1023:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 1024; initvar = initvar+1)
ram[initvar] = {242 {$random}};
reg_RW0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge RW0_clk)
reg_RW0_ren <= RW0_en && !RW0_wmode;
always @(posedge RW0_clk)
if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
always @(posedge RW0_clk)
if (RW0_en && RW0_wmode) begin
for(i=0;i<16;i=i+1) begin
if(RW0_wmask[i]) begin
ram[RW0_addr][i*484 +: 484] <= RW0_wdata[i*484 +: 484];
end
end
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [7743:0] RW0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
RW0_random = {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random};
reg_RW0_ren = RW0_random[0];
end
`endif
always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random};
assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[7743:0];
`else
assign RW0_rdata = ram[reg_RW0_addr];
`endif
endmodule
module array_0_7_ext(
input RW0_clk,
input [13:0] RW0_addr,
input RW0_en,
input RW0_wmode,
input [63:0] RW0_wdata,
output [63:0] RW0_rdata
);
reg reg_RW0_ren;
reg [13:0] reg_RW0_addr;
reg [63:0] ram [16383:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 16384; initvar = initvar+1)
ram[initvar] = {2 {$random}};
reg_RW0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge RW0_clk)
reg_RW0_ren <= RW0_en && !RW0_wmode;
always @(posedge RW0_clk)
if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
always @(posedge RW0_clk)
if (RW0_en && RW0_wmode) begin
for(i=0;i<1;i=i+1) begin
ram[RW0_addr][i*64 +: 64] <= RW0_wdata[i*64 +: 64];
end
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [63:0] RW0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
RW0_random = {$random, $random};
reg_RW0_ren = RW0_random[0];
end
`endif
always @(posedge RW0_clk) RW0_random <= {$random, $random};
assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[63:0];
`else
assign RW0_rdata = ram[reg_RW0_addr];
`endif
endmodule
module array_0_8_ext(
input RW0_clk,
input [13:0] RW0_addr,
input RW0_en,
input RW0_wmode,
input [31:0] RW0_wdata,
output [31:0] RW0_rdata
);
reg reg_RW0_ren;
reg [13:0] reg_RW0_addr;
reg [31:0] ram [16383:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 16384; initvar = initvar+1)
ram[initvar] = {1 {$random}};
reg_RW0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge RW0_clk)
reg_RW0_ren <= RW0_en && !RW0_wmode;
always @(posedge RW0_clk)
if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
always @(posedge RW0_clk)
if (RW0_en && RW0_wmode) begin
for(i=0;i<1;i=i+1) begin
ram[RW0_addr][i*32 +: 32] <= RW0_wdata[i*32 +: 32];
end
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [31:0] RW0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
RW0_random = {$random};
reg_RW0_ren = RW0_random[0];
end
`endif
always @(posedge RW0_clk) RW0_random <= {$random};
assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[31:0];
`else
assign RW0_rdata = ram[reg_RW0_addr];
`endif
endmodule
module array_18_ext(
input RW0_clk,
input [9:0] RW0_addr,
input RW0_en,
input RW0_wmode,
input [9:0] RW0_wmask,
input [19:0] RW0_wdata,
output [19:0] RW0_rdata
);
reg reg_RW0_ren;
reg [9:0] reg_RW0_addr;
reg [19:0] ram [1023:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 1024; initvar = initvar+1)
ram[initvar] = {1 {$random}};
reg_RW0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge RW0_clk)
reg_RW0_ren <= RW0_en && !RW0_wmode;
always @(posedge RW0_clk)
if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
always @(posedge RW0_clk)
if (RW0_en && RW0_wmode) begin
for(i=0;i<10;i=i+1) begin
if(RW0_wmask[i]) begin
ram[RW0_addr][i*2 +: 2] <= RW0_wdata[i*2 +: 2];
end
end
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [31:0] RW0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
RW0_random = {$random};
reg_RW0_ren = RW0_random[0];
end
`endif
always @(posedge RW0_clk) RW0_random <= {$random};
assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[19:0];
`else
assign RW0_rdata = ram[reg_RW0_addr];
`endif
endmodule
module array_19_ext(
input RW0_clk,
input [9:0] RW0_addr,
input RW0_en,
input RW0_wmode,
input [9:0] RW0_wmask,
input [179:0] RW0_wdata,
output [179:0] RW0_rdata
);
reg reg_RW0_ren;
reg [9:0] reg_RW0_addr;
reg [179:0] ram [1023:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 1024; initvar = initvar+1)
ram[initvar] = {6 {$random}};
reg_RW0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge RW0_clk)
reg_RW0_ren <= RW0_en && !RW0_wmode;
always @(posedge RW0_clk)
if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
always @(posedge RW0_clk)
if (RW0_en && RW0_wmode) begin
for(i=0;i<10;i=i+1) begin
if(RW0_wmask[i]) begin
ram[RW0_addr][i*18 +: 18] <= RW0_wdata[i*18 +: 18];
end
end
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [191:0] RW0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
RW0_random = {$random, $random, $random, $random, $random, $random};
reg_RW0_ren = RW0_random[0];
end
`endif
always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random, $random, $random};
assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[179:0];
`else
assign RW0_rdata = ram[reg_RW0_addr];
`endif
endmodule
module array_20_ext(
input RW0_clk,
input [9:0] RW0_addr,
input RW0_en,
input RW0_wmode,
input [9:0] RW0_wmask,
input [59:0] RW0_wdata,
output [59:0] RW0_rdata
);
reg reg_RW0_ren;
reg [9:0] reg_RW0_addr;
reg [59:0] ram [1023:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 1024; initvar = initvar+1)
ram[initvar] = {2 {$random}};
reg_RW0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge RW0_clk)
reg_RW0_ren <= RW0_en && !RW0_wmode;
always @(posedge RW0_clk)
if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
always @(posedge RW0_clk)
if (RW0_en && RW0_wmode) begin
for(i=0;i<10;i=i+1) begin
if(RW0_wmask[i]) begin
ram[RW0_addr][i*6 +: 6] <= RW0_wdata[i*6 +: 6];
end
end
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [63:0] RW0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
RW0_random = {$random, $random};
reg_RW0_ren = RW0_random[0];
end
`endif
always @(posedge RW0_clk) RW0_random <= {$random, $random};
assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[59:0];
`else
assign RW0_rdata = ram[reg_RW0_addr];
`endif
endmodule
module array_21_ext(
input RW0_clk,
input [11:0] RW0_addr,
input RW0_en,
input RW0_wmode,
input [15:0] RW0_wmask,
input [95:0] RW0_wdata,
output [95:0] RW0_rdata
);
reg reg_RW0_ren;
reg [11:0] reg_RW0_addr;
reg [95:0] ram [4095:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 4096; initvar = initvar+1)
ram[initvar] = {3 {$random}};
reg_RW0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge RW0_clk)
reg_RW0_ren <= RW0_en && !RW0_wmode;
always @(posedge RW0_clk)
if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
always @(posedge RW0_clk)
if (RW0_en && RW0_wmode) begin
for(i=0;i<16;i=i+1) begin
if(RW0_wmask[i]) begin
ram[RW0_addr][i*6 +: 6] <= RW0_wdata[i*6 +: 6];
end
end
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [95:0] RW0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
RW0_random = {$random, $random, $random};
reg_RW0_ren = RW0_random[0];
end
`endif
always @(posedge RW0_clk) RW0_random <= {$random, $random, $random};
assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[95:0];
`else
assign RW0_rdata = ram[reg_RW0_addr];
`endif
endmodule
module array_22_ext(
input RW0_clk,
input [11:0] RW0_addr,
input RW0_en,
input RW0_wmode,
input [15:0] RW0_wmask,
input [255:0] RW0_wdata,
output [255:0] RW0_rdata
);
reg reg_RW0_ren;
reg [11:0] reg_RW0_addr;
reg [255:0] ram [4095:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 4096; initvar = initvar+1)
ram[initvar] = {8 {$random}};
reg_RW0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge RW0_clk)
reg_RW0_ren <= RW0_en && !RW0_wmode;
always @(posedge RW0_clk)
if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
always @(posedge RW0_clk)
if (RW0_en && RW0_wmode) begin
for(i=0;i<16;i=i+1) begin
if(RW0_wmask[i]) begin
ram[RW0_addr][i*16 +: 16] <= RW0_wdata[i*16 +: 16];
end
end
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [255:0] RW0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
RW0_random = {$random, $random, $random, $random, $random, $random, $random, $random};
reg_RW0_ren = RW0_random[0];
end
`endif
always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random, $random, $random, $random, $random};
assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[255:0];
`else
assign RW0_rdata = ram[reg_RW0_addr];
`endif
endmodule
module array_0_9_ext(
input RW0_clk,
input [11:0] RW0_addr,
input RW0_en,
input RW0_wmode,
input [14:0] RW0_wdata,
output [14:0] RW0_rdata
);
reg reg_RW0_ren;
reg [11:0] reg_RW0_addr;
reg [14:0] ram [4095:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 4096; initvar = initvar+1)
ram[initvar] = {1 {$random}};
reg_RW0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge RW0_clk)
reg_RW0_ren <= RW0_en && !RW0_wmode;
always @(posedge RW0_clk)
if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
always @(posedge RW0_clk)
if (RW0_en && RW0_wmode) begin
for(i=0;i<1;i=i+1) begin
ram[RW0_addr][i*15 +: 15] <= RW0_wdata[i*15 +: 15];
end
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [31:0] RW0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
RW0_random = {$random};
reg_RW0_ren = RW0_random[0];
end
`endif
always @(posedge RW0_clk) RW0_random <= {$random};
assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[14:0];
`else
assign RW0_rdata = ram[reg_RW0_addr];
`endif
endmodule
Reference in New Issue View Git Blame Copy Permalink