OSchip
/
arduino_core_ch32
mirror of https://github.com/openwch/arduino_core_ch32.git
13
0
Fork 5
Code Issues Packages Projects Releases Wiki Activity

adding hardwaret timer and fixing PWM pins errors (#71) 

* add yield(default weak)

* 1.add hardware timer
2.fix PWM pins error
This commit is contained in:
TianpeiLee 2024-03-11 15:32:16 +08:00 committed by GitHub
parent d77f8e0750
commit c40c5c8095
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
22 changed files with 2652 additions and 448 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1780
cores/arduino/HardwareTimer.cpp Normal file
View File

File diff suppressed because it is too large Load Diff

197
cores/arduino/HardwareTimer.h Normal file
View File

@ -0,0 +1,197 @@
/*
Copyright (c) 2017 Daniel Fekete
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
Copyright (c) 2019 STMicroelectronics
Modified to support Arduino_Core_STM32
Modified by TempersLee to support Adruino_Core_CH32
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef HARDWARETIMER_H_
#define HARDWARETIMER_H_
/* Includes ------------------------------------------------------------------*/
#include "timer.h"
#include "ch32yyxx_tim.h"
#if defined(TIM_MODULE_ENABLED) && !defined(TIM_MODULE_ONLY)
#define TIMER_CHANNELS 4 // channel5 and channel 6 are not considered here has they don't have gpio output and they don't have interrupt
#define TIM_CHANNEL_CH1 TIM_CC1E /*!< Timer input/output channel 1 */
#define TIM_CHANNEL_CH1N TIM_CC1NE /*!< Timer complementary output channel 1 */
#define TIM_CHANNEL_CH2 TIM_CC2E /*!< Timer input/output channel 2 */
#define TIM_CHANNEL_CH2N TIM_CC2NE /*!< Timer complementary output channel 2 */
#define TIM_CHANNEL_CH3 TIM_CC3E /*!< Timer input/output channel 3 */
#define TIM_CHANNEL_CH3N TIM_CC3NE /*!< Timer complementary output channel 3 */
#define TIM_CHANNEL_CH4 TIM_CC4E /*!< Timer input/output channel 4 */
typedef enum {
TIMER_DISABLED, // == TIM_OCMODE_TIMING no output, useful for only-interrupt
// Output Compare
TIMER_OUTPUT_COMPARE, // == Obsolete, use TIMER_DISABLED instead. Kept for compatibility reason
TIMER_OUTPUT_COMPARE_ACTIVE, // == TIM_OCMODE_ACTIVE pin is set high when counter == channel compare
TIMER_OUTPUT_COMPARE_INACTIVE, // == TIM_OCMODE_INACTIVE pin is set low when counter == channel compare
TIMER_OUTPUT_COMPARE_TOGGLE, // == TIM_OCMODE_TOGGLE pin toggles when counter == channel compare
TIMER_OUTPUT_COMPARE_PWM1, // == TIM_OCMODE_PWM1 pin high when counter < channel compare, low otherwise
TIMER_OUTPUT_COMPARE_PWM2, // == TIM_OCMODE_PWM2 pin low when counter < channel compare, high otherwise
TIMER_OUTPUT_COMPARE_FORCED_ACTIVE, // == TIM_OCMODE_FORCED_ACTIVE pin always high
TIMER_OUTPUT_COMPARE_FORCED_INACTIVE, // == TIM_OCMODE_FORCED_INACTIVE pin always low
//Input capture
TIMER_INPUT_CAPTURE_RISING, // == TIM_INPUTCHANNELPOLARITY_RISING
TIMER_INPUT_CAPTURE_FALLING, // == TIM_INPUTCHANNELPOLARITY_FALLING
TIMER_INPUT_CAPTURE_BOTHEDGE, // == TIM_INPUTCHANNELPOLARITY_BOTHEDGE
// Used 2 channels for a single pin. One channel in TIM_INPUTCHANNELPOLARITY_RISING another channel in TIM_INPUTCHANNELPOLARITY_FALLING.
// Channels must be used by pair: CH1 with CH2, or CH3 with CH4
// This mode is very useful for Frequency and Dutycycle measurement
TIMER_INPUT_FREQ_DUTY_MEASUREMENT,
TIMER_NOT_USED = 0xFFFF // This must be the last item of this enum
} TimerModes_t;
typedef enum {
TICK_FORMAT, // default
MICROSEC_FORMAT,
HERTZ_FORMAT,
} TimerFormat_t;
typedef enum {
RESOLUTION_1B_COMPARE_FORMAT = 1, // used for Dutycycle: [0 .. 1]
RESOLUTION_2B_COMPARE_FORMAT, // used for Dutycycle: [0 .. 3]
RESOLUTION_3B_COMPARE_FORMAT, // used for Dutycycle: [0 .. 7]
RESOLUTION_4B_COMPARE_FORMAT, // used for Dutycycle: [0 .. 15]
RESOLUTION_5B_COMPARE_FORMAT, // used for Dutycycle: [0 .. 31]
RESOLUTION_6B_COMPARE_FORMAT, // used for Dutycycle: [0 .. 63]
RESOLUTION_7B_COMPARE_FORMAT, // used for Dutycycle: [0 .. 127]
RESOLUTION_8B_COMPARE_FORMAT, // used for Dutycycle: [0 .. 255]
RESOLUTION_9B_COMPARE_FORMAT, // used for Dutycycle: [0 .. 511]
RESOLUTION_10B_COMPARE_FORMAT, // used for Dutycycle: [0 .. 1023]
RESOLUTION_11B_COMPARE_FORMAT, // used for Dutycycle: [0 .. 2047]
RESOLUTION_12B_COMPARE_FORMAT, // used for Dutycycle: [0 .. 4095]
RESOLUTION_13B_COMPARE_FORMAT, // used for Dutycycle: [0 .. 8191]
RESOLUTION_14B_COMPARE_FORMAT, // used for Dutycycle: [0 .. 16383]
RESOLUTION_15B_COMPARE_FORMAT, // used for Dutycycle: [0 .. 32767]
RESOLUTION_16B_COMPARE_FORMAT, // used for Dutycycle: [0 .. 65535]
TICK_COMPARE_FORMAT = 0x80, // default
MICROSEC_COMPARE_FORMAT,
HERTZ_COMPARE_FORMAT,
PERCENT_COMPARE_FORMAT, // used for Dutycycle
} TimerCompareFormat_t;
#ifdef __cplusplus
#include <functional>
using callback_function_t = std::function<void(void)>;
/* Class --------------------------------------------------------*/
class HardwareTimer {
public:
HardwareTimer();
HardwareTimer(TIM_TypeDef *instance);
~HardwareTimer(); // destructor
void setup(TIM_TypeDef *instance); // Setup, only needed if no instance was passed to the constructor
void pause(void); // Pause counter and all output channels
void pauseChannel(uint32_t channel); // Timer is still running but channel (output and interrupt) is disabled
void resume(void); // Resume counter and all output channels
void resumeChannel(uint32_t channel); // Resume only one channel
void setPrescaleFactor(uint32_t prescaler); // set prescaler register (which is factor value - 1)
uint32_t getPrescaleFactor();
void setOverflow(uint32_t val, TimerFormat_t format = TICK_FORMAT); // set AutoReload register depending on format provided
uint32_t getOverflow(TimerFormat_t format = TICK_FORMAT); // return overflow depending on format provided
void setPWM(uint32_t channel, PinName pin, uint32_t frequency, uint32_t dutycycle, callback_function_t PeriodCallback = nullptr, callback_function_t CompareCallback = nullptr); // Set all in one command freq in HZ, Duty in percentage. Including both interrupt.
void setPWM(uint32_t channel, uint32_t pin, uint32_t frequency, uint32_t dutycycle, callback_function_t PeriodCallback = nullptr, callback_function_t CompareCallback = nullptr);
void setCount(uint32_t val, TimerFormat_t format = TICK_FORMAT); // set timer counter to value 'val' depending on format provided
uint32_t getCount(TimerFormat_t format = TICK_FORMAT); // return current counter value of timer depending on format provided
void setMode(uint32_t channel, TimerModes_t mode, PinName pin = NC); // Configure timer channel with specified mode on specified pin if available
void setMode(uint32_t channel, TimerModes_t mode, uint32_t pin);
TimerModes_t getMode(uint32_t channel); // Retrieve configured mode
void setPreloadEnable(bool value); // Configure overflow preload enable setting
uint32_t getCaptureCompare(uint32_t channel, TimerCompareFormat_t format = TICK_COMPARE_FORMAT); // return Capture/Compare register value of specified channel depending on format provided
void setCaptureCompare(uint32_t channel, uint32_t compare, TimerCompareFormat_t format = TICK_COMPARE_FORMAT); // set Compare register value of specified channel depending on format provided
void setInterruptPriority(uint32_t preemptPriority, uint32_t subPriority); // set interrupt priority
//Add interrupt to period update
void attachInterrupt(callback_function_t callback); // Attach interrupt callback which will be called upon update event (timer rollover)
void detachInterrupt(); // remove interrupt callback which was attached to update event
bool hasInterrupt(); //returns true if a timer rollover interrupt has already been set
//Add interrupt to capture/compare channel
void attachInterrupt(uint32_t channel, callback_function_t callback); // Attach interrupt callback which will be called upon compare match event of specified channel
void detachInterrupt(uint32_t channel); // remove interrupt callback which was attached to compare match event of specified channel
bool hasInterrupt(uint32_t channel); //returns true if an interrupt has already been set on the channel compare match
void timerHandleDeinit(); // Timer deinitialization
// Refresh() is useful while timer is running after some registers update
void refresh(void); // Generate update event to force all registers (Autoreload, prescaler, compare) to be taken into account
uint32_t getTimerClkFreq(); // return timer clock frequency in Hz.
static void captureCompareCallback(TIM_HandleTypeDef *htim); // Generic Capture and Compare callback which will call user callback
static void updateCallback(TIM_HandleTypeDef *htim); // Generic Update (rollover) callback which will call user callback
void updateRegistersIfNotRunning(TIM_TypeDef *TIMx); // Take into account registers update immediately if timer is not running,
bool isRunning(); // return true if HardwareTimer is running
bool isRunningChannel(uint32_t channel); // return true if channel is running
// The following function(s) are available for more advanced timer options
TIM_HandleTypeDef *getHandle(); // return the handle address for HAL related configuration
int getChannel(uint32_t channel);
int getLLChannel(uint32_t channel);
int getIT(uint32_t channel);
int getAssociatedChannel(uint32_t channel);
#if defined(TIM_CC1NE)
bool isComplementaryChannel[TIMER_CHANNELS];
#endif
void TIM_OC_ConfigChannel_Static(TIM_TypeDef *htim, TIM_OCInitTypeDef *sConfig, uint32_t Channel);
void TIM_IC_ConfigChannel_Static(TIM_TypeDef *htim, TIM_ICInitTypeDef *sConfig, uint32_t Channel);
private:
TimerModes_t _ChannelMode[TIMER_CHANNELS];
timerObj_t _timerObj;
callback_function_t callbacks[1 + TIMER_CHANNELS]; //Callbacks: 0 for update, 1-4 for channels. (channel5/channel6, if any, doesn't have interrupt)
};
extern timerObj_t *HardwareTimer_Handle[TIMER_NUM];
extern timer_index_t get_timer_index(TIM_TypeDef *htim);
#endif /* __cplusplus */
#endif // TIM_MODULE_ENABLED && TIM_MODULE_ONLY
#endif // HARDWARETIMER_H_

2
cores/arduino/board.h
View File

@ -11,7 +11,7 @@
// #include "dwt.h"
#include "hw_config.h"
// #include "otp.h"
// #include "timer.h"
#include "timer.h"
#include "uart.h"

5
cores/arduino/ch32/PinNamesTypes.h
View File

@ -88,7 +88,7 @@ extern "C" {
#define CH_PIN_SPEED_MASK 0x03
#define CH_PIN_SPEED_SHIFT 6
#define CH_PIN_SPEED_BITS (CH_PIN_SPEED_MASK << CH_PIN_SPEED_SHIFT)
*/
#define CH_PIN_INV_MASK 0x01
#define CH_PIN_INV_SHIFT 20
#define CH_PIN_INV_BIT (CH_PIN_INV_MASK << CH_PIN_INV_SHIFT)
@ -97,6 +97,7 @@ extern "C" {
#define CH_PIN_AN_CTRL_SHIFT 21
#define CH_PIN_ANALOG_CONTROL_BIT (CH_PIN_AN_CTRL_MASK << CH_PIN_AN_CTRL_SHIFT)
/*
#define CH_PIN_AN_CHAN_BANK_B_MASK 0x01
#define CH_PIN_AN_CHAN_BANK_B_SHIFT 22
#define CH_PIN_ANALOG_CHAN_BANK_B_BIT (CH_PIN_AN_CHAN_BANK_B_MASK << CH_PIN_AN_CHAN_BANK_B_SHIFT)
@ -115,8 +116,10 @@ extern "C" {
#define CH_PIN_SPEED(X) (((X) >> CH_PIN_SPEED_SHIFT) & CH_PIN_SPEED_MASK)
#define CH_PIN_AFNUM(X) (((X) >> CH_PIN_AFNUM_SHIFT) & CH_PIN_AFNUM_MASK)
#define CH_PIN_CHANNEL(X) (((X) >> CH_PIN_CHAN_SHIFT) & CH_PIN_CHAN_MASK)
*/
#define CH_PIN_INVERTED(X) (((X) >> CH_PIN_INV_SHIFT) & CH_PIN_INV_MASK)
#define CH_PIN_ANALOG_CONTROL(X) (((X) >> CH_PIN_AN_CTRL_SHIFT) & CH_PIN_AN_CTRL_MASK)
/*
#define CH_PIN_ANALOG_CHANNEL_BANK_B(X) (((X) >> CH_PIN_AN_CHAN_BANK_B_SHIFT) & CH_PIN_AN_CHAN_BANK_B_MASK)
#define CH_PIN_MODE(X) ((CH_PIN_OD((X)) << 4) | \
(CH_PIN_FUNCTION((X)) & (~CH_PIN_OD_BITS)))

3
cores/arduino/ch32/analog.h
View File

@ -44,8 +44,7 @@
#include "ch32_def.h"
#include "PeripheralPins.h"
#include "variant.h"
// #include "HardwareTimer.h"
#include "HardwareTimer.h"
#ifdef __cplusplus
extern "C" {

473
cores/arduino/ch32/timer.c Normal file
View File

@ -0,0 +1,473 @@
/**
*******************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* All rights reserved.
*
* This software component is licensed by WCH under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
modified by TempersLee
*/
#include "core_debug.h"
#include "timer.h"
#include "board.h"
#ifdef __cplusplus
extern "C" {
#endif
#if defined(TIM_MODULE_ENABLED)
/* Private Functions */
/* Aim of the function is to get _timerObj pointer using htim pointer */
/* Highly inspired from magical linux kernel's "container_of" */
/* (which was not directly used since not compatible with IAR toolchain) */
timerObj_t *get_timer_obj(TIM_HandleTypeDef *htim)
{
timerObj_t *obj;
obj = (timerObj_t *)((char *)htim - offsetof(timerObj_t, handle));
return (obj);
}
/**
* @brief TIMER Initialization - clock init and nvic init
* @param htim_base: TIM handle
* @retval None
*/
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim_base)
{
timerObj_t *obj = get_timer_obj(htim_base);
enableTimerClock(htim_base);
// configure Update interrupt
NVIC_SetPriority(getTimerUpIrq(htim_base->Instance), obj->preemptPriority | obj->subPriority);
NVIC_EnableIRQ(getTimerUpIrq(htim_base->Instance));
if (getTimerCCIrq(htim_base->Instance) != getTimerUpIrq(htim_base->Instance)) {
// configure Capture Compare interrupt
NVIC_SetPriority(getTimerCCIrq(htim_base->Instance), obj->preemptPriority | obj->subPriority);
NVIC_EnableIRQ(getTimerCCIrq(htim_base->Instance));
}
}
/**
* @brief TIMER Deinitialization - clock and nvic
* @param htim_base: TIM handle
* @retval None
*/
void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim_base)
{
disableTimerClock(htim_base);
NVIC_DisableIRQ(getTimerUpIrq(htim_base->Instance));
NVIC_DisableIRQ(getTimerCCIrq(htim_base->Instance));
}
/**
* @brief Initializes the TIM Output Compare MSP.
* @param htim: TIM handle
* @retval None
*/
void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
{
timerObj_t *obj = get_timer_obj(htim);
enableTimerClock(htim);
// configure Update interrupt
NVIC_SetPriority(getTimerUpIrq(htim->Instance), obj->preemptPriority | obj->subPriority);
NVIC_EnableIRQ(getTimerUpIrq(htim->Instance));
if (getTimerCCIrq(htim->Instance) != getTimerUpIrq(htim->Instance)) {
// configure Capture Compare interrupt
NVIC_SetPriority(getTimerCCIrq(htim->Instance), obj->preemptPriority | obj->subPriority);
NVIC_EnableIRQ(getTimerCCIrq(htim->Instance));
}
}
/**
* @brief DeInitialize TIM Output Compare MSP.
* @param htim: TIM handle
* @retval None
*/
void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
{
disableTimerClock(htim);
NVIC_DisableIRQ(getTimerUpIrq(htim->Instance));
NVIC_DisableIRQ(getTimerCCIrq(htim->Instance));
}
/**
* @brief Initializes the TIM Input Capture MSP.
* @param htim: TIM handle
* @retval None
*/
void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
{
enableTimerClock(htim);
}
/**
* @brief DeInitialize TIM Input Capture MSP.
* @param htim: TIM handle
* @retval None
*/
void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
{
disableTimerClock(htim);
}
/* Exported functions */
/**
* @brief Enable the timer clock
* @param htim: TIM handle
* @retval None
*/
void enableTimerClock(TIM_HandleTypeDef *htim)
{
// Enable TIM clock
#if defined(TIM1_BASE)
if (htim->Instance == TIM1) {
RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1, ENABLE);
}
#endif
#if defined(TIM2_BASE)
if (htim->Instance == TIM2) {
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);
}
#endif
#if defined(TIM3_BASE)
if (htim->Instance == TIM3) {
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE);
}
#endif
#if defined(TIM4_BASE)
if (htim->Instance == TIM4) {
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE);
}
#endif
#if defined(TIM5_BASE)
if (htim->Instance == TIM5) {
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM5, ENABLE);
}
#endif
#if defined(TIM6_BASE)
if (htim->Instance == TIM6) {
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM6, ENABLE);
}
#endif
#if defined(TIM7_BASE)
if (htim->Instance == TIM7) {
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM7, ENABLE);
}
#endif
#if defined(TIM8_BASE)
if (htim->Instance == TIM8) {
RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM8, ENABLE);
}
#endif
#if defined(TIM9_BASE)
if (htim->Instance == TIM9) {
RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM9, ENABLE);
}
#endif
#if defined(TIM10_BASE)
if (htim->Instance == TIM10) {
RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM10, ENABLE);
}
#endif
}
/**
* @brief Disable the timer clock
* @param htim: TIM handle
* @retval None
*/
void disableTimerClock(TIM_HandleTypeDef *htim)
{
// Enable TIM clock
#if defined(TIM1_BASE)
if (htim->Instance == TIM1) {
RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1, DISABLE);
}
#endif
#if defined(TIM2_BASE)
if (htim->Instance == TIM2) {
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, DISABLE);
}
#endif
#if defined(TIM3_BASE)
if (htim->Instance == TIM3) {
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, DISABLE);
}
#endif
#if defined(TIM4_BASE)
if (htim->Instance == TIM4) {
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, DISABLE);
}
#endif
#if defined(TIM5_BASE)
if (htim->Instance == TIM5) {
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM5, DISABLE);
}
#endif
#if defined(TIM6_BASE)
if (htim->Instance == TIM6) {
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM6, DISABLE);
}
#endif
#if defined(TIM7_BASE)
if (htim->Instance == TIM7) {
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM7, DISABLE);
}
#endif
#if defined(TIM8_BASE)
if (htim->Instance == TIM8) {
RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM8, DISABLE);
}
#endif
#if defined(TIM9_BASE)
if (htim->Instance == TIM9) {
RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM9, DISABLE);
}
#endif
#if defined(TIM10_BASE)
if (htim->Instance == TIM10) {
RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM10, DISABLE);
}
#endif
}
/**
* @brief This function return IRQ number corresponding to update interrupt event of timer instance.
* @param tim: timer instance
* @retval IRQ number
*/
IRQn_Type getTimerUpIrq(TIM_TypeDef *tim)
{
IRQn_Type IRQn = NonMaskableInt_IRQn;
if (tim != (TIM_TypeDef *)NC) {
/* Get IRQn depending on TIM instance */
switch ((uint32_t)tim) {
#if defined(TIM1_BASE)
case (uint32_t)TIM1_BASE:
IRQn = TIM1_UP_IRQn;
break;
#endif
#if defined(TIM2_BASE)
case (uint32_t)TIM2_BASE:
IRQn = TIM2_IRQn;
break;
#endif
#if defined(TIM3_BASE)
case (uint32_t)TIM3_BASE:
IRQn = TIM3_IRQn;
break;
#endif
#if defined(TIM4_BASE)
case (uint32_t)TIM4_BASE:
IRQn = TIM4_IRQn;
break;
#endif
#if defined(TIM5_BASE) && !defined(CH32V10x) && !defined(CH32V20x)
case (uint32_t)TIM5_BASE:
IRQn = TIM5_IRQn;
break;
#endif
#if defined(TIM6_BASE) && !defined(CH32V10x) && !defined(CH32V20x)
case (uint32_t)TIM6_BASE:
IRQn = TIM6_IRQn;
break;
#endif
#if defined(TIM7_BASE) && !defined(CH32V10x) && !defined(CH32V20x)
case (uint32_t)TIM7_BASE:
IRQn = TIM7_IRQn;
break;
#endif
#if defined(TIM8_BASE) && !defined(CH32V10x) && !defined(CH32V20x)
case (uint32_t)TIM8_BASE:
IRQn = TIM8_UP_IRQn;
break;
#endif
#if defined(TIM9_BASE) && !defined(CH32V10x) && !defined(CH32V20x)
case (uint32_t)TIM9_BASE:
IRQn = TIM9_UP_IRQn;
break;
#endif
#if defined(TIM10_BASE) && !defined(CH32V10x) && !defined(CH32V20x)
case (uint32_t)TIM10_BASE:
IRQn = TIM10_UP_IRQn;
break;
#endif
default:
_Error_Handler("TIM: Unknown timer IRQn", (int)tim);
break;
}
}
return IRQn;
}
/**
* @brief This function return IRQ number corresponding to Capture or Compare interrupt event of timer instance.
* @param tim: timer instance
* @retval IRQ number
*/
IRQn_Type getTimerCCIrq(TIM_TypeDef *tim)
{
IRQn_Type IRQn = NonMaskableInt_IRQn;
if (tim != (TIM_TypeDef *)NC) {
/* Get IRQn depending on TIM instance */
switch ((uint32_t)tim) {
#if defined(TIM1_BASE)
case (uint32_t)TIM1_BASE:
IRQn = TIM1_CC_IRQn;
break;
#endif
#if defined(TIM2_BASE)
case (uint32_t)TIM2_BASE:
IRQn = TIM2_IRQn;
break;
#endif
#if defined(TIM3_BASE)
case (uint32_t)TIM3_BASE:
IRQn = TIM3_IRQn;
break;
#endif
#if defined(TIM4_BASE)
case (uint32_t)TIM4_BASE:
IRQn = TIM4_IRQn;
break;
#endif
#if defined(TIM5_BASE) && !defined(CH32V20x) && !defined(CH32V10x)
case (uint32_t)TIM5_BASE:
IRQn = TIM5_IRQn;
break;
#endif
#if defined(TIM6_BASE) && !defined(CH32V20x) && !defined(CH32V10x)
case (uint32_t)TIM6_BASE:
IRQn = TIM6_IRQn;
break;
#endif
#if defined(TIM7_BASE) && !defined(CH32V20x) && !defined(CH32V10x)
case (uint32_t)TIM7_BASE:
IRQn = TIM7_IRQn;
break;
#endif
#if defined(TIM8_BASE) && !defined(CH32V20x) && !defined(CH32V10x)
case (uint32_t)TIM8_BASE:
IRQn = TIM8_CC_IRQn;
break;
#endif
#if defined(TIM9_BASE) && !defined(CH32V20x) && !defined(CH32V10x)
case (uint32_t)TIM9_BASE:
IRQn = TIM9_CC_IRQn;
break;
#endif
#if defined(TIM10_BASE) && !defined(CH32V20x) && !defined(CH32V10x)
case (uint32_t)TIM10_BASE:
IRQn = TIM10_CC_IRQn;
break;
#endif
default:
_Error_Handler("TIM: Unknown timer IRQn", (int)tim);
break;
}
}
return IRQn;
}
/**
* @brief This function return the timer clock source.
* @param tim: timer instance
* @retval 1 = PCLK1 or 2 = PCLK2
*/
uint8_t getTimerClkSrc(TIM_TypeDef *tim)
{
uint8_t clkSrc = 0;
if (tim != (TIM_TypeDef *)NC)
{
/* Get source clock depending on TIM instance */
switch ((uint32_t)tim) {
#if defined(TIM2_BASE)
case (uint32_t)TIM2:
#endif
#if defined(TIM3_BASE)
case (uint32_t)TIM3:
#endif
#if defined(TIM4_BASE)
case (uint32_t)TIM4:
#endif
#if defined(TIM5_BASE)
case (uint32_t)TIM5:
#endif
#if defined(TIM6_BASE)
case (uint32_t)TIM6:
#endif
#if defined(TIM7_BASE)
case (uint32_t)TIM7:
#endif
clkSrc = 1;
break;
#if defined(TIM1_BASE)
case (uint32_t)TIM1:
#endif
#if defined(TIM8_BASE)
case (uint32_t)TIM8:
#endif
#if defined(TIM9_BASE)
case (uint32_t)TIM9:
#endif
#if defined(TIM10_BASE)
case (uint32_t)TIM10:
#endif
clkSrc = 2;
break;
default:
_Error_Handler("TIM: Unknown timer instance", (int)tim);
break;
}
}
return clkSrc;
}
/**
* @brief Return HAL timer channel linked to a PinName
* @param pin: PinName
* @retval Valid HAL channel
*/
uint32_t getTimerChannel(PinName pin)
{
uint32_t function = pinmap_function(pin, PinMap_TIM);
uint32_t channel = 0;
switch (CH_PIN_CHANNEL(function)) {
case 1:
channel = TIM_Channel_1;
break;
case 2:
channel = TIM_Channel_2;
break;
case 3:
channel = TIM_Channel_3;
break;
case 4:
channel = TIM_Channel_4;
break;
default:
_Error_Handler("TIM: Unknown timer channel", (int)(CH_PIN_CHANNEL(function)));
break;
}
return channel;
}
#endif /* TIM_MODULE_ENABLED */
#ifdef __cplusplus
}
#endif

228
cores/arduino/ch32/timer.h
View File

@ -18,177 +18,27 @@
/* Includes ------------------------------------------------------------------*/
#include "ch32_def.h"
#include "PinNames.h"
#include "variant.h"
#ifdef __cplusplus
extern "C" {
#endif
#if defined(HAL_TIM_MODULE_ENABLED) && !defined(HAL_TIM_MODULE_ONLY)
#if defined(TIM_MODULE_ENABLED)
/* Exported constants --------------------------------------------------------*/
#ifndef TIM_IRQ_PRIO
#if (__CORTEX_M == 0x00U)
#define TIM_IRQ_PRIO 3
#else
#define TIM_IRQ_PRIO 14
#endif /* __CORTEX_M */
#define TIM_IRQ_PRIO 0x80
#endif /* TIM_IRQ_PRIO */
#ifndef TIM_IRQ_SUBPRIO
#define TIM_IRQ_SUBPRIO 0
#define TIM_IRQ_SUBPRIO 0x40
#endif
#if defined(TIM1_BASE) && !defined(TIM1_IRQn)
#if defined(CH32F0xx) || defined(CH32G0xx)
#define TIM1_IRQn TIM1_BRK_UP_TRG_COM_IRQn
#define TIM1_IRQHandler TIM1_BRK_UP_TRG_COM_IRQHandler
#elif defined(CH32F1xx) ||defined(CH32G4xx)
#define TIM1_IRQn TIM1_UP_TIM16_IRQn
#if !defined (TIM10_BASE)
#define TIM1_IRQHandler TIM1_UP_TIM16_IRQHandler
#elif defined (TIM10_BASE)
#define TIM1_IRQHandler TIM1_UP_TIM10_IRQHandler
#endif
#elif defined(CH32F3xx) || defined(CH32L4xx) || defined(CH32WBxx)
#define TIM1_IRQn TIM1_UP_TIM16_IRQn
#define TIM1_IRQHandler TIM1_UP_TIM16_IRQHandler
#elif defined(CH32F2xx) || defined(CH32F4xx) || defined(CH32F7xx)
#if !defined (TIM10_BASE)
#define TIM1_IRQn TIM1_UP_IRQn
#define TIM1_IRQHandler TIM1_UP_IRQHandler
#else
#define TIM1_IRQn TIM1_UP_TIM10_IRQn
#define TIM1_IRQHandler TIM1_UP_TIM10_IRQHandler
#endif
#elif defined(CH32H7xx) || defined(CH32L5xx) || defined(CH32MP1xx) ||\
defined(CH32U5xx) || defined(CH32WLxx)
#define TIM1_IRQn TIM1_UP_IRQn
#define TIM1_IRQHandler TIM1_UP_IRQHandler
#endif
#endif
#if defined(TIM3_BASE) && !defined(TIM3_IRQn)
#if defined(CH32G0xx) && defined(TIM4_BASE)
#define TIM3_IRQn TIM3_TIM4_IRQn
#define TIM3_IRQHandler TIM3_TIM4_IRQHandler
#endif
#endif
#if defined(TIM4_BASE) && !defined(TIM4_IRQn)
#if defined(CH32G0xx)
#define TIM4_IRQn TIM3_TIM4_IRQn
#endif
#endif
#if defined(TIM6_BASE) && !defined(TIM6_IRQn)
#if defined(DAC_BASE) || defined(DAC1_BASE)
#if defined(CH32G0xx)
#define TIM6_IRQn TIM6_DAC_LPTIM1_IRQn
#define TIM6_IRQHandler TIM6_DAC_LPTIM1_IRQHandler
#elif !defined(CH32F1xx) && !defined(CH32L1xx) && !defined(CH32L5xx) &&\
!defined(CH32MP1xx) && !defined(CH32U5xx)
#define TIM6_IRQn TIM6_DAC_IRQn
#define TIM6_IRQHandler TIM6_DAC_IRQHandler
#endif
#endif
#endif
#if defined(TIM7_BASE) && !defined(TIM7_IRQn)
#if defined(CH32G0xx) && defined(LPTIM2_BASE)
#define TIM7_IRQn TIM7_LPTIM2_IRQn
#define TIM7_IRQHandler TIM7_LPTIM2_IRQHandler
#elif defined(CH32G4xx)
#define TIM7_IRQn TIM7_DAC_IRQn
#define TIM7_IRQHandler TIM7_DAC_IRQHandler
#endif
#endif
#if defined(TIM8_BASE) && !defined(TIM8_IRQn)
#if defined(CH32F1xx) || defined(CH32F2xx) ||defined(CH32F4xx) || defined(CH32F7xx)\
|| defined(CH32H7xx)
#define TIM8_IRQn TIM8_UP_TIM13_IRQn
#define TIM8_IRQHandler TIM8_UP_TIM13_IRQHandler
#elif defined(CH32F3xx) || defined(CH32G4xx) || defined(CH32L4xx) ||\
defined(CH32L5xx) || defined(CH32MP1xx) || defined(CH32U5xx)
#define TIM8_IRQn TIM8_UP_IRQn
#define TIM8_IRQHandler TIM8_UP_IRQHandler
#endif
#endif
#if defined(TIM9_BASE) && !defined(TIM9_IRQn)
#if defined(CH32F1xx) || defined(CH32F2xx) ||defined(CH32F4xx) || defined(CH32F7xx)
#define TIM9_IRQn TIM1_BRK_TIM9_IRQn
#define TIM9_IRQHandler TIM1_BRK_TIM9_IRQHandler
#endif
#endif
#if defined(TIM10_BASE) && !defined(TIM10_IRQn)
#if defined(CH32F1xx) || defined(CH32F2xx) ||defined(CH32F4xx) || defined(CH32F7xx)
#define TIM10_IRQn TIM1_UP_TIM10_IRQn
//TIM10_IRQHandler is mapped on TIM1_IRQHandler when TIM10_IRQn is not defined
#endif
#endif
#if defined(TIM11_BASE) && !defined(TIM11_IRQn)
#if defined(CH32F1xx) || defined(CH32F2xx) ||defined(CH32F4xx) || defined(CH32F7xx)
#define TIM11_IRQn TIM1_TRG_COM_TIM11_IRQn
#define TIM11_IRQHandler TIM1_TRG_COM_TIM11_IRQHandler
#endif
#endif
#if defined(TIM12_BASE) && !defined(TIM12_IRQn)
#if defined(CH32F1xx) || defined(CH32F2xx) ||defined(CH32F4xx) || defined(CH32F7xx)\
|| defined(CH32H7xx)
#define TIM12_IRQn TIM8_BRK_TIM12_IRQn
#define TIM12_IRQHandler TIM8_BRK_TIM12_IRQHandler
#endif
#endif
#if defined(TIM13_BASE) && !defined(TIM13_IRQn)
#if defined(CH32F1xx) || defined(CH32F2xx) ||defined(CH32F4xx) || defined(CH32F7xx)\
|| defined(CH32H7xx)
#define TIM13_IRQn TIM8_UP_TIM13_IRQn
#endif
#endif
#if defined(TIM14_BASE) && !defined(TIM14_IRQn)
#if defined(CH32F1xx) || defined(CH32F2xx) ||defined(CH32F4xx) || defined(CH32F7xx)\
|| defined(CH32H7xx)
#define TIM14_IRQn TIM8_TRG_COM_TIM14_IRQn
#define TIM14_IRQHandler TIM8_TRG_COM_TIM14_IRQHandler
#endif
#endif
#if defined(TIM15_BASE) && !defined(TIM15_IRQn)
#if defined(CH32F1xx) || defined(CH32F3xx) || defined(CH32G4xx) || defined(CH32L4xx)
#define TIM15_IRQn TIM1_BRK_TIM15_IRQn
#define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
#endif
#endif
#if defined(TIM16_BASE) && !defined(TIM16_IRQn)
#if defined(CH32F1xx) || defined(CH32F3xx) || defined(CH32G4xx) || defined(CH32L4xx) || \
defined(CH32WBxx)
#define TIM16_IRQn TIM1_UP_TIM16_IRQn
//TIM16_IRQHandler is mapped on TIM1_IRQHandler when TIM16_IRQn is not defined
#elif defined(CH32G0xx) && defined(FDCAN1_BASE)
#define TIM16_IRQn TIM16_FDCAN_IT0_IRQn
#define TIM16_IRQHandler TIM16_FDCAN_IT0_IRQHandler
#endif
#endif
#if defined(TIM17_BASE) && !defined(TIM17_IRQn)
#if defined(CH32F1xx) || defined(CH32F3xx) || defined(CH32G4xx) || defined(CH32L4xx) || \
defined(CH32WBxx)
#define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
#define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
#elif defined(CH32G0xx) && defined(FDCAN1_BASE)
#define TIM17_IRQn TIM17_FDCAN_IT1_IRQn
#define TIM17_IRQHandler TIM17_FDCAN_IT1_IRQHandler
#endif
#endif
#if defined(TIM18_BASE) && !defined(TIM18_IRQn)
#if defined(CH32F3xx)
#define TIM18_IRQn TIM18_DAC2_IRQn
#define TIM18_IRQHandler TIM18_DAC2_IRQHandler
#endif
#endif
#if defined(TIM20_BASE) && !defined(TIM20_IRQn)
#if defined(CH32F3xx) || defined(CH32G4xx)
#define TIM20_IRQn TIM20_UP_IRQn
#define TIM20_IRQHandler TIM20_UP_IRQHandler
#endif
#endif
typedef enum {
#if defined(TIM1_BASE)
@ -220,48 +70,36 @@ typedef enum {
#endif
#if defined(TIM10_BASE)
TIMER10_INDEX,
#endif
#if defined(TIM11_BASE)
TIMER11_INDEX,
#endif
#if defined(TIM12_BASE)
TIMER12_INDEX,
#endif
#if defined(TIM13_BASE)
TIMER13_INDEX,
#endif
#if defined(TIM14_BASE)
TIMER14_INDEX,
#endif
#if defined(TIM15_BASE)
TIMER15_INDEX,
#endif
#if defined(TIM16_BASE)
TIMER16_INDEX,
#endif
#if defined(TIM17_BASE)
TIMER17_INDEX,
#endif
#if defined(TIM18_BASE)
TIMER18_INDEX,
#endif
#if defined(TIM19_BASE)
TIMER19_INDEX,
#endif
#if defined(TIM20_BASE)
TIMER20_INDEX,
#endif
#if defined(TIM21_BASE)
TIMER21_INDEX,
#endif
#if defined(TIM22_BASE)
TIMER22_INDEX,
#endif
TIMER_NUM,
UNKNOWN_TIMER = 0XFFFF
} timer_index_t;
typedef enum
{
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */
HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */
HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */
HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */
HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */
HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */
HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */
} TIM_ActiveChannel;
typedef struct
{
TIM_TypeDef *Instance;
TIM_TimeBaseInitTypeDef Init;
TIM_ActiveChannel Channel; //ÊÇ·ñÐèÒª£¿
/* //Not yet considered
TIM_OCInitTypeDef OC_Init;
TIM_ICInitTypeDef IC_Init;
*/
}TIM_HandleTypeDef;
// This structure is used to be able to get HardwareTimer instance (C++ class)
// from handler (C structure) specially for interrupt management
typedef struct {
@ -286,7 +124,7 @@ IRQn_Type getTimerCCIrq(TIM_TypeDef *tim);
uint32_t getTimerChannel(PinName pin);
#endif /* HAL_TIM_MODULE_ENABLED && !HAL_TIM_MODULE_ONLY */
#endif /* TIM_MODULE_ENABLED && TIM_MODULE_ONLY */
#ifdef __cplusplus
}

22
variants/CH32V00x/CH32V003F4/PeripheralPins.c
View File

@ -62,18 +62,18 @@ WEAK const PinMap PinMap_I2C_SCL[] = {
//*** TIM ***
#ifdef TIM_MODULE_ENABLED
WEAK const PinMap PinMap_TIM[] = {
{PD_4, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_NONE, 1, 0)}, // TIM2_CH1
{PD_3, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_DISABLE, 2, 0)}, // TIM2_CH2
{PC_0, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_DISABLE, 3, 0)}, // TIM2_CH3
{PC_1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_DISABLE, 4, 0)}, // TIM2_CH4
{PD_4, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM2_DISABLE, 1)}, // TIM2_CH1
{PD_3, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM2_DISABLE, 2)}, // TIM2_CH2
{PC_0, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM2_DISABLE, 3)}, // TIM2_CH3
{PD_7, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM2_DISABLE, 4)}, // TIM2_CH4
{PD_2, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 1, 0)}, // TIM1_CH1
{PA_1, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 2, 0)}, // TIM1_CH2
{PC_3, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 3, 0)}, // TIM1_CH3
{PC_4, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 4, 0)}, // TIM1_CH4
{PD_0, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 1, 1)}, // TIM1_CH1N
{PA_2, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 2, 1)}, // TIM1_CH2N
{PD_1, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 3, 1)}, // TIM1_CH3N
{PD_2, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 1)}, // TIM1_CH1
{PA_1, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 2)}, // TIM1_CH2
{PC_3, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 3)}, // TIM1_CH3
{PC_4, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 4)}, // TIM1_CH4
{PD_0, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 1)}, // TIM1_CH1N
{PA_2, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 2)}, // TIM1_CH2N
{PD_1, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 3)}, // TIM1_CH3N
{NC, NP, 0, 0, 0}
};
#endif

5
variants/CH32V00x/CH32V003F4/variant_CH32V003F4.h
View File

@ -13,10 +13,11 @@
#pragma once
/* ENABLE Peripherals */
// #define ADC_MODULE_ENABLED
#define ADC_MODULE_ENABLED
#define UART_MODULE_ENABLED
// #define SPI_MODULE_ENABLED
#define SPI_MODULE_ENABLED
#define I2C_MODULE_ENABLED
#define TIM_MODULE_ENABLED
/* CH32V003F4 Pins */
#define PA1 PIN_A1

61
variants/CH32V10x/CH32V103R8T6/PeripheralPins.c
View File

@ -66,44 +66,29 @@ WEAK const PinMap PinMap_I2C_SCL[] = {
//*** TIM ***
#ifdef TIM_MODULE_ENABLED
WEAK const PinMap PinMap_TIM[] = {
{PA_0, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_NONE, 1, 0)}, // TIM2_CH1
{PA_0_ALT1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_PARTIAL_2, 1, 0)}, // TIM2_CH1
{PA_1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_DISABLE, 2, 0)}, // TIM2_CH2
{PA_1_ALT1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_PARTIAL_2, 2, 0)}, // TIM2_CH2
{PA_2, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_DISABLE, 3, 0)}, // TIM2_CH3
{PA_2_ALT1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_PARTIAL_1, 3, 0)}, // TIM2_CH3
{PA_3, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_DISABLE, 4, 0)}, // TIM2_CH4
{PA_3_ALT1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_PARTIAL_1, 4, 0)}, // TIM2_CH4
{PA_6, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM3_DISABLE, 1, 0)}, // TIM3_CH1
{PA_7, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 1, 1)}, // TIM1_CH1N
{PA_7_ALT1, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM3_DISABLE, 2, 0)}, // TIM3_CH2
{PA_8, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 1, 0)}, // TIM1_CH1
{PA_8_ALT1, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 1, 0)}, // TIM1_CH1
{PA_9, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 2, 0)}, // TIM1_CH2
{PA_9_ALT1, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 2, 0)}, // TIM1_CH2
{PA_10, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 3, 0)}, // TIM1_CH3
{PA_10_ALT1, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 3, 0)}, // TIM1_CH3
{PA_11, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 4, 0)}, // TIM1_CH4
{PA_11_ALT1, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 4, 0)}, // TIM1_CH4
{PA_15, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_PARTIAL_1, 1, 0)}, // TIM2_CH1
{PA_15_ALT1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_ENABLE, 1, 0)}, // TIM2_CH1
{PB_0, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 2, 1)}, // TIM1_CH2N
{PB_0_ALT1, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM3_DISABLE, 3, 0)}, // TIM3_CH3
{PB_0_ALT2, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM3_PARTIAL, 3, 0)}, // TIM3_CH3
{PB_1, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 3, 1)}, // TIM1_CH3N
{PB_1_ALT1, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM3_DISABLE, 4, 0)}, // TIM3_CH4
{PB_1_ALT2, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM3_PARTIAL, 4, 0)}, // TIM3_CH4
{PB_3, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_PARTIAL_1, 2, 0)}, // TIM2_CH2
{PB_3_ALT1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_ENABLE, 2, 0)}, // TIM2_CH2
{PB_4, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM3_PARTIAL, 1, 0)}, // TIM3_CH1
{PB_5, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM3_PARTIAL, 2, 0)}, // TIM3_CH2
{PB_10, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_PARTIAL_2, 3, 0)}, // TIM2_CH3
{PB_10_ALT1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_ENABLE, 3, 0)}, // TIM2_CH3
{PB_11, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_PARTIAL_2, 4, 0)}, // TIM2_CH4
{PB_11_ALT1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_ENABLE, 4, 0)}, // TIM2_CH4
{PB_13, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 1, 1)}, // TIM1_CH1N
{PB_14, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 2, 1)}, // TIM1_CH2N
{PB_15, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 3, 1)}, // TIM1_CH3N
{PA_0, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM2_DISABLE, 1)}, // TIM2_CH1
{PA_1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM2_DISABLE, 2)}, // TIM2_CH2
{PA_2, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM2_DISABLE, 3)}, // TIM2_CH3
{PA_3, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM2_DISABLE, 4)}, // TIM2_CH4
{PA_6, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM3_DISABLE, 1)}, // TIM3_CH1
{PA_7, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM3_DISABLE, 2)}, // TIM3_CH2
{PB_0, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM3_DISABLE, 3)}, // TIM3_CH3
{PB_1, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM3_DISABLE, 4)}, // TIM3_CH4
{PB_6, TIM4, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM4_DISABLE, 1)}, // TIM4_CH1
{PB_7, TIM4, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM4_DISABLE, 2)}, // TIM4_CH2
{PB_8, TIM4, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM4_DISABLE, 3)}, // TIM4_CH3
{PB_9, TIM4, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM4_DISABLE, 4)}, // TIM4_CH4
{PA_8, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 1)}, // TIM1_CH1
{PA_9, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 2)}, // TIM1_CH2
{PA_10, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 3)}, // TIM1_CH3
{PA_11, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 4)}, // TIM1_CH4
{PB_13, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 1)}, // TIM1_CH1N
{PB_14, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 2)}, // TIM1_CH2N
{PA_15, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 3)}, // TIM1_CH3N
{NC, NP, 0, 0, 0}
};
#endif

1
variants/CH32V10x/CH32V103R8T6/variant_CH32V103R8T6.h
View File

@ -17,6 +17,7 @@
#define UART_MODULE_ENABLED
#define SPI_MODULE_ENABLED
#define I2C_MODULE_ENABLED
#define TIM_MODULE_ENABLED
/* CH32V307VCT6 Pins */

63
variants/CH32V20x/CH32V203C6/PeripheralPins.c
View File

@ -76,45 +76,30 @@ WEAK const PinMap PinMap_I2C_SCL[] = {
//*** TIM ***
#ifdef TIM_MODULE_ENABLED
WEAK const PinMap PinMap_TIM[] = {
{PA_0, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_NONE, 1, 0)}, // TIM2_CH1
{PA_0_ALT1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_PARTIAL_2, 1, 0)}, // TIM2_CH1
{PA_1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_DISABLE, 2, 0)}, // TIM2_CH2
{PA_1_ALT1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_PARTIAL_2, 2, 0)}, // TIM2_CH2
{PA_2, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_DISABLE, 3, 0)}, // TIM2_CH3
{PA_2_ALT1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_PARTIAL_1, 3, 0)}, // TIM2_CH3
{PA_3, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_DISABLE, 4, 0)}, // TIM2_CH4
{PA_3_ALT1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_PARTIAL_1, 4, 0)}, // TIM2_CH4
{PA_6, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM3_DISABLE, 1, 0)}, // TIM3_CH1
{PA_7, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 1, 1)}, // TIM1_CH1N
{PA_7_ALT1, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM3_DISABLE, 2, 0)}, // TIM3_CH2
{PA_8, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 1, 0)}, // TIM1_CH1
{PA_8_ALT1, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 1, 0)}, // TIM1_CH1
{PA_9, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 2, 0)}, // TIM1_CH2
{PA_9_ALT1, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 2, 0)}, // TIM1_CH2
{PA_10, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 3, 0)}, // TIM1_CH3
{PA_10_ALT1, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 3, 0)}, // TIM1_CH3
{PA_11, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 4, 0)}, // TIM1_CH4
{PA_11_ALT1, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 4, 0)}, // TIM1_CH4
{PA_15, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_PARTIAL_1, 1, 0)}, // TIM2_CH1
{PA_15_ALT1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_ENABLE, 1, 0)}, // TIM2_CH1
{PB_0, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 2, 1)}, // TIM1_CH2N
{PB_0_ALT1, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM3_DISABLE, 3, 0)}, // TIM3_CH3
{PB_0_ALT2, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM3_PARTIAL, 3, 0)}, // TIM3_CH3
{PB_1, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 3, 1)}, // TIM1_CH3N
{PB_1_ALT1, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM3_DISABLE, 4, 0)}, // TIM3_CH4
{PB_1_ALT2, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM3_PARTIAL, 4, 0)}, // TIM3_CH4
{PB_3, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_PARTIAL_1, 2, 0)}, // TIM2_CH2
{PB_3_ALT1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_ENABLE, 2, 0)}, // TIM2_CH2
{PB_4, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM3_PARTIAL, 1, 0)}, // TIM3_CH1
{PB_5, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM3_PARTIAL, 2, 0)}, // TIM3_CH2
{PB_10, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_PARTIAL_2, 3, 0)}, // TIM2_CH3
{PB_10_ALT1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_ENABLE, 3, 0)}, // TIM2_CH3
{PB_11, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_PARTIAL_2, 4, 0)}, // TIM2_CH4
{PB_11_ALT1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_ENABLE, 4, 0)}, // TIM2_CH4
{PB_13, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 1, 1)}, // TIM1_CH1N
{PB_14, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 2, 1)}, // TIM1_CH2N
{PB_15, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 3, 1)}, // TIM1_CH3N
{NC, NP, 0}
{PA_0, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM2_DISABLE, 1)}, // TIM2_CH1
{PA_1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM2_DISABLE, 2)}, // TIM2_CH2
{PA_2, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM2_DISABLE, 3)}, // TIM2_CH3
{PA_3, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM2_DISABLE, 4)}, // TIM2_CH4
{PA_6, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM3_DISABLE, 1)}, // TIM3_CH1
{PA_7, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM3_DISABLE, 2)}, // TIM3_CH2
{PB_0, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM3_DISABLE, 3)}, // TIM3_CH3
{PB_1, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM3_DISABLE, 4)}, // TIM3_CH4
{PB_6, TIM4, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM4_DISABLE, 1)}, // TIM4_CH1
{PB_7, TIM4, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM4_DISABLE, 2)}, // TIM4_CH2
{PB_8, TIM4, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM4_DISABLE, 3)}, // TIM4_CH3
{PB_9, TIM4, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM4_DISABLE, 4)}, // TIM4_CH4
{PA_8, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 1)}, // TIM1_CH1
{PA_9, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 2)}, // TIM1_CH2
{PA_10, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 3)}, // TIM1_CH3
{PA_11, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 4)}, // TIM1_CH4
{PB_13, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 1)}, // TIM1_CH1N
{PB_14, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 2)}, // TIM1_CH2N
{PA_15, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 3)}, // TIM1_CH3N
{NC, NP, 0, 0, 0}
};
#endif

2
variants/CH32V20x/CH32V203C6/variant_CH32V203C6.h
View File

@ -17,7 +17,7 @@
#define UART_MODULE_ENABLED
#define SPI_MODULE_ENABLED
#define I2C_MODULE_ENABLED
#define TIM_MODULE_ENABLED
/* CH32V203C6 Pins */
#define PA0 PIN_A0
#define PA1 PIN_A1

63
variants/CH32V20x/CH32V203C8/PeripheralPins.c
View File

@ -78,45 +78,30 @@ WEAK const PinMap PinMap_I2C_SCL[] = {
//*** TIM ***
#ifdef TIM_MODULE_ENABLED
WEAK const PinMap PinMap_TIM[] = {
{PA_0, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_NONE, 1, 0)}, // TIM2_CH1
{PA_0_ALT1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_PARTIAL_2, 1, 0)}, // TIM2_CH1
{PA_1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_DISABLE, 2, 0)}, // TIM2_CH2
{PA_1_ALT1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_PARTIAL_2, 2, 0)}, // TIM2_CH2
{PA_2, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_DISABLE, 3, 0)}, // TIM2_CH3
{PA_2_ALT1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_PARTIAL_1, 3, 0)}, // TIM2_CH3
{PA_3, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_DISABLE, 4, 0)}, // TIM2_CH4
{PA_3_ALT1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_PARTIAL_1, 4, 0)}, // TIM2_CH4
{PA_6, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM3_DISABLE, 1, 0)}, // TIM3_CH1
{PA_7, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 1, 1)}, // TIM1_CH1N
{PA_7_ALT1, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM3_DISABLE, 2, 0)}, // TIM3_CH2
{PA_8, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 1, 0)}, // TIM1_CH1
{PA_8_ALT1, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 1, 0)}, // TIM1_CH1
{PA_9, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 2, 0)}, // TIM1_CH2
{PA_9_ALT1, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 2, 0)}, // TIM1_CH2
{PA_10, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 3, 0)}, // TIM1_CH3
{PA_10_ALT1, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 3, 0)}, // TIM1_CH3
{PA_11, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 4, 0)}, // TIM1_CH4
{PA_11_ALT1, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 4, 0)}, // TIM1_CH4
{PA_15, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_PARTIAL_1, 1, 0)}, // TIM2_CH1
{PA_15_ALT1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_ENABLE, 1, 0)}, // TIM2_CH1
{PB_0, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 2, 1)}, // TIM1_CH2N
{PB_0_ALT1, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM3_DISABLE, 3, 0)}, // TIM3_CH3
{PB_0_ALT2, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM3_PARTIAL, 3, 0)}, // TIM3_CH3
{PB_1, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 3, 1)}, // TIM1_CH3N
{PB_1_ALT1, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM3_DISABLE, 4, 0)}, // TIM3_CH4
{PB_1_ALT2, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM3_PARTIAL, 4, 0)}, // TIM3_CH4
{PB_3, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_PARTIAL_1, 2, 0)}, // TIM2_CH2
{PB_3_ALT1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_ENABLE, 2, 0)}, // TIM2_CH2
{PB_4, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM3_PARTIAL, 1, 0)}, // TIM3_CH1
{PB_5, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM3_PARTIAL, 2, 0)}, // TIM3_CH2
{PB_10, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_PARTIAL_2, 3, 0)}, // TIM2_CH3
{PB_10_ALT1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_ENABLE, 3, 0)}, // TIM2_CH3
{PB_11, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_PARTIAL_2, 4, 0)}, // TIM2_CH4
{PB_11_ALT1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_ENABLE, 4, 0)}, // TIM2_CH4
{PB_13, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 1, 1)}, // TIM1_CH1N
{PB_14, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 2, 1)}, // TIM1_CH2N
{PB_15, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 3, 1)}, // TIM1_CH3N
{NC, NP, 0, 0}
{PA_0, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM2_DISABLE, 1)}, // TIM2_CH1
{PA_1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM2_DISABLE, 2)}, // TIM2_CH2
{PA_2, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM2_DISABLE, 3)}, // TIM2_CH3
{PA_3, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM2_DISABLE, 4)}, // TIM2_CH4
{PA_6, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM3_DISABLE, 1)}, // TIM3_CH1
{PA_7, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM3_DISABLE, 2)}, // TIM3_CH2
{PB_0, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM3_DISABLE, 3)}, // TIM3_CH3
{PB_1, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM3_DISABLE, 4)}, // TIM3_CH4
{PB_6, TIM4, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM4_DISABLE, 1)}, // TIM4_CH1
{PB_7, TIM4, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM4_DISABLE, 2)}, // TIM4_CH2
{PB_8, TIM4, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM4_DISABLE, 3)}, // TIM4_CH3
{PB_9, TIM4, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM4_DISABLE, 4)}, // TIM4_CH4
{PA_8, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 1)}, // TIM1_CH1
{PA_9, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 2)}, // TIM1_CH2
{PA_10, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 3)}, // TIM1_CH3
{PA_11, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 4)}, // TIM1_CH4
{PB_13, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 1)}, // TIM1_CH1N
{PB_14, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 2)}, // TIM1_CH2N
{PA_15, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 3)}, // TIM1_CH3N
{NC, NP, 0, 0, 0}
};
#endif

2
variants/CH32V20x/CH32V203C8/variant_CH32V203C8.h
View File

@ -17,7 +17,7 @@
#define UART_MODULE_ENABLED
#define SPI_MODULE_ENABLED
#define I2C_MODULE_ENABLED
#define TIM_MODULE_ENABLED
/* CH32V203C8 Pins */
#define PA0 PIN_A0
#define PA1 PIN_A1

61
variants/CH32V20x/CH32V203G8/PeripheralPins.c
View File

@ -76,44 +76,29 @@ WEAK const PinMap PinMap_I2C_SCL[] = {
//*** TIM ***
#ifdef TIM_MODULE_ENABLED
WEAK const PinMap PinMap_TIM[] = {
{PA_0, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_NONE, 1, 0)}, // TIM2_CH1
{PA_0_ALT1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_PARTIAL_2, 1, 0)}, // TIM2_CH1
{PA_1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_DISABLE, 2, 0)}, // TIM2_CH2
{PA_1_ALT1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_PARTIAL_2, 2, 0)}, // TIM2_CH2
{PA_2, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_DISABLE, 3, 0)}, // TIM2_CH3
{PA_2_ALT1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_PARTIAL_1, 3, 0)}, // TIM2_CH3
{PA_3, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_DISABLE, 4, 0)}, // TIM2_CH4
{PA_3_ALT1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_PARTIAL_1, 4, 0)}, // TIM2_CH4
{PA_6, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM3_DISABLE, 1, 0)}, // TIM3_CH1
{PA_7, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 1, 1)}, // TIM1_CH1N
{PA_7_ALT1, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM3_DISABLE, 2, 0)}, // TIM3_CH2
{PA_8, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 1, 0)}, // TIM1_CH1
{PA_8_ALT1, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 1, 0)}, // TIM1_CH1
{PA_9, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 2, 0)}, // TIM1_CH2
{PA_9_ALT1, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 2, 0)}, // TIM1_CH2
{PA_10, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 3, 0)}, // TIM1_CH3
{PA_10_ALT1, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 3, 0)}, // TIM1_CH3
{PA_11, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 4, 0)}, // TIM1_CH4
{PA_11_ALT1, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 4, 0)}, // TIM1_CH4
{PA_15, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_PARTIAL_1, 1, 0)}, // TIM2_CH1
{PA_15_ALT1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_ENABLE, 1, 0)}, // TIM2_CH1
{PB_0, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 2, 1)}, // TIM1_CH2N
{PB_0_ALT1, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM3_DISABLE, 3, 0)}, // TIM3_CH3
{PB_0_ALT2, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM3_PARTIAL, 3, 0)}, // TIM3_CH3
{PB_1, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 3, 1)}, // TIM1_CH3N
{PB_1_ALT1, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM3_DISABLE, 4, 0)}, // TIM3_CH4
{PB_1_ALT2, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM3_PARTIAL, 4, 0)}, // TIM3_CH4
{PB_3, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_PARTIAL_1, 2, 0)}, // TIM2_CH2
{PB_3_ALT1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_ENABLE, 2, 0)}, // TIM2_CH2
{PB_4, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM3_PARTIAL, 1, 0)}, // TIM3_CH1
{PB_5, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM3_PARTIAL, 2, 0)}, // TIM3_CH2
{PB_10, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_PARTIAL_2, 3, 0)}, // TIM2_CH3
{PB_10_ALT1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_ENABLE, 3, 0)}, // TIM2_CH3
{PB_11, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_PARTIAL_2, 4, 0)}, // TIM2_CH4
{PB_11_ALT1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_ENABLE, 4, 0)}, // TIM2_CH4
{PB_13, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 1, 1)}, // TIM1_CH1N
{PB_14, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 2, 1)}, // TIM1_CH2N
{PB_15, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 3, 1)}, // TIM1_CH3N
{PA_0, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM2_DISABLE, 1)}, // TIM2_CH1
{PA_1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM2_DISABLE, 2)}, // TIM2_CH2
{PA_2, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM2_DISABLE, 3)}, // TIM2_CH3
{PA_3, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM2_DISABLE, 4)}, // TIM2_CH4
{PA_6, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM3_DISABLE, 1)}, // TIM3_CH1
{PA_7, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM3_DISABLE, 2)}, // TIM3_CH2
{PB_0, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM3_DISABLE, 3)}, // TIM3_CH3
{PB_1, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM3_DISABLE, 4)}, // TIM3_CH4
{PB_6, TIM4, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM4_DISABLE, 1)}, // TIM4_CH1
{PB_7, TIM4, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM4_DISABLE, 2)}, // TIM4_CH2
{PB_8, TIM4, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM4_DISABLE, 3)}, // TIM4_CH3
{PB_9, TIM4, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM4_DISABLE, 4)}, // TIM4_CH4
{PA_8, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 1)}, // TIM1_CH1
{PA_9, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 2)}, // TIM1_CH2
{PA_10, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 3)}, // TIM1_CH3
{PA_11, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 4)}, // TIM1_CH4
{PB_13, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 1)}, // TIM1_CH1N
{PB_14, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 2)}, // TIM1_CH2N
{PA_15, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 3)}, // TIM1_CH3N
{NC, NP, 0, 0, 0}
};
#endif

1
variants/CH32V20x/CH32V203G8/variant_CH32V203G8.h
View File

@ -17,6 +17,7 @@
#define UART_MODULE_ENABLED
#define SPI_MODULE_ENABLED
#define I2C_MODULE_ENABLED
#define TIM_MODULE_ENABLED
/* CH32V203G8 Pins */
#define PA0 PIN_A0

63
variants/CH32V20x/CH32V203RB/PeripheralPins.c
View File

@ -76,45 +76,30 @@ WEAK const PinMap PinMap_I2C_SCL[] = {
//*** TIM ***
#ifdef TIM_MODULE_ENABLED
WEAK const PinMap PinMap_TIM[] = {
{PA_0, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_NONE, 1, 0)}, // TIM2_CH1
{PA_0_ALT1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_PARTIAL_2, 1, 0)}, // TIM2_CH1
{PA_1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_DISABLE, 2, 0)}, // TIM2_CH2
{PA_1_ALT1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_PARTIAL_2, 2, 0)}, // TIM2_CH2
{PA_2, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_DISABLE, 3, 0)}, // TIM2_CH3
{PA_2_ALT1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_PARTIAL_1, 3, 0)}, // TIM2_CH3
{PA_3, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_DISABLE, 4, 0)}, // TIM2_CH4
{PA_3_ALT1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_PARTIAL_1, 4, 0)}, // TIM2_CH4
{PA_6, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM3_DISABLE, 1, 0)}, // TIM3_CH1
{PA_7, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 1, 1)}, // TIM1_CH1N
{PA_7_ALT1, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM3_DISABLE, 2, 0)}, // TIM3_CH2
{PA_8, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 1, 0)}, // TIM1_CH1
{PA_8_ALT1, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 1, 0)}, // TIM1_CH1
{PA_9, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 2, 0)}, // TIM1_CH2
{PA_9_ALT1, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 2, 0)}, // TIM1_CH2
{PA_10, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 3, 0)}, // TIM1_CH3
{PA_10_ALT1, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 3, 0)}, // TIM1_CH3
{PA_11, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 4, 0)}, // TIM1_CH4
{PA_11_ALT1, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 4, 0)}, // TIM1_CH4
{PA_15, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_PARTIAL_1, 1, 0)}, // TIM2_CH1
{PA_15_ALT1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_ENABLE, 1, 0)}, // TIM2_CH1
{PB_0, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 2, 1)}, // TIM1_CH2N
{PB_0_ALT1, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM3_DISABLE, 3, 0)}, // TIM3_CH3
{PB_0_ALT2, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM3_PARTIAL, 3, 0)}, // TIM3_CH3
{PB_1, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 3, 1)}, // TIM1_CH3N
{PB_1_ALT1, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM3_DISABLE, 4, 0)}, // TIM3_CH4
{PB_1_ALT2, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM3_PARTIAL, 4, 0)}, // TIM3_CH4
{PB_3, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_PARTIAL_1, 2, 0)}, // TIM2_CH2
{PB_3_ALT1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_ENABLE, 2, 0)}, // TIM2_CH2
{PB_4, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM3_PARTIAL, 1, 0)}, // TIM3_CH1
{PB_5, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM3_PARTIAL, 2, 0)}, // TIM3_CH2
{PB_10, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_PARTIAL_2, 3, 0)}, // TIM2_CH3
{PB_10_ALT1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_ENABLE, 3, 0)}, // TIM2_CH3
{PB_11, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_PARTIAL_2, 4, 0)}, // TIM2_CH4
{PB_11_ALT1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_ENABLE, 4, 0)}, // TIM2_CH4
{PB_13, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 1, 1)}, // TIM1_CH1N
{PB_14, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 2, 1)}, // TIM1_CH2N
{PB_15, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 3, 1)}, // TIM1_CH3N
{NC, NP, 0}
{PA_0, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM2_DISABLE, 1)}, // TIM2_CH1
{PA_1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM2_DISABLE, 2)}, // TIM2_CH2
{PA_2, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM2_DISABLE, 3)}, // TIM2_CH3
{PA_3, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM2_DISABLE, 4)}, // TIM2_CH4
{PA_6, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM3_DISABLE, 1)}, // TIM3_CH1
{PA_7, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM3_DISABLE, 2)}, // TIM3_CH2
{PB_0, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM3_DISABLE, 3)}, // TIM3_CH3
{PB_1, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM3_DISABLE, 4)}, // TIM3_CH4
{PB_6, TIM4, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM4_DISABLE, 1)}, // TIM4_CH1
{PB_7, TIM4, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM4_DISABLE, 2)}, // TIM4_CH2
{PB_8, TIM4, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM4_DISABLE, 3)}, // TIM4_CH3
{PB_9, TIM4, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM4_DISABLE, 4)}, // TIM4_CH4
{PA_8, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 1)}, // TIM1_CH1
{PA_9, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 2)}, // TIM1_CH2
{PA_10, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 3)}, // TIM1_CH3
{PA_11, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 4)}, // TIM1_CH4
{PB_13, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 1)}, // TIM1_CH1N
{PB_14, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 2)}, // TIM1_CH2N
{PA_15, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 3)}, // TIM1_CH3N
{NC, NP, 0, 0, 0}
};
#endif

2
variants/CH32V20x/CH32V203RB/variant_CH32V203RB.h
View File

@ -17,7 +17,7 @@
#define UART_MODULE_ENABLED
#define SPI_MODULE_ENABLED
#define I2C_MODULE_ENABLED
#define TIM_MODULE_ENABLED
/* CH32V203RB Pins */
#define PA0 PIN_A0
#define PA1 PIN_A1

61
variants/CH32V30x/CH32V307VCT6/PeripheralPins.c
View File

@ -73,44 +73,29 @@ WEAK const PinMap PinMap_I2C_SCL[] = {
//*** TIM ***
#ifdef TIM_MODULE_ENABLED
WEAK const PinMap PinMap_TIM[] = {
{PA_0, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_NONE, 1, 0)}, // TIM2_CH1
{PA_0_ALT1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_PARTIAL_2, 1, 0)}, // TIM2_CH1
{PA_1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_DISABLE, 2, 0)}, // TIM2_CH2
{PA_1_ALT1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_PARTIAL_2, 2, 0)}, // TIM2_CH2
{PA_2, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_DISABLE, 3, 0)}, // TIM2_CH3
{PA_2_ALT1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_PARTIAL_1, 3, 0)}, // TIM2_CH3
{PA_3, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_DISABLE, 4, 0)}, // TIM2_CH4
{PA_3_ALT1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_PARTIAL_1, 4, 0)}, // TIM2_CH4
{PA_6, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM3_DISABLE, 1, 0)}, // TIM3_CH1
{PA_7, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 1, 1)}, // TIM1_CH1N
{PA_7_ALT1, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM3_DISABLE, 2, 0)}, // TIM3_CH2
{PA_8, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 1, 0)}, // TIM1_CH1
{PA_8_ALT1, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 1, 0)}, // TIM1_CH1
{PA_9, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 2, 0)}, // TIM1_CH2
{PA_9_ALT1, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 2, 0)}, // TIM1_CH2
{PA_10, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 3, 0)}, // TIM1_CH3
{PA_10_ALT1, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 3, 0)}, // TIM1_CH3
{PA_11, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 4, 0)}, // TIM1_CH4
{PA_11_ALT1, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 4, 0)}, // TIM1_CH4
{PA_15, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_PARTIAL_1, 1, 0)}, // TIM2_CH1
{PA_15_ALT1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_ENABLE, 1, 0)}, // TIM2_CH1
{PB_0, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 2, 1)}, // TIM1_CH2N
{PB_0_ALT1, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM3_DISABLE, 3, 0)}, // TIM3_CH3
{PB_0_ALT2, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM3_PARTIAL, 3, 0)}, // TIM3_CH3
{PB_1, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_PARTIAL, 3, 1)}, // TIM1_CH3N
{PB_1_ALT1, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM3_DISABLE, 4, 0)}, // TIM3_CH4
{PB_1_ALT2, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM3_PARTIAL, 4, 0)}, // TIM3_CH4
{PB_3, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_PARTIAL_1, 2, 0)}, // TIM2_CH2
{PB_3_ALT1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_ENABLE, 2, 0)}, // TIM2_CH2
{PB_4, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM3_PARTIAL, 1, 0)}, // TIM3_CH1
{PB_5, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM3_PARTIAL, 2, 0)}, // TIM3_CH2
{PB_10, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_PARTIAL_2, 3, 0)}, // TIM2_CH3
{PB_10_ALT1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_ENABLE, 3, 0)}, // TIM2_CH3
{PB_11, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_PARTIAL_2, 4, 0)}, // TIM2_CH4
{PB_11_ALT1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM2_ENABLE, 4, 0)}, // TIM2_CH4
{PB_13, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 1, 1)}, // TIM1_CH1N
{PB_14, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 2, 1)}, // TIM1_CH2N
{PB_15, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, GPIO_PULLUP, AFIO_TIM1_DISABLE, 3, 1)}, // TIM1_CH3N
{PA_0, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM2_DISABLE, 1)}, // TIM2_CH1
{PA_1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM2_DISABLE, 2)}, // TIM2_CH2
{PA_2, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM2_DISABLE, 3)}, // TIM2_CH3
{PA_3, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM2_DISABLE, 4)}, // TIM2_CH4
{PA_6, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM3_DISABLE, 1)}, // TIM3_CH1
{PA_7, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM3_DISABLE, 2)}, // TIM3_CH2
{PB_0, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM3_DISABLE, 3)}, // TIM3_CH3
{PB_1, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM3_DISABLE, 4)}, // TIM3_CH4
{PB_6, TIM4, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM4_DISABLE, 1)}, // TIM4_CH1
{PB_7, TIM4, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM4_DISABLE, 2)}, // TIM4_CH2
{PB_8, TIM4, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM4_DISABLE, 3)}, // TIM4_CH3
{PB_9, TIM4, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM4_DISABLE, 4)}, // TIM4_CH4
{PA_8, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 1)}, // TIM1_CH1
{PA_9, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 2)}, // TIM1_CH2
{PA_10, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 3)}, // TIM1_CH3
{PA_11, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 4)}, // TIM1_CH4
{PB_13, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 1)}, // TIM1_CH1N
{PB_14, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 2)}, // TIM1_CH2N
{PA_15, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 3)}, // TIM1_CH3N
{NC, NP, 0, 0, 0}
};
#endif

2
variants/CH32V30x/CH32V307VCT6/variant_CH32V307VCT6.h
View File

@ -18,9 +18,9 @@
#define DAC_MODULE_ENABLED
#define SPI_MODULE_ENABLED
#define I2C_MODULE_ENABLED
#define TIM_MODULE_ENABLED
/* CH32V307VCT6 Pins */
#define PA0 PIN_A0
#define PA1 PIN_A1
#define PA2 PIN_A2

3
variants/CH32X035/CH32X035G8U/variant_CH32X035G8U.h
View File

@ -16,7 +16,8 @@
#define ADC_MODULE_ENABLED
#define UART_MODULE_ENABLED
#define SPI_MODULE_ENABLED
// #define I2C_MODULE_ENABLED
#define I2C_MODULE_ENABLED
#define TIM_MODULE_ENABLED
/* CH32VX035G8 Pins */
#define PA0 PIN_A0