[AArch64] Regenerate arm64-vshuffle.ll test checks
Not quite ready to use the update script, but can clean it up slightly so the diffs aren't so great.
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			@ -1,9 +1,10 @@
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; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -mcpu=cyclone | FileCheck %s
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; CHECK-LABEL: test1
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; CHECK: movi.16b v[[REG0:[0-9]+]], #0
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define <8 x i1> @test1() {
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; CHECK-LABEL: test1:
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; CHECK:       ; %bb.0: ; %entry
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; CHECK-NEXT:    movi.16b v0, #0
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; CHECK-NEXT:    ret
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entry:
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  %Shuff = shufflevector <8 x i1> <i1 0, i1 1, i1 2, i1 3, i1 4, i1 5, i1 6,
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                                   i1 7>,
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			@ -23,10 +24,10 @@ entry:
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; CHECK:          .byte   0                       ; 0x0
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; CHECK:          .byte   0                       ; 0x0
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; CHECK:          .byte   0                       ; 0x0
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define <8 x i1>@test2() {
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; CHECK-LABEL: test2
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; CHECK: adrp    x[[REG2:[0-9]+]], lCPI1_0@PAGE
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; CHECK: ldr     d[[REG1:[0-9]+]], [x[[REG2]], lCPI1_0@PAGEOFF]
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define <8 x i1>@test2() {
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bb:
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  %Shuff = shufflevector <8 x i1> zeroinitializer,
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     <8 x i1> <i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 0, i1 0>,
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			@ -35,9 +36,11 @@ bb:
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  ret <8 x i1> %Shuff
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}
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; CHECK-LABEL: test3
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; CHECK: movi.4s v{{[0-9]+}}, #1
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define <16 x i1> @test3(i1* %ptr, i32 %v) {
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; CHECK-LABEL: test3:
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; CHECK:       ; %bb.0: ; %bb
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; CHECK-NEXT:    movi.4s v0, #1
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; CHECK-NEXT:    ret
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bb:
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  %Shuff = shufflevector <16 x i1> <i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 0, i1 0>, <16 x i1> undef,
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     <16 x i32> <i32 2, i32 undef, i32 6, i32 undef, i32 10, i32 12, i32 14,
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			@ -62,10 +65,10 @@ bb:
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; CHECK:         .byte   0                       ; 0x0
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; CHECK:         .byte   0                       ; 0x0
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; CHECK:         .byte   0                       ; 0x0
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define <16 x i1> @test4(i1* %ptr, i32 %v) {
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; CHECK-LABEL: _test4:
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; CHECK:         adrp    x[[REG3:[0-9]+]], lCPI3_0@PAGE
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; CHECK:         ldr     q[[REG2:[0-9]+]], [x[[REG3]], lCPI3_0@PAGEOFF]
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define <16 x i1> @test4(i1* %ptr, i32 %v) {
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bb:
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  %Shuff = shufflevector <16 x i1> zeroinitializer,
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     <16 x i1> <i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 0, i1 0, i1 0, i1 1,
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