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after fixing the i386 case 

Change-Id: If6fe0b6ec01f111115fb734fe31c0e152dbc165f
llvm-svn: 315311
This commit is contained in:
Uriel Korach 2017-10-10 13:43:09 +00:00
parent a17a7b619a
commit 059e211aa1
1 changed files with 2 additions and 2 deletions
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4
llvm/lib/Target/X86/X86ISelLowering.cpp
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@ -8028,8 +8028,8 @@ static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
// output register, mark it as legal and catch the pattern in instruction
// selection to avoid emitting extra insturctions (for zeroing upper bits).
if (SDValue Promoted = isTypePromotionOfi1ZeroUpBits(Op)) {
SDValue ZeroC = DAG.getConstant(0, dl, MVT::i64);
SDValue AllZeros = DAG.getSplatBuildVector(ResVT, dl, ZeroC);
SDValue ZeroC = DAG.getIntPtrConstant(0, dl);
SDValue AllZeros = getZeroVector(ResVT, Subtarget, DAG, dl);
return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, AllZeros, Promoted,
ZeroC);
}